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Commit 69493c17 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "usb: phy: Make cfg_ahb_clk optional"

parents fafc9051 45c86c2e

Documentation/devicetree/bindings/usb/msm-phy.txt

+24 −1
Original line number Diff line number Diff line
@@ -101,6 +101,10 @@ Required properties: 
   Required "supply-name" examples are:

	"vdd" : vdd supply for SSPHY digital circuit operation

	"core" : high-voltage analog supply for SSPHY

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "aux_clk" and "pipe_clk".

 - qcom,vdd-voltage-level: This property must be a list of three integer

   values (no, min, max) where each value represents either a voltage in

   microvolts or a value corresponding to voltage corner
@@ -119,6 +123,10 @@ Optional properties: 
 - reg: Additional register set of address and length to control QMP PHY are:

   "tcsr_usb3_dp_phymode" : top-level CSR register to be written to select

   super speed usb qmp phy.

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "cfg_ahb_clk", "phy_reset" and "phy_phy_reset".

 - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to

   the USB PHY and the controller must rely on external VBUS notification in

   order to manually relay the notification to the SSPHY.
@@ -138,6 +146,17 @@ Example: 
		vdda18-supply = <&pmd9635_l8>;

		qcom,vdd-voltage-level = <0 900000 1050000>;

		qcom,vbus-valid-override;



		clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,

			 <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			 <&clock_gcc clk_gcc_usb3_phy_reset>,

			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,

			 <&clock_gcc clk_ln_bb_clk1>,

			 <&clock_gcc clk_gcc_usb3_clkref_clk>;



		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",

			      "phy_phy_reset", "ref_clk_src", "ref_clk";

	};



QUSB2 High-Speed PHY
@@ -157,7 +176,7 @@ Required properties: 
 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "cfg_ahb_clk" and "phy_reset".

   property. Required clock is "phy_reset".

 - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.



Optional properties:
@@ -171,6 +190,10 @@ Optional properties: 
   allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w

   control in device mode. The reg-names property is required if the

   reg property is specified.

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. "cfg_ahb_clk", "ref_clk_src" and "ref_clk" are optional clocks.

 - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.

 - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode

   with value,reg pair.

Documentation/devicetree/bindings/usb/msm-ssusb.txt

+21 −0
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ Required properties : 
	"hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM.

	"pwr_event_irq" : Interrupt to controller for asynchronous events in LPM.

	Used for SS-USB power events.

 - clocks: a list of phandles to the controller clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk"

   and "utmi_clk".



Optional properties :

- reg: Additional registers
@@ -27,6 +32,10 @@ Optional properties : 
- interrupt-names : Optional interrupt resource entries are:

    "pmic_id_irq" : Interrupt from PMIC for external ID pin notification.

    "ss_phy_irq"  : Interrupt from super speed phy for wake up notification.

 - clocks: a list of phandles to the controller clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Optional clocks are "bus_aggr_clk" and "cfg_ahb_clk".

- qcom,charging-disabled: If present then battery charging using USB

  is disabled.

- vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode.
@@ -77,6 +86,18 @@ Example MSM USB3.0 controller device node : 
		qcom,msm_bus,vectors =

				<61 512 0 0>,

				<61 512 240000000 960000000>;



		clocks = <&clock_gcc clk_gcc_usb30_master_clk>,

			<&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,

			<&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,

			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			<&clock_gcc clk_gcc_usb30_sleep_clk>,

			<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			<&clock_gcc clk_cxo_dwc3_clk>;



		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

				"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";



		dwc3@f9200000 {

			compatible = "synopsys,dwc3";

			reg = <0xf9200000 0xfc000>;

drivers/usb/dwc3/dwc3-msm.c

+12 −5
Original line number Diff line number Diff line
@@ -2366,12 +2366,19 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) 
	if (IS_ERR(mdwc->bus_aggr_clk))

		mdwc->bus_aggr_clk = NULL;



	if (of_property_match_string(mdwc->dev->of_node,

				"clock-names", "cfg_ahb_clk") >= 0) {

		mdwc->cfg_ahb_clk = devm_clk_get(mdwc->dev, "cfg_ahb_clk");

		if (IS_ERR(mdwc->cfg_ahb_clk)) {

		dev_err(mdwc->dev, "failed to get cfg_ahb_clk\n");

			ret = PTR_ERR(mdwc->cfg_ahb_clk);

			mdwc->cfg_ahb_clk = NULL;

			if (ret != -EPROBE_DEFER)

				dev_err(mdwc->dev,

					"failed to get cfg_ahb_clk ret %d\n",

					ret);

			return ret;

		}

	}



	return 0;

}

drivers/usb/phy/phy-msm-qusb-v2.c

+11 −3
Original line number Diff line number Diff line
@@ -820,9 +820,17 @@ static int qusb_phy_probe(struct platform_device *pdev) 
	else

		clk_set_rate(qphy->ref_clk, 19200000);



	if (of_property_match_string(pdev->dev.of_node,

				"clock-names", "cfg_ahb_clk") >= 0) {

		qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");

	if (IS_ERR(qphy->cfg_ahb_clk))

		return PTR_ERR(qphy->cfg_ahb_clk);

		if (IS_ERR(qphy->cfg_ahb_clk)) {

			ret = PTR_ERR(qphy->cfg_ahb_clk);

			if (ret != -EPROBE_DEFER)

				dev_err(dev,

				"clk get failed for cfg_ahb_clk ret %d\n", ret);

			return ret;

		}

	}



	qphy->phy_reset = devm_clk_get(dev, "phy_reset");

	if (IS_ERR(qphy->phy_reset))

drivers/usb/phy/phy-msm-ssusb-qmp.c

+10 −7
Original line number Diff line number Diff line
@@ -547,14 +547,17 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev) 


	clk_set_rate(phy->aux_clk, clk_round_rate(phy->aux_clk, ULONG_MAX));



	if (of_property_match_string(pdev->dev.of_node,

				"clock-names", "cfg_ahb_clk") >= 0) {

		phy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");

		if (IS_ERR(phy->cfg_ahb_clk)) {

			ret = PTR_ERR(phy->cfg_ahb_clk);

		phy->cfg_ahb_clk = NULL;

			if (ret != -EPROBE_DEFER)

			dev_err(dev, "failed to get cfg_ahb_clk\n");

				dev_err(dev,

				"failed to get cfg_ahb_clk ret %d\n", ret);

			goto err;

		}

	}



	phy->pipe_clk = devm_clk_get(dev, "pipe_clk");

	if (IS_ERR(phy->pipe_clk)) {