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Commit 6917c7b9 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Initialise min/max frequencies before updating RPS registers 



The RPS register writing routines use the current value of min/max to
set certain limits and interrupt gating. If we set those afterwards, we
risk setting up the hw incorrectly and losing power management events,
and worse, trigger some internal assertions.

Reorder the calling sequences to be correct, and remove the then
unrequired clamping from inside set_rps(). And for a bonus, fix the bug
of calling gen6_set_rps() from Valleyview.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c5bd2bf6

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2756,7 +2756,7 @@ i915_max_freq_set(void *data, u64 val) 
	if (IS_VALLEYVIEW(dev)) {

	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv, val);

		val = vlv_freq_opcode(dev_priv, val);

		dev_priv->rps.max_delay = val;

		dev_priv->rps.max_delay = val;

		gen6_set_rps(dev, val);

		valleyview_set_rps(dev, val);

	} else {

	} else {

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		dev_priv->rps.max_delay = val;

		dev_priv->rps.max_delay = val;

drivers/gpu/drm/i915/i915_sysfs.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -339,15 +339,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, 
		DRM_DEBUG("User requested overclocking to %d\n",

		DRM_DEBUG("User requested overclocking to %d\n",

			  val * GT_FREQUENCY_MULTIPLIER);

			  val * GT_FREQUENCY_MULTIPLIER);





	dev_priv->rps.max_delay = val;



	if (dev_priv->rps.cur_delay > val) {

	if (dev_priv->rps.cur_delay > val) {

		if (IS_VALLEYVIEW(dev_priv->dev))

		if (IS_VALLEYVIEW(dev))

			valleyview_set_rps(dev_priv->dev, val);

			valleyview_set_rps(dev, val);

		else

		else

			gen6_set_rps(dev_priv->dev, val);

			gen6_set_rps(dev, val);

	}

	}





	dev_priv->rps.max_delay = val;



	mutex_unlock(&dev_priv->rps.hw_lock);

	mutex_unlock(&dev_priv->rps.hw_lock);





	return count;

	return count;
@@ -408,15 +408,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, 
		return -EINVAL;

		return -EINVAL;

	}

	}





	dev_priv->rps.min_delay = val;



	if (dev_priv->rps.cur_delay < val) {

	if (dev_priv->rps.cur_delay < val) {

		if (IS_VALLEYVIEW(dev))

		if (IS_VALLEYVIEW(dev))

			valleyview_set_rps(dev, val);

			valleyview_set_rps(dev, val);

		else

		else

			gen6_set_rps(dev_priv->dev, val);

			gen6_set_rps(dev, val);

	}

	}





	dev_priv->rps.min_delay = val;



	mutex_unlock(&dev_priv->rps.hw_lock);

	mutex_unlock(&dev_priv->rps.hw_lock);





	return count;

	return count;

drivers/gpu/drm/i915/intel_pm.c

+5 −14
Original line number Original line Diff line number Diff line
@@ -3414,26 +3414,19 @@ static void ironlake_disable_drps(struct drm_device *dev) 
 * ourselves, instead of doing a rmw cycle (which might result in us clearing

 * ourselves, instead of doing a rmw cycle (which might result in us clearing

 * all limits and the gpu stuck at whatever frequency it is at atm).

 * all limits and the gpu stuck at whatever frequency it is at atm).

 */

 */

static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)

static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)

{

{

	u32 limits;

	u32 limits;





	limits = 0;



	if (*val >= dev_priv->rps.max_delay)

		*val = dev_priv->rps.max_delay;

	limits |= dev_priv->rps.max_delay << 24;



	/* Only set the down limit when we've reached the lowest level to avoid

	/* Only set the down limit when we've reached the lowest level to avoid

	 * getting more interrupts, otherwise leave this clear. This prevents a

	 * getting more interrupts, otherwise leave this clear. This prevents a

	 * race in the hw when coming out of rc6: There's a tiny window where

	 * race in the hw when coming out of rc6: There's a tiny window where

	 * the hw runs at the minimal clock before selecting the desired

	 * the hw runs at the minimal clock before selecting the desired

	 * frequency, if the down threshold expires in that window we will not

	 * frequency, if the down threshold expires in that window we will not

	 * receive a down interrupt. */

	 * receive a down interrupt. */

	if (*val <= dev_priv->rps.min_delay) {

	limits = dev_priv->rps.max_delay << 24;

		*val = dev_priv->rps.min_delay;

	if (val <= dev_priv->rps.min_delay)

		limits |= dev_priv->rps.min_delay << 16;

		limits |= dev_priv->rps.min_delay << 16;

	}





	return limits;

	return limits;

}

}
@@ -3533,7 +3526,6 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 
void gen6_set_rps(struct drm_device *dev, u8 val)

void gen6_set_rps(struct drm_device *dev, u8 val)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 limits = gen6_rps_limits(dev_priv, &val);





	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(val > dev_priv->rps.max_delay);

	WARN_ON(val > dev_priv->rps.max_delay);
@@ -3556,7 +3548,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
	/* Make sure we continue to get interrupts

	/* Make sure we continue to get interrupts

	 * until we hit the minimum or maximum frequencies.

	 * until we hit the minimum or maximum frequencies.

	 */

	 */

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

		   gen6_rps_limits(dev_priv, val));





	POSTING_READ(GEN6_RPNSWREQ);

	POSTING_READ(GEN6_RPNSWREQ);
@@ -3620,8 +3613,6 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) 
{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;





	gen6_rps_limits(dev_priv, &val);



	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(val > dev_priv->rps.max_delay);

	WARN_ON(val > dev_priv->rps.max_delay);

	WARN_ON(val < dev_priv->rps.min_delay);

	WARN_ON(val < dev_priv->rps.min_delay);