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Commit 674366e9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v3.15-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:
 "These are fixes for a powerpc NULL pointer dereference, an OF
  interrupt mapping issue on some of the new host bridges, and a
  DesignWare iATU issue.

  Host bridge drivers
   - Fix OF interrupt mapping for DesignWare, R-Car, Tegra (Lucas Stach)
   - Fix DesignWare iATU programming (Mohit Kumar)

  Miscellaneous
    - Fix powerpc NULL dereference from list_for_each_entry() update (Mike Qiu)"

* tag 'pci-v3.15-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: tegra: Use new OF interrupt mapping when possible
  PCI: rcar: Use new OF interrupt mapping when possible
  PCI: designware: Use new OF interrupt mapping when possible
  PCI: designware: Fix iATU programming for cfg1, io and mem viewport
  PCI: designware: Fix comment for setting number of lanes
  powerpc/PCI: Fix NULL dereference in sys_pciconfig_iobase() list traversal
parents b81fd5ba f5d3352b

arch/powerpc/kernel/pci_64.c

+6 −4
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, 
			  unsigned long in_devfn)

{

	struct pci_controller* hose;

	struct pci_bus *bus = NULL;

	struct pci_bus *tmp_bus, *bus = NULL;

	struct device_node *hose_node;



	/* Argh ! Please forgive me for that hack, but that's the
@@ -229,10 +229,12 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, 
	 * used on pre-domains setup. We return the first match

	 */



	list_for_each_entry(bus, &pci_root_buses, node) {

		if (in_bus >= bus->number && in_bus <= bus->busn_res.end)

	list_for_each_entry(tmp_bus, &pci_root_buses, node) {

		if (in_bus >= tmp_bus->number &&

		    in_bus <= tmp_bus->busn_res.end) {

			bus = tmp_bus;

			break;

		bus = NULL;

		}

	}

	if (bus == NULL || bus->dev.of_node == NULL)

		return -ENODEV;

drivers/pci/host/pci-rcar-gen2.c

+7 −1
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_pci.h>

#include <linux/pci.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>
@@ -180,8 +181,13 @@ static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 
{

	struct pci_sys_data *sys = dev->bus->sysdata;

	struct rcar_pci_priv *priv = sys->private_data;

	int irq;



	return priv->irq;

	irq = of_irq_parse_and_map_pci(dev, slot, pin);

	if (!irq)

		irq = priv->irq;



	return irq;

}



#ifdef CONFIG_PCI_DEBUG

drivers/pci/host/pci-tegra.c

+6 −1
Original line number Diff line number Diff line
@@ -639,10 +639,15 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) 
static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)

{

	struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);

	int irq;



	tegra_cpuidle_pcie_irqs_in_use();



	return pcie->irq;

	irq = of_irq_parse_and_map_pci(pdev, slot, pin);

	if (!irq)

		irq = pcie->irq;



	return irq;

}



static void tegra_pcie_add_bus(struct pci_bus *bus)

drivers/pci/host/pcie-designware.c

+13 −7
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/module.h>

#include <linux/msi.h>

#include <linux/of_address.h>

#include <linux/of_pci.h>

#include <linux/pci.h>

#include <linux/pci_regs.h>

#include <linux/types.h>
@@ -490,7 +491,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
	dw_pci.nr_controllers = 1;

	dw_pci.private_data = (void **)&pp;



	pci_common_init(&dw_pci);

	pci_common_init_dev(pp->dev, &dw_pci);

	pci_assign_unassigned_resources();

#ifdef CONFIG_PCI_DOMAINS

	dw_pci.domain++;
@@ -520,13 +521,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) 
	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,

			  PCIE_ATU_VIEWPORT);

	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);

	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);

	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,

			  PCIE_ATU_LIMIT);

	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);

	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

}



static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -535,7 +536,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 
	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,

			  PCIE_ATU_VIEWPORT);

	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);

	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);

	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -543,6 +543,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 
	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);

	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),

			  PCIE_ATU_UPPER_TARGET);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

}



static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -551,7 +552,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 
	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,

			  PCIE_ATU_VIEWPORT);

	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);

	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);

	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -559,6 +559,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 
	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);

	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),

			  PCIE_ATU_UPPER_TARGET);

	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

}



static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -723,7 +724,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) 


	if (pp) {

		pp->root_bus_nr = sys->busnr;

		bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,

		bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,

					sys, &sys->resources);

	} else {

		bus = NULL;
@@ -736,8 +737,13 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) 
static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);

	int irq;



	irq = of_irq_parse_and_map_pci(dev, slot, pin);

	if (!irq)

		irq = pp->irq;



	return pp->irq;

	return irq;

}



static void dw_pcie_add_bus(struct pci_bus *bus)
@@ -764,7 +770,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
	u32 membase;

	u32 memlimit;



	/* set the number of lines as 4 */

	/* set the number of lanes */

	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);

	val &= ~PORT_LINK_MODE_MASK;

	switch (pp->lanes) {