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Commit 668b4ada authored by Tirumalesh Chalamarla's avatar Tirumalesh Chalamarla Committed by Will Deacon
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iommu/arm-smmu: ThunderX mis-extends 64bit registers 



The SMMU architecture defines two different behaviors when 64-bit
registers are written with 32-bit writes.  The first behavior causes
zero extension into the upper 32-bits.  The second behavior splits a
64-bit register into "normal" 32-bit register pairs.

On some buggy implementations, registers incorrectly zero extended
when they should instead behave as normal 32-bit register pairs.

Signed-off-by: default avatarTirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
[will: removed redundant macro parameters]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 077124c9

drivers/iommu/arm-smmu.c

+27 −23
Original line number Diff line number Diff line
@@ -70,6 +70,18 @@ 
		((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)	\

			? 0x400 : 0))



#ifdef CONFIG_64BIT

#define smmu_writeq	writeq_relaxed

#else

#define smmu_writeq(reg64, addr)				\

	do {							\

		u64 __val = (reg64);				\

		void __iomem *__addr = (addr);			\

		writel_relaxed(__val >> 32, __addr + 4);	\

		writel_relaxed(__val, __addr);			\

	} while (0)

#endif



/* Configuration registers */

#define ARM_SMMU_GR0_sCR0		0x0

#define sCR0_CLIENTPD			(1 << 0)
@@ -185,10 +197,8 @@ 
#define ARM_SMMU_CB_SCTLR		0x0

#define ARM_SMMU_CB_RESUME		0x8

#define ARM_SMMU_CB_TTBCR2		0x10

#define ARM_SMMU_CB_TTBR0_LO		0x20

#define ARM_SMMU_CB_TTBR0_HI		0x24

#define ARM_SMMU_CB_TTBR1_LO		0x28

#define ARM_SMMU_CB_TTBR1_HI		0x2c

#define ARM_SMMU_CB_TTBR0		0x20

#define ARM_SMMU_CB_TTBR1		0x28

#define ARM_SMMU_CB_TTBCR		0x30

#define ARM_SMMU_CB_S1_MAIR0		0x38

#define ARM_SMMU_CB_S1_MAIR1		0x3c
@@ -226,7 +236,7 @@ 
#define TTBCR2_SEP_SHIFT		15

#define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)



#define TTBRn_HI_ASID_SHIFT            16

#define TTBRn_ASID_SHIFT		48



#define FSR_MULTI			(1 << 31)

#define FSR_SS				(1 << 30)
@@ -695,6 +705,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
				       struct io_pgtable_cfg *pgtbl_cfg)

{

	u32 reg;

	u64 reg64;

	bool stage1;

	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;

	struct arm_smmu_device *smmu = smmu_domain->smmu;
@@ -738,22 +749,17 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 


	/* TTBRs */

	if (stage1) {

		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);

		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;

		reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);



		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);

		reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;

		reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);

		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];



		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;

		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);



		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];

		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;

		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);

	} else {

		reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);

		reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);

		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;

		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);

	}



	/* TTBCR */
@@ -1212,11 +1218,9 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, 


	/* ATS1 registers can only be written atomically */

	va = iova & ~0xfffUL;

#ifdef CONFIG_64BIT

	if (smmu->version == ARM_SMMU_V2)

		writeq_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);

		smmu_writeq(va, cb_base + ARM_SMMU_CB_ATS1PR);

	else

#endif

		writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);



	if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,