diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index f344b9e49198829617c9c3462f068595a1e0794f..ae2278fb3d1cfb13e8e4862d6e22b5018a2f24a9 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -69,6 +69,20 @@ Required properties:
 Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
   regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
+					panels in microseconds. Driver uses this number to adjust
+					the clock rate according to the expected transfer time.
+					Increasing this value would slow down the mdp processing
+					and can result in slower performance.
+					Decreasing this value can speed up the mdp processing,
+					but this can also impact power consumption.
+					As a rule this time should not be higher than the time
+					that would be expected with the processing at the
+					dsi link rate since anyways this would be the maximum
+					transfer time that could be achieved.
+					If ping pong split is enabled, this time should not be higher
+					than two times the dsi link rate time.
+					If the property is not specified, then the default value is 14000 us.
 
 Example:
 	mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -105,6 +119,8 @@ Example:
 		qcom,master-dsi;
 		qcom,sync-dual-dsi;
 
+		qcom,mdss-mdp-transfer-time-us = <12000>;
+
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&mdss_dsi_active>;
 		pinctrl-1 = <&mdss_dsi_suspend>;
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c9e7d7423d7f335ecc1cd9c1a784b17865c8d868
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -0,0 +1,472 @@
+Qualcomm Technologies, Inc. SDE KMS
+
+Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
+interface to different panel interfaces. SDE driver is the core of
+display subsystem which manage all data paths to different panel interfaces.
+
+Required properties
+- compatible: Must be "qcom,sde-kms"
+- reg: Offset and length of the register set for the device.
+- reg-names : Names to refer to register sets related to this device
+- clocks: List of Phandles for clock device nodes
+    needed by the device.
+- clock-names: List of clock names needed by the device.
+- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
+- vdd-supply: Phandle for vdd regulator device node.
+- interrupt-parent: Must be core interrupt controller.
+- interrupts: Interrupt associated with MDSS.
+- interrupt-controller: Mark the device node as an interrupt controller.
+- #interrupt-cells: Should be one. The first cell is interrupt number.
+- iommus: Specifies the SID's used by this context bank.
+- qcom,sde-sspp-type:		Array of strings for SDE source surface pipes type information.
+				A source pipe can be "vig", "rgb", "dma" or "cursor" type.
+				Number of xin ids defined should match the number of offsets
+				defined in property: qcom,sde-sspp-off.
+- qcom,sde-sspp-off:		Array of offset for SDE source surface pipes. The offsets
+				are calculated from register "mdp_phys" defined in
+				reg property + "sde-off". The number of offsets defined here should
+				reflect the amount of pipes that can be active in SDE for
+				this configuration.
+- qcom,sde-sspp-xin-id:		Array of VBIF clients ids (xins) corresponding
+				to the respective source pipes. Number of xin ids
+				defined should match the number of offsets
+				defined in property: qcom,sde-sspp-off.
+- qcom,sde-ctl-off:		Array of offset addresses for the available ctl
+				hw blocks within SDE, these offsets are
+				calculated from register "mdp_phys" defined in
+				reg property.  The number of ctl offsets defined
+				here should reflect the number of control paths
+				that can be configured concurrently on SDE for
+				this configuration.
+- qcom,sde-wb-off:		Array of offset addresses for the programmable
+				writeback blocks within SDE.
+- qcom,sde-wb-xin-id:		Array of VBIF clients ids (xins) corresponding
+				to the respective writeback. Number of xin ids
+				defined should match the number of offsets
+				defined in property: qcom,sde-wb-off.
+- qcom,sde-mixer-off:	 	Array of offset addresses for the available
+				mixer blocks that can drive data to panel
+				interfaces. These offsets are be calculated from
+				register "mdp_phys" defined in reg property.
+				The number of offsets defined should reflect the
+				amount of mixers that can drive data to a panel
+				interface.
+- qcom,sde-dspp-off: 		Array of offset addresses for the available dspp
+				blocks. These offsets are calculated from
+				register "mdp_phys" defined in reg property.
+- qcom,sde-pp-off:		Array of offset addresses for the available
+				pingpong blocks. These offsets are calculated
+				from register "mdp_phys" defined in reg property.
+- qcom,sde-pp-slave:		Array of flags indicating whether each ping pong
+				block may be configured as a pp slave.
+- qcom,sde-intf-off:		Array of offset addresses for the available SDE
+				interface blocks that can drive data to a
+				panel controller. The offsets are calculated
+				from "mdp_phys" defined in reg property. The number
+				of offsets defined should reflect the number of
+				programmable interface blocks available in hardware.
+
+Optional properties:
+- clock-rate:		List of clock rates in Hz.
+- clock-max-rate:	List of maximum clock rate in Hz that this device supports.
+- qcom,platform-supply-entries:	A node that lists the elements of the supply. There
+				can be more than one instance of this binding,
+				in which case the entry would be appended with
+				the supply entry index.
+				e.g. qcom,platform-supply-entry@0
+				-- reg: offset and length of the register set for the device.
+				-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+				-- qcom,supply-min-voltage: minimum voltage level (uV)
+				-- qcom,supply-max-voltage: maximum voltage level (uV)
+				-- qcom,supply-enable-load: load drawn (uA) from enabled supply
+				-- qcom,supply-disable-load: load drawn (uA) from disabled supply
+				-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,sde-sspp-src-size:	A u32 value indicates the address range for each sspp.
+- qcom,sde-mixer-size:		A u32 value indicates the address range for each mixer.
+- qcom,sde-ctl-size:		A u32 value indicates the address range for each ctl.
+- qcom,sde-dspp-size:		A u32 value indicates the address range for each dspp.
+- qcom,sde-intf-size:		A u32 value indicates the address range for each intf.
+- qcom,sde-dsc-size:		A u32 value indicates the address range for each dsc.
+- qcom,sde-cdm-size:		A u32 value indicates the address range for each cdm.
+- qcom,sde-pp-size:		A u32 value indicates the address range for each pingpong.
+- qcom,sde-wb-size:		A u32 value indicates the address range for each writeback.
+- qcom,sde-len:			A u32 entry for SDE address range.
+- qcom,sde-intf-max-prefetch-lines:	Array of u32 values for max prefetch lines on
+				each interface.
+- qcom,sde-sspp-linewidth:	A u32 value indicates the max sspp line width.
+- qcom,sde-mixer-linewidth:	A u32 value indicates the max mixer line width.
+- qcom,sde-wb-linewidth:	A u32 value indicates the max writeback line width.
+- qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.
+- qcom,sde-mixer-blendstages:	A u32 value indicates the max mixer blend stages for
+				alpha blending.
+- qcom,sde-qseed-type:		A string entry indicates qseed support on sspp and wb.
+				It supports "qssedv3" and "qseedv2" entries for qseed
+				type. By default "qseedv2" is used if this optional property
+				is not defined.
+- qcom,sde-csc-type:		A string entry indicates csc support on sspp and wb.
+				It supports "csc" and "csc-10bit" entries for csc
+				type.
+- qcom,sde-highest-bank-bit:	A u32 property to indicate GPU/Camera/Video highest memory
+				bank bit used for tile format buffers.
+- qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal
+				control feature is available on each source pipe.
+- qcom,sde-has-src-split:	Boolean property to indicate if source split
+				feature is available or not.
+- qcom,sde-has-mixer-gc:	Boolean property to indicate if mixer has gamma correction
+				feature available or not.
+- qcom,sde-has-cdp:		Boolean property to indicate if cdp feature is
+				available or not.
+- qcom,sde-sspp-clk-ctrl:	Array of offsets describing clk control
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the control
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off
+- qcom,sde-sspp-clk-status:	Array of offsets describing clk status
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the status
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off.
+- qcom,sde-sspp-danger-lut:	A 3 cell property, with a format of <linear, tile, nrt>,
+				indicating the danger luts on sspp.
+- qcom,sde-sspp-safe-lut:	A 3 cell property, with a format of <linear, tile, nrt>,
+				indicating the safe luts on sspp.
+- qcom,sde-sspp-max-rects:	Array of u32 values indicating maximum rectangles supported
+				on each sspp. This property is for multirect feature support.
+				Number of offsets defined should match the number of
+				offsets defined in property: qcom,sde-sspp-off.
+- qcom,sde-intf-type:		Array of string provides the interface type information.
+				Possible string values
+					"dsi" - dsi display interface
+					"dp" - Display Port interface
+					"hdmi" - HDMI display interface
+				An interface is considered as "none" if interface type
+				is not defined.
+- qcom,sde-off:			SDE offset from "mdp_phys" defined in reg property.
+- qcom,sde-cdm-off:	 	Array of offset addresses for the available
+				cdm blocks. These offsets will be calculated from
+				register "mdp_phys" defined in reg property.
+- qcom,sde-vbif-off:		Array of offset addresses for the available
+				vbif blocks. These offsets will be calculated from
+				register "vbif_phys" defined in reg property.
+- qcom,sde-vbif-size:		A u32 value indicates the vbif block address range.
+- qcom,sde-te-off:		A u32 offset indicates the te block offset on pingpong.
+				This offset is 0x0 by default.
+- qcom,sde-te2-off:		A u32 offset indicates the te2 block offset on pingpong.
+- qcom,sde-te-size:		A u32 value indicates the te block address range.
+- qcom,sde-te2-size:		A u32 value indicates the te2 block address range.
+- qcom,sde-dsc-off:	 	A u32 offset indicates the dsc block offset on pingpong.
+- qcom,sde-sspp-vig-blocks:	A node that lists the blocks inside the VIG hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the SSPP VIG contains that feature hardware.
+				e.g. qcom,sde-sspp-vig-blocks
+				-- qcom,sde-vig-csc-off: offset of CSC hardware
+				-- qcom,sde-vig-qseed-off: offset of QSEED hardware
+				-- qcom,sde-vig-pcc: offset and version of PCC hardware
+				-- qcom,sde-vig-hsic: offset and version of global PA adjustment
+				-- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware
+- qcom,sde-sspp-rgb-blocks:	A node that lists the blocks inside the RGB hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the SSPP RGB contains that feature hardware.
+				e.g. qcom,sde-sspp-vig-blocks
+				-- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware
+				-- qcom,sde-rgb-pcc: offset and version of PCC hardware
+- qcom,sde-dspp-blocks:		A node that lists the blocks inside the DSPP hardware. The
+				block entries will contain the offset and version of each
+				feature block. The presence of a block entry indicates that
+				the DSPP contains that feature hardware.
+				e.g. qcom,sde-dspp-blocks
+				-- qcom,sde-dspp-pcc: offset and version of PCC hardware
+				-- qcom,sde-dspp-gc: offset and version of GC hardware
+				-- qcom,sde-dspp-hsic: offset and version of global PA adjustment
+				-- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware
+				-- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware
+				-- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware
+				-- qcom,sde-dspp-dither: offset and version of dither hardware
+				-- qcom,sde-dspp-hist: offset and version of histogram hardware
+				-- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware
+- qcom,sde-mixer-blocks:	A node that lists the blocks inside the layer mixer hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the layer mixer contains that feature hardware.
+				e.g. qcom,sde-mixer-blocks
+				-- qcom,sde-mixer-gc: offset and version of mixer GC hardware
+- qcom,sde-dspp-ad-off:		Array of u32 offsets indicate the ad block offset from the
+				DSPP offset. Since AD hardware is represented as part of
+				DSPP block, the AD offsets must be offset from the
+				corresponding DSPP base.
+- qcom,sde-dspp-ad-version	A u32 value indicating the version of the AD hardware
+- qcom,sde-vbif-id:		Array of vbif ids corresponding to the
+				offsets defined in property: qcom,sde-vbif-off.
+- qcom,sde-vbif-default-ot-rd-limit:	A u32 value indicates the default read OT limit
+- qcom,sde-vbif-default-ot-wr-limit:	A u32 value indicates the default write OT limit
+- qcom,sde-vbif-dynamic-ot-rd-limit:	A series of 2 cell property, with a format
+				of (pps, OT limit), where pps is pixel per second and
+				OT limit is the read limit to apply if the given
+				pps is not exceeded.
+- qcom,sde-vbif-dynamic-ot-wr-limit:	A series of 2 cell property, with a format
+				of (pps, OT limit), where pps is pixel per second and
+				OT limit is the write limit to apply if the given
+				pps is not exceeded.
+- qcom,sde-wb-id:		Array of writeback ids corresponding to the
+				offsets defined in property: qcom,sde-wb-off.
+- qcom,sde-wb-clk-ctrl:		Array of 2 cell property describing clk control
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the control
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-wb-off
+- qcom,sde-dram-channels:	This represents the number of channels in the
+				Bus memory controller.
+- qcom,sde-num-nrt-paths:	Integer property represents the number of non-realtime
+				paths in each Bus Scaling Usecase. This value depends on
+				number of AXI ports that are dedicated to non-realtime VBIF
+				for particular chipset.
+				These paths must be defined after rt-paths in
+				"qcom,msm-bus,vectors-KBps" vector request.
+- qcom,sde-max-bw-low-kbps:	This value indicates the max bandwidth in Kbps
+				that can be supported without underflow.
+				This is a low bandwidth threshold which should
+				be applied in most scenarios to be safe from
+				underflows when unable to satisfy bandwidth
+				requirements.
+- qcom,sde-max-bw-high-kbps:	This value indicates the max bandwidth in Kbps
+				that can be supported without underflow.
+				This is a high bandwidth threshold which can be
+				applied in scenarios where panel interface can
+				be more tolerant to memory latency such as
+				command mode panels.
+
+Bus Scaling Subnodes:
+- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
+				mdss blocks.
+- qcom,sde-data-bus:		Property to provide Bus scaling for data bus access for
+				mdss blocks.
+
+Bus Scaling Data:
+- qcom,msm-bus,name:		String property describing client name.
+- qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
+				defined in the vectors property.
+- qcom,msm-bus,num-paths:	This represents the number of paths in each
+				Bus Scaling Usecase.
+- qcom,msm-bus,vectors-KBps:	* A series of 4 cell properties, with a format
+				of (src, dst, ab, ib) which is defined at
+				Documentation/devicetree/bindings/arm/msm/msm_bus.txt
+				* Current values of src & dst are defined at
+				include/linux/msm-bus-board.h
+
+
+Please refer to ../../interrupt-controller/interrupts.txt for a general
+description of interrupt bindings.
+
+Example:
+  mdss_mdp: qcom,mdss_mdp@900000 {
+    compatible = "qcom,sde-kms";
+    reg = <0x00900000 0x90000>,
+          <0x009b0000 0x1040>,
+          <0x009b8000 0x1040>;
+    reg-names = "mdp_phys",
+      "vbif_phys",
+      "vbif_nrt_phys";
+    clocks = <&clock_mmss clk_mdss_ahb_clk>,
+      <&clock_mmss clk_mdss_axi_clk>,
+      <&clock_mmss clk_mdp_clk_src>,
+      <&clock_mmss clk_mdss_mdp_vote_clk>,
+      <&clock_mmss clk_smmu_mdp_axi_clk>,
+      <&clock_mmss clk_mmagic_mdss_axi_clk>,
+      <&clock_mmss clk_mdss_vsync_clk>;
+    clock-names = "iface_clk",
+      "bus_clk",
+      "core_clk_src",
+      "core_clk",
+      "iommu_clk",
+      "mmagic_clk",
+      "vsync_clk";
+    clock-rate = <0>, <0>, <0>;
+    clock-max-rate= <0 320000000 0>;
+    mmagic-supply = <&gdsc_mmagic_mdss>;
+    vdd-supply = <&gdsc_mdss>;
+    interrupt-parent = <&intc>;
+    interrupts = <0 83 0>;
+    interrupt-controller;
+    #interrupt-cells = <1>;
+    iommus = <&mdp_smmu 0>;
+
+    qcom,sde-off = <0x1000>;
+    qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400
+		     0x00002600 0x00002800>;
+    qcom,sde-mixer-off = <0x00045000 0x00046000
+			0x00047000 0x0004a000>;
+    qcom,sde-dspp-off = <0x00055000 0x00057000>;
+    qcom,sde-dspp-ad-off = <0x24000 0x22800>;
+    qcom,sde-dspp-ad-version = <0x00030000>;
+    qcom,sde-wb-off = <0x00066000>;
+    qcom,sde-wb-xin-id = <6>;
+    qcom,sde-intf-off = <0x0006b000 0x0006b800
+			0x0006c000 0x0006c800>;
+    qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
+    qcom,sde-pp-off = <0x00071000 0x00071800
+			  0x00072000 0x00072800>;
+    qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>;
+    qcom,sde-cdm-off = <0x0007a200>;
+    qcom,sde-dsc-off = <0x00081000 0x00081400>;
+    qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
+
+    qcom,sde-sspp-type = "vig", "vig", "vig",
+			      "vig", "rgb", "rgb",
+			      "rgb", "rgb", "dma",
+			      "dma", "cursor", "cursor";
+
+    qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000
+		      0x0000b000 0x00015000 0x00017000
+		      0x00019000 0x0001b000 0x00025000
+		      0x00027000 0x00035000 0x00037000>;
+
+    qcom,sde-sspp-xin-id = <0 4 8
+			12 1 5
+			9 13 2
+			10 7 7>;
+
+    /* offsets are relative to "mdp_phys + qcom,sde-off */
+    qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+			  <0x3b0 16>;
+    qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+			  <0x3b0 16>;
+    qcom,sde-mixer-linewidth = <2560>;
+    qcom,sde-sspp-linewidth = <2560>;
+    qcom,sde-mixer-blendstages = <0x7>;
+    qcom,sde-highest-bank-bit = <0x2>;
+    qcom,sde-panic-per-pipe;
+    qcom,sde-has-cdp;
+    qcom,sde-has-src-split;
+    qcom,sde-sspp-src-size = <0x100>;
+    qcom,sde-mixer-size = <0x100>;
+    qcom,sde-ctl-size = <0x100>;
+    qcom,sde-dspp-size = <0x100>;
+    qcom,sde-intf-size = <0x100>;
+    qcom,sde-dsc-size = <0x100>;
+    qcom,sde-cdm-size = <0x100>;
+    qcom,sde-pp-size = <0x100>;
+    qcom,sde-wb-size = <0x100>;
+    qcom,sde-len = <0x100>;
+    qcom,sde-wb-linewidth = <2560>;
+    qcom,sde-sspp-scale-size = <0x100>;
+    qcom,sde-mixer-blendstages = <0x8>;
+    qcom,sde-qseed-type = "qseedv2";
+    qcom,sde-highest-bank-bit = <15>;
+    qcom,sde-has-mixer-gc;
+    qcom,sde-sspp-max-rects = <1 1 1 1
+				1 1 1 1
+				1 1
+				1 1>;
+    qcom,sde-te-off = <0x100>;
+    qcom,sde-te2-off = <0x100>;
+    qcom,sde-te-size = <0xffff>;
+    qcom,sde-te2-size = <0xffff>;
+
+    qcom,sde-wb-id = <2>;
+    qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+    qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>;
+    qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>;
+
+    qcom,sde-vbif-off = <0 0>;
+    qcom,sde-vbif-id = <0 1>;
+    qcom,sde-vbif-default-ot-rd-limit = <32>;
+    qcom,sde-vbif-default-ot-wr-limit = <16>;
+    qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>,
+        <124416000 4>, <248832000 16>;
+    qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
+        <124416000 4>, <248832000 16>;
+
+    qcom,sde-dram-channels = <2>;
+    qcom,sde-num-nrt-paths = <1>;
+
+    qcom,sde-max-bw-high-kbps = <9000000>;
+    qcom,sde-max-bw-low-kbps = <9000000>;
+
+    qcom,sde-sspp-vig-blocks {
+        qcom,sde-vig-csc-off = <0x320>;
+        qcom,sde-vig-qseed-off = <0x200>;
+        /* Offset from vig top, version of HSIC */
+        qcom,sde-vig-hsic = <0x200 0x00010000>;
+        qcom,sde-vig-memcolor = <0x200 0x00010000>;
+        qcom,sde-vig-pcc = <0x1780 0x00010000>;
+    };
+
+    qcom,sde-sspp-rgb-blocks {
+        qcom,sde-rgb-scaler-off = <0x200>;
+        qcom,sde-rgb-pcc = <0x380 0x00010000>;
+    };
+
+    qcom,sde-dspp-blocks {
+        qcom,sde-dspp-pcc = <0x1700 0x00010000>;
+        qcom,sde-dspp-gc = <0x17c0 0x00010000>;
+        qcom,sde-dspp-hsic = <0x0 0x00010000>;
+        qcom,sde-dspp-memcolor = <0x0 0x00010000>;
+        qcom,sde-dspp-sixzone = <0x0 0x00010000>;
+        qcom,sde-dspp-gamut = <0x1600 0x00010000>;
+        qcom,sde-dspp-dither = <0x0 0x00010000>;
+        qcom,sde-dspp-hist = <0x0 0x00010000>;
+        qcom,sde-dspp-vlut = <0x0 0x00010000>;
+    };
+
+    qcom,sde-mixer-blocks {
+        qcom,sde-mixer-gc = <0x3c0 0x00010000>;
+    };
+
+    qcom,platform-supply-entries {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       qcom,platform-supply-entry@0 {
+           reg = <0>;
+           qcom,supply-name = "vdd";
+           qcom,supply-min-voltage = <0>;
+           qcom,supply-max-voltage = <0>;
+           qcom,supply-enable-load = <0>;
+           qcom,supply-disable-load = <0>;
+           qcom,supply-pre-on-sleep = <0>;
+           qcom,supply-post-on-sleep = <0>;
+           qcom,supply-pre-off-sleep = <0>;
+           qcom,supply-post-off-sleep = <0>;
+        };
+    };
+
+    qcom,sde-data-bus {
+        qcom,msm-bus,name = "mdss_sde";
+        qcom,msm-bus,num-cases = <3>;
+        qcom,msm-bus,num-paths = <3>;
+        qcom,msm-bus,vectors-KBps =
+            <22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
+            <22 512 0 6400000>, <23 512 0 6400000>,
+                <25 512 0 6400000>,
+            <22 512 0 6400000>, <23 512 0 6400000>,
+                <25 512 0 6400000>;
+    };
+
+    qcom,sde-reg-bus {
+        /* Reg Bus Scale Settings */
+        qcom,msm-bus,name = "mdss_reg";
+        qcom,msm-bus,num-cases = <4>;
+        qcom,msm-bus,num-paths = <1>;
+        qcom,msm-bus,active-only;
+        qcom,msm-bus,vectors-KBps =
+              <1 590 0 0>,
+              <1 590 0 76800>,
+              <1 590 0 160000>,
+              <1 590 0 320000>;
+        };
+  };
diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
new file mode 100644
index 0000000000000000000000000000000000000000..48a2c6c78297ba1f662532153c7c1ec3216f6dee
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -0,0 +1,96 @@
+Qualcomm Technologies, Inc.
+
+mdss-dsi is the master DSI device which supports multiple DSI host controllers
+that are compatible with MIPI display serial interface specification.
+
+DSI Controller:
+Required properties:
+- compatible:           Should be "qcom,dsi-ctrl-hw-v<version>". Supported
+			versions include 1.4 and 2.0.
+			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0
+			And for dsi phy driver:
+			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0,
+			qcom,dsi-phy-v4.0
+- reg:                  Base address and length of DSI controller's memory
+			mapped regions.
+- reg-names:            A list of strings that name the list of regs.
+			"dsi_ctrl" - DSI controller memory region.
+			"mmss_misc" - MMSS misc memory region.
+- cell-index:           Specifies the controller instance.
+- clocks:               Clocks required for DSI controller operation.
+- clock-names:          Names of the clocks corresponding to handles. Following
+			clocks are required:
+			"mdp_core_clk"
+			"iface_clk"
+			"core_mmss_clk"
+			"bus_clk"
+			"byte_clk"
+			"pixel_clk"
+			"core_clk"
+			"byte_clk_rcg"
+			"pixel_clk_rcg"
+- gdsc-supply:		phandle to gdsc regulator node.
+- vdda-supply:		phandle to vdda regulator node.
+- vcca-supply:		phandle to vcca regulator node.
+- interrupt-parent	phandle to the interrupt parent device node.
+- interrupts:		The interrupt signal from the DSI block.
+
+Bus Scaling Data:
+- qcom,msm-bus,name:		String property describing MDSS client.
+- qcom,msm-bus,num-cases:	This is the number of bus scaling use cases
+				defined in the vectors property. This must be
+				set to <2> for MDSS DSI driver where use-case 0
+				is used to remove BW votes from the system. Use
+				case 1 is used to generate bandwidth requestes
+				when sending command packets.
+- qcom,msm-bus,num-paths:	This represents number of paths in each bus
+				scaling usecase. This value depends on number of
+				AXI master ports dedicated to MDSS for
+				particular chipset.
+- qcom,msm-bus,vectors-KBps:	A series of 4 cell properties, with a format
+				of (src, dst, ab, ib) which is defined at
+				Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
+				DSI driver should always set average bandwidth
+				(ab) to 0 and always use instantaneous
+				bandwidth(ib) values.
+
+Optional properties:
+- label:                  String to describe controller.
+- qcom,platform-te-gpio:  Specifies the gpio used for TE.
+- qcom,dsi-display-active: Current active display
+- qcom,dsi-ctrl: handle to dsi controller device
+- qcom,dsi-phy: handle to dsi phy device
+- qcom,dsi-manager:       Specifies dsi manager is present
+- qcom,dsi-display:       Specifies dsi display is present
+- qcom,hdmi-display:      Specifies hdmi is present
+- qcom,dp-display:        Specified dp is present
+- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
+					a particular "type" of DSI module. The module "types"
+					can be "core", "ctrl", and "phy". Within the same type,
+					there can be more than one instance of this binding,
+					in which case the entry would be appended with the
+					supply entry index.
+					e.g. qcom,ctrl-supply-entry@0
+					-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+					-- qcom,supply-min-voltage: minimum voltage level (uV)
+					-- qcom,supply-max-voltage: maximum voltage level (uV)
+					-- qcom,supply-enable-load: load drawn (uA) from enabled supply
+					-- qcom,supply-disable-load: load drawn (uA) from disabled supply
+					-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+					-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+					-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+					-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
+					panels in microseconds. Driver uses this number to adjust
+					the clock rate according to the expected transfer time.
+					Increasing this value would slow down the mdp processing
+					and can result in slower performance.
+					Decreasing this value can speed up the mdp processing,
+					but this can also impact power consumption.
+					As a rule this time should not be higher than the time
+					that would be expected with the processing at the
+					dsi link rate since anyways this would be the maximum
+					transfer time that could be achieved.
+					If ping pong split enabled, this time should not be higher
+					than two times the dsi link rate time.
+					If the property is not specified, then the default value is 14000 us.
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/drm/msm/sde-wb.txt b/Documentation/devicetree/bindings/drm/msm/sde-wb.txt
new file mode 100644
index 0000000000000000000000000000000000000000..863b334e438a704f8ff9396e6bf2ac3f02b0224b
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/sde-wb.txt
@@ -0,0 +1,23 @@
+QTI Snapdragon Display Engine (SDE) writeback display
+
+Required properties:
+- compatible:		"qcom,wb-display"
+
+Optional properties:
+- cell-index:		Index of writeback device instance.
+			Default to 0 if not specified.
+- label:		String to describe this writeback display.
+			Default to "unknown" if not specified.
+
+Example:
+
+/ {
+	...
+
+	sde_wb: qcom,wb-display {
+		compatible = "qcom,wb-display";
+		cell-index = <2>;
+		label = "wb_display";
+	};
+
+};
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index b676efe97b8b5c0bd1ff5f7badb944f2ed4afb14..4fd0c2ecbc6e4966fa47995dabf79bcd50966bae 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -628,6 +628,7 @@ Example:
 		qcom,mdss-dsi-underflow-color = <0xff>;
 		qcom,mdss-dsi-bl-min-level = <1>;
 		qcom,mdss-dsi-bl-max-level = < 15>;
+		qcom,mdss-brightness-max-level = <255>;
 		qcom,mdss-dsi-interleave-mode = <0>;
 		qcom,mdss-dsi-panel-type = "dsi_video_mode";
 		qcom,mdss-dsi-te-check-enable;
diff --git a/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi b/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi
index 70156b1f8493ef5d3fe53031d5215a415f284a41..533861b4422a6d7ededae736c68f0b2d336fc115 100644
--- a/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi
@@ -325,7 +325,7 @@
 	};
 };
 
-#include "msm8996-mdss-panels.dtsi"
+#include "msm8996-sde-display.dtsi"
 
 &dsi_hx8379a_fwvga_truly_vid {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
diff --git a/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi b/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi
index a7482bcce112fcd93af4d5289965d2d80e3db883..bfc6f210a0bbc5a9aa668b6dbebd88bd255f9eb7 100644
--- a/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi
@@ -325,7 +325,7 @@
 	};
 };
 
-#include "msm8996-mdss-panels.dtsi"
+#include "msm8996-sde-display.dtsi"
 
 &dsi_hx8379a_fwvga_truly_vid {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
@@ -341,9 +341,6 @@
 	qcom,mdss-pref-prim-intf = "dsi";
 };
 
-&mdss_dsi {
-	hw-config = "single_dsi";
-};
 
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_hx8379a_fwvga_truly_vid>;
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-jdi-1080p-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-jdi-1080p-video.dtsi
index cecd8d3cf2a091546536531f03f67c5c2c421a8d..6f3f63d27d7034231cc2f6bbb9d57f28d176ac6a 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-jdi-1080p-video.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-jdi-1080p-video.dtsi
@@ -10,8 +10,14 @@
  * GNU General Public License for more details.
  */
 
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------
+ */
 &mdss_mdp {
-	dsi_jdi_1080_vid: qcom,mdss_dsi_jdi_1080p_video {
+	dsi_jdi_1080p_video: qcom,mdss_dsi_jdi_1080p_video {
 		qcom,mdss-dsi-panel-name = "jdi 1080p video mode dsi panel";
 		qcom,mdss-dsi-panel-type = "dsi_video_mode";
 		qcom,mdss-dsi-panel-framerate = <60>;
@@ -31,19 +37,21 @@
 		qcom,mdss-dsi-v-top-border = <0>;
 		qcom,mdss-dsi-v-bottom-border = <0>;
 		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
 		qcom,mdss-dsi-underflow-color = <0xff>;
 		qcom,mdss-dsi-border-color = <0>;
 		qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 55 00
-			15 01 00 00 00 00 02 53 2C
-			15 01 00 00 00 00 02 35 00
-			05 01 00 00 78 00 02 29 00
-			05 01 00 00 78 00 02 11 00];
+				15 01 00 00 00 00 02 53 2C
+				15 01 00 00 00 00 02 35 00
+				05 01 00 00 78 00 02 29 00
+				05 01 00 00 78 00 02 11 00];
 		qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00
 				 05 01 00 00 79 00 02 10 00];
 		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
 		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
 		qcom,mdss-dsi-h-sync-pulse = <0>;
 		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
 		qcom,mdss-dsi-bllp-eof-power-mode;
 		qcom,mdss-dsi-bllp-power-mode;
 		qcom,mdss-dsi-lane-0-state;
@@ -51,9 +59,9 @@
 		qcom,mdss-dsi-lane-2-state;
 		qcom,mdss-dsi-lane-3-state;
 		qcom,mdss-dsi-panel-timings =
-				[e7 36 24 00 66 6a 2a 3a 2d 03 04 00];
-		qcom,mdss-dsi-t-clk-post = <0x04>;
-		qcom,mdss-dsi-t-clk-pre = <0x1b>;
+					[ce 2e 1e 00 5a 5c 24 30 24 03 04 00];
+		qcom,mdss-dsi-t-clk-post = <0x0d>;
+		qcom,mdss-dsi-t-clk-pre = <0x2f>;
 		qcom,mdss-dsi-bl-min-level = <1>;
 		qcom,mdss-dsi-bl-max-level = <4095>;
 		qcom,mdss-dsi-dma-trigger = "trigger_sw";
@@ -61,6 +69,8 @@
 		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
 		qcom,mdss-pan-physical-width-dimension = <61>;
-		qcom,mdss-pan-physical-height-dimension = <110>;
+		qcom,mdss-pan-physical-heigth-dimenstion = <110>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,ulps-enabled;
 	};
 };
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
index aeeaaa7ca6fb19d05a241b05dcd28ef7be48b9d0..ebd73ceaa8ce9a4df5afcc589f9db51673fa3aac 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
@@ -61,35 +61,31 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,ulps-enabled;
-		qcom,mdss-dsi-panel-hdr-enabled;
-		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
-			17000 15500 30000 8000 3000>;
-		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
-		qcom,mdss-dsi-panel-blackness-level = <3230>;
-		qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10
-			15 01 00 00 00 00 02 fb 01
-			15 01 00 00 00 00 02 ba 03
-			15 01 00 00 00 00 02 e5 01
-			15 01 00 00 00 00 02 35 00
-			15 01 00 00 00 00 02 bb 10
-			15 01 00 00 00 00 02 b0 03
-			15 01 00 00 00 00 02 ff e0
-			15 01 00 00 00 00 02 fb 01
-			15 01 00 00 00 00 02 6b 3d
-			15 01 00 00 00 00 02 6c 3d
-			15 01 00 00 00 00 02 6d 3d
-			15 01 00 00 00 00 02 6e 3d
-			15 01 00 00 00 00 02 6f 3d
-			15 01 00 00 00 00 02 35 02
-			15 01 00 00 00 00 02 36 72
-			15 01 00 00 00 00 02 37 10
-			15 01 00 00 00 00 02 08 c0
-			15 01 00 00 00 00 02 ff 24
-			15 01 00 00 00 00 02 fb 01
-			15 01 00 00 00 00 02 c6 06
-			15 01 00 00 00 00 02 ff 10
-			05 01 00 00 78 00 02 11 00
-			05 01 00 00 32 00 02 29 00];
+		qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 10
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 ba 03
+			15 01 00 00 10 00 02 e5 01
+			15 01 00 00 10 00 02 35 00
+			15 01 00 00 10 00 02 bb 10
+			15 01 00 00 10 00 02 b0 03
+			15 01 00 00 10 00 02 ff e0
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 6b 3d
+			15 01 00 00 10 00 02 6c 3d
+			15 01 00 00 10 00 02 6d 3d
+			15 01 00 00 10 00 02 6e 3d
+			15 01 00 00 10 00 02 6f 3d
+			15 01 00 00 10 00 02 35 02
+			15 01 00 00 10 00 02 36 72
+			15 01 00 00 10 00 02 37 10
+			15 01 00 00 10 00 02 08 c0
+			15 01 00 00 10 00 02 ff 24
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 c6 06
+			15 01 00 00 10 00 02 9d 30 /* Enable IMGSWAP */
+			15 01 00 00 10 00 02 ff 10
+			05 01 00 00 a0 00 02 11 00
+			05 01 00 00 a0 00 02 29 00];
 
 		qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
 			05 01 00 00 3c 00 02 10 00];
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi
index 68dabd2fe41ca6fd47adfd446efd0578c8a16a72..401cb21b4adaed02489380073e6c054a872b878e 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi
@@ -13,7 +13,9 @@
 &mdss_mdp {
 	dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd {
 		qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel";
+		qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
 		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-destination = "display_1";
 		qcom,mdss-dsi-panel-framerate = <60>;
 		qcom,mdss-dsi-panel-clockrate = <850000000>;
 		qcom,mdss-dsi-virtual-channel-id = <0>;
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
index 2a5b8a2487305191449877806941a1190fec710f..94620f007dd917a84f1aee082a8d1941f41b7009 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -31,7 +31,7 @@
 		qcom,mdss-dsi-border-color = <0>;
 		qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00
 			05 01 00 00 02 00 02 29 00];
-		qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00
+		qcom,mdss-dsi-pre-off-command = [05 01 00 00 02 00 02 28 00
 				 05 01 00 00 a0 00 02 10 00];
 		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
 		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi
index 36e3022e4d1f8d08518bb0e4ecbd3def79727575..e5a5ee8f08d9b3a1101abbab0339afe3f9423f81 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -19,9 +19,9 @@
 		qcom,mdss-dsi-stream = <0>;
 		qcom,mdss-dsi-panel-width = <640>;
 		qcom,mdss-dsi-panel-height = <480>;
-		qcom,mdss-dsi-h-front-porch = <6>;
-		qcom,mdss-dsi-h-back-porch = <6>;
-		qcom,mdss-dsi-h-pulse-width = <2>;
+		qcom,mdss-dsi-h-front-porch = <8>;
+		qcom,mdss-dsi-h-back-porch = <8>;
+		qcom,mdss-dsi-h-pulse-width = <8>;
 		qcom,mdss-dsi-h-sync-skew = <0>;
 		qcom,mdss-dsi-v-back-porch = <6>;
 		qcom,mdss-dsi-v-front-porch = <6>;
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-toshiba-720p-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-toshiba-720p-video.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..191a3fba8ce65da5da56fa58b562f3e1b81348d4
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/dsi-panel-toshiba-720p-video.dtsi
@@ -0,0 +1,100 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_tosh_720_vid: qcom,mdss_dsi_toshiba_720p_video {
+		qcom,mdss-dsi-panel-name = "toshiba 720p video mode dsi panel";
+		qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-destination = "display_1";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <1280>;
+		qcom,mdss-dsi-h-front-porch = <144>;
+		qcom,mdss-dsi-h-back-porch = <32>;
+		qcom,mdss-dsi-h-pulse-width = <12>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <3>;
+		qcom,mdss-dsi-v-front-porch = <9>;
+		qcom,mdss-dsi-v-pulse-width = <4>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-on-command = [23 01 00 00 0a 00 02 b0 00
+				23 01 00 00 0a 00 02 b2 00
+				23 01 00 00 0a 00 02 b3 0c
+				23 01 00 00 0a 00 02 b4 02
+				29 01 00 00 00 00 06 c0 40 02 7f c8 08
+				29 01 00 00 00 00 10 c1 00 a8 00 00 00
+					00 00 9d 08 27 00 00 00 00 00
+				29 01 00 00 00 00 06 c2 00 00 09 00 00
+				23 01 00 00 0a 00 02 c3 04
+				29 01 00 00 00 00 04 c4 4d 83 00
+				29 01 00 00 00 00 0b c6 12 00 08 71 00
+					00 00 80 00 04
+				23 01 00 00 0a 00 02 c7 22
+				29 01 00 00 00 00 05 c8 4c 0c 0c 0c
+				29 01 00 00 00 00 0e c9 00 40 00 16 32
+					2e 3a 43 3e 3c 45 79 3f
+				29 01 00 00 00 00 0e ca 00 46 1a 23 21
+					1c 25 31 2d 49 5f 7f 3f
+				29 01 00 00 00 00 0e cb 00 4c 20 3a 42
+					40 47 4b 42 3e 46 7e 3f
+				29 01 00 00 00 00 0e cc 00 41 19 21 1d
+					14 18 1f 1d 25 3f 73 3f
+				29 01 00 00 00 00 0e cd 23 79 5a 5f 57
+					4c 51 51 45 3f 4b 7f 3f
+				29 01 00 00 00 00 0e ce 00 40 14 20 1a
+					0e 0e 13 08 00 05 46 1c
+				29 01 00 00 00 00 04 d0 6a 64 01
+				29 01 00 00 00 00 03 d1 77 d4
+				23 01 00 00 0a 00 02 d3 33
+				29 01 00 00 00 00 03 d5 0f 0f
+				29 01 00 00 00 00 07 d8 34 64 23 25 62 32
+				29 01 00 00 00 00 0c de 10 7b 11 0a 00
+					00 00 00 00 00 00
+				29 01 00 00 00 00 09 fd 04 55 53 00 70 ff 10 73
+				23 01 00 00 0a 00 02 e2 00
+				05 01 00 00 78 00 02 11 00
+				05 01 00 00 32 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
+				 05 01 00 00 78 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [b0 23 1b 00 94 93 1e 25
+						15 03 04 00];
+		qcom,mdss-dsi-t-clk-post = <0x04>;
+		qcom,mdss-dsi-t-clk-pre = <0x1b>;
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-pan-enable-dynamic-fps;
+		qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
+		qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
+	};
+};
diff --git a/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi
index 165c7de039e53f508ea79ea5cb4f47ec2dfee77e..6fafb8b38d065bd5f7e61efe22a91110fc5dcca1 100644
--- a/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi
@@ -340,6 +340,7 @@
 	};
 };
 
+#include "msm8996-sde-display.dtsi"
 #include "msm8996-mdss-panels.dtsi"
 
 &mdss_mdp {
@@ -350,6 +351,21 @@
 	hw-config = "split_dsi";
 };
 
+&mdss_hdmi_tx {
+	pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active",
+				"hdmi_active", "hdmi_sleep";
+	pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_suspend
+						&mdss_hdmi_cec_suspend>;
+	pinctrl-1 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active
+						&mdss_hdmi_cec_suspend>;
+	pinctrl-2 = <&mdss_hdmi_hpd_active &mdss_hdmi_cec_active
+						&mdss_hdmi_ddc_suspend>;
+	pinctrl-3 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active
+						&mdss_hdmi_cec_active>;
+	pinctrl-4 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend
+						&mdss_hdmi_cec_suspend>;
+};
+
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_sharp_video>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -370,19 +386,8 @@
 	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
 };
 
-&mdss_hdmi_tx {
-	pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active",
-				"hdmi_active", "hdmi_sleep";
-	pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_suspend
-						&mdss_hdmi_cec_suspend>;
-	pinctrl-1 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active
-						&mdss_hdmi_cec_suspend>;
-	pinctrl-2 = <&mdss_hdmi_hpd_active &mdss_hdmi_cec_active
-						&mdss_hdmi_ddc_suspend>;
-	pinctrl-3 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active
-						&mdss_hdmi_cec_active>;
-	pinctrl-4 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend
-						&mdss_hdmi_cec_suspend>;
+&ibb_regulator {
+	qcom,qpnp-ibb-discharge-resistor = <32>;
 };
 
 &labibb {
@@ -390,11 +395,24 @@
 	qcom,qpnp-labibb-mode = "lcd";
 };
 
+&dsi_tosh_720_vid {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,cont-splash-enabled;
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
+	qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>;
+};
+
 &dsi_dual_sharp_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
 };
 
 &dsi_dual_nt35597_video {
@@ -402,6 +420,7 @@
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
 };
 
 &dsi_dual_nt35597_cmd {
@@ -411,6 +430,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,partial-update-enabled = "single_roi";
 	qcom,panel-roi-alignment = <720 128 720 64 720 64>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
 };
 
 &dsi_nt35950_4k_dsc_cmd {
@@ -502,6 +522,17 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
+&dsi_jdi_1080p_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,cont-splash-enabled;
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
+	qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>;
+};
+
 &pm8994_gpios {
 	gpio@c700 { /* GPIO 8 - WLAN_EN */
 		qcom,mode = <1>;		/* Digital output*/
diff --git a/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi b/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi
index 5c62766b1a269b63a3dd2dffdad397947dbe1095..c2667b49fedbe36d2a8995aca7ece5fc124b43ff 100644
--- a/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi
@@ -11,7 +11,7 @@
  */
 
 #include "msm8996-pinctrl.dtsi"
-#include "msm8996-mdss-panels.dtsi"
+#include "msm8996-sde-display.dtsi"
 #include "msm8996-camera-sensor-dtp.dtsi"
 #include "msm8996-wsa881x.dtsi"
 
@@ -467,10 +467,6 @@
 	status = "disabled";
 };
 
-&mdss_dsi {
-	hw-config = "split_dsi";
-};
-
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_r69007_wqxga_cmd>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
diff --git a/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi b/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi
index baecf4b8574edd8730ea2835be69050ec97e72d0..86bc8099c4d65255f2a5d7c797be3131568e4077 100644
--- a/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi
@@ -587,6 +587,7 @@
 	status = "ok";
 };
 
+#include "msm8996-sde-display.dtsi"
 #include "msm8996-mdss-panels.dtsi"
 
 &mdss_mdp {
diff --git a/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi b/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi
index dae7306cdd074e74dca530bc70d45e9aa6a7b55d..571e67a7dd938d4f32251ad67c69091ae4969835 100644
--- a/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi
@@ -294,16 +294,12 @@
 	};
 };
 
-#include "msm8996-mdss-panels.dtsi"
+#include "msm8996-sde-display.dtsi"
 
 &mdss_mdp {
 	qcom,mdss-pref-prim-intf = "dsi";
 };
 
-&mdss_dsi {
-	hw-config = "split_dsi";
-};
-
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_jdi_4k_nofbc_video>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
diff --git a/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi
index bfb85274846fa81cbbf4b22de697322853f94bd0..18a0f29e4d8af2ec9036091c773e83f06c3423f5 100644
--- a/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi
@@ -30,7 +30,9 @@
 #include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
 #include "dsi-panel-sharp-1080p-cmd.dtsi"
 #include "dsi-panel-sharp-dsc-4k-video.dtsi"
+#include "dsi-panel-toshiba-720p-video.dtsi"
 #include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
+#include "dsi-panel-jdi-1080p-video.dtsi"
 
 &soc {
 	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
@@ -127,6 +129,16 @@
 			qcom,supply-disable-load = <80>;
 			qcom,supply-post-on-sleep = <20>;
 		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdd";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <857000>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <0>;
+		};
 	};
 };
 
diff --git a/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi
index 27d3eea5bc20486b3ab29e2cce96bd8f01bc9e00..ab10a71d1fd76322a077a012f84ba6e1bbdc6a92 100644
--- a/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi
@@ -336,12 +336,17 @@
 	};
 };
 
+#include "msm8996-sde-display.dtsi"
 #include "msm8996-mdss-panels.dtsi"
 
 &mdss_mdp {
 	qcom,mdss-pref-prim-intf = "dsi";
 };
 
+&mdss_hdmi {
+	status = "ok";
+};
+
 &mdss_dsi {
 	hw-config = "split_dsi";
 };
@@ -366,23 +371,44 @@
 	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
 };
 
+&ibb_regulator {
+	qcom,qpnp-ibb-discharge-resistor = <32>;
+};
+
 &labibb {
 	status = "ok";
 	qcom,qpnp-labibb-mode = "lcd";
 };
 
+&dsi_tosh_720_vid {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,cont-splash-enabled;
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
+	qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>;
+};
+
 &dsi_dual_sharp_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
 };
 
 &dsi_sharp_1080_cmd {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,cont-splash-enabled;
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
+	qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>;
 };
 
 &dsi_dual_nt35597_video {
@@ -390,6 +416,7 @@
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
 };
 
 &dsi_dual_nt35597_cmd {
@@ -399,6 +426,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,partial-update-enabled = "single_roi";
 	qcom,panel-roi-alignment = <720 128 720 64 720 64>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
 };
 
 &dsi_nt35950_4k_dsc_cmd {
@@ -483,6 +511,17 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
+&dsi_jdi_1080p_video {
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,cont-splash-enabled;
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,platform-reset-gpio = <&tlmm 8 0>;
+	qcom,platform-bklight-en-gpio = <&pm8994_gpios 14 0>;
+	qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>;
+};
+
 /{
 	mtp_batterydata: qcom,battery-data {
 		qcom,batt-id-range-pct = <15>;
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3f81da7c3ebcb134275a1de9b6534d1a82a62f11
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi
@@ -0,0 +1,352 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "dsi-panel-toshiba-720p-video.dtsi"
+#include "dsi-panel-sharp-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35597-dsc-wqxga-video.dtsi"
+#include "dsi-panel-jdi-dualmipi-video.dtsi"
+#include "dsi-panel-jdi-dualmipi-cmd.dtsi"
+#include "dsi-panel-jdi-4k-dualmipi-video-nofbc.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-cmd.dtsi"
+#include "dsi-panel-nt35597-dsc-wqxga-cmd.dtsi"
+#include "dsi-panel-hx8379a-truly-fwvga-video.dtsi"
+#include "dsi-panel-r69007-dualdsi-wqxga-cmd.dtsi"
+#include "dsi-panel-jdi-1080p-video.dtsi"
+#include "dsi-panel-sharp-1080p-cmd.dtsi"
+
+&soc {
+	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1800000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "lab";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+		};
+
+		qcom,panel-supply-entry@2 {
+			reg = <2>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1800000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1800000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdd";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <857000>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <0>;
+		};
+	};
+
+	dsi_dual_sharp_video_1: qcom,dsi-display@0 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_sharp_video";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+		qcom,platform-reset-gpio = <&tlmm 8 0>;
+
+		qcom,dsi-panel = <&dsi_dual_sharp_video>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+		qcom,dsi-display-active;
+	};
+
+	single_dsi_sim_vid: qcom,dsi-display@1 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_sim";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_sim_vid>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
+
+	dsi_toshiba_720p_vid: qcom,dsi-display@2 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_toshiba_720p";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_tosh_720_vid>;
+		vddio-supply = <&pm8994_l14>;
+		vdd-supply = <&pm8994_l19>;
+	};
+
+	dsi_jdi_1080p_vid: qcom,dsi-display@3 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_jdi_1080p";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+		qcom,dsi-panel = <&dsi_jdi_1080p_video>;
+		vddio-supply = <&pm8994_l14>;
+	};
+
+	dsi_sharp_fhd_cmd: qcom,dsi-display@4 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_sharp_1080p";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+		qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
+		vddio-supply = <&pm8994_l14>;
+		vdd-supply = <&pm8994_l19>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
+
+	sde_wb: qcom,wb-display@0 {
+		compatible = "qcom,wb-display";
+		cell-index = <0>;
+		label = "wb_display";
+	};
+
+	dsi_dual_nt35597_cmd_1: qcom,dsi-display@5 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_nt35597_cmd";
+		qcom,display-type = "primary";
+
+		/* dsi1/dsi0 swapped due to IMGSWAP */
+		qcom,dsi-ctrl = <&mdss_dsi1 &mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
+
+	dsi_dual_nt35597_video_1: qcom,dsi-display@6 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_nt35597_video";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_dual_nt35597_video>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
+};
+
+&mdss_mdp {
+	connectors = <&dsi_dual_sharp_video_1
+		&sde_wb>;
+};
+
+&dsi_dual_sharp_video {
+	qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0
+			23 20 06 09 05 03 04 a0
+			23 20 06 09 05 03 04 a0
+			23 20 06 09 05 03 04 a0
+			23 2e 06 08 05 03 04 a0];
+};
+
+&dsi_dual_jdi_cmd {
+	qcom,mdss-dsi-panel-timings-8996 = [22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 2c 05 08 04 03 04 a0];
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "te_signal_check";
+};
+
+&dsi_dual_jdi_video {
+	qcom,mdss-dsi-panel-timings-8996 = [22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 1e 06 08 04 03 04 a0
+			22 2c 05 08 04 03 04 a0];
+};
+
+&dsi_dual_nt35597_video {
+	qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 18 07 08 04 03 04 a0];
+};
+
+&dsi_dual_nt35597_cmd {
+	qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 1e 07 08 05 03 04 a0
+		23 18 07 08 04 03 04 a0];
+};
+
+&dsi_nt35597_dsc_video {
+	qcom,mdss-dsi-panel-timings-8996 = [20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 12 05 06 03 13 04 a0];
+};
+
+&dsi_nt35597_dsc_cmd {
+	qcom,mdss-dsi-panel-timings-8996 = [20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 1d 05 07 03 03 04 a0
+		20 12 05 06 03 13 04 a0];
+};
+
+&dsi_dual_jdi_4k_nofbc_video {
+	qcom,mdss-dsi-panel-timings-8996 = [
+		2c 27 0e 10 0a 03 04 a0
+		2c 27 0e 10 0a 03 04 a0
+		2c 27 0e 10 0a 03 04 a0
+		2c 27 0e 10 0a 03 04 a0
+		2c 32 0e 0f 0a 03 04 a0];
+};
+
+&dsi_hx8379a_fwvga_truly_vid {
+	qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0
+		23 20 06 09 05 03 04 a0
+		23 20 06 09 05 03 04 a0
+		23 20 06 09 05 03 04 a0
+		23 2e 06 08 05 03 04 a0];
+};
+
+&dsi_r69007_wqxga_cmd {
+	qcom,mdss-dsi-panel-timings-8996 = [23 1f 07 09 05 03 04 a0
+		23 1f 07 09 05 03 04 a0
+		23 1f 07 09 05 03 04 a0
+		23 1f 07 09 05 03 04 a0
+		23 19 08 08 05 03 04 a0];
+};
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8aebac3b0e22d111b68fd1ef0b9e49d18a9cab2a
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
@@ -0,0 +1,546 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	mdss_mdp: qcom,mdss_mdp@900000 {
+		compatible = "qcom,sde-kms";
+		reg = <0x00900000 0x90000>,
+		      <0x009b0000 0x1040>,
+		      <0x009b8000 0x1040>;
+		reg-names = "mdp_phys",
+			"vbif_phys",
+			"vbif_nrt_phys";
+
+		/* clock and supply entries */
+		clocks = <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mdss_axi_clk>,
+			 <&clock_mmss clk_mdp_clk_src>,
+			 <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_smmu_mdp_axi_clk>,
+			 <&clock_mmss clk_smmu_mdp_ahb_clk>,
+			 <&clock_mmss clk_smmu_rot_axi_clk>,
+			 <&clock_mmss clk_smmu_rot_ahb_clk>,
+			 <&clock_mmss clk_mmagic_mdss_axi_clk>,
+			 <&clock_mmss clk_mdss_vsync_clk>;
+		clock-names = "iface_clk",
+			"bus_clk",
+			"core_clk_src",
+			"core_clk",
+			"iommu_mdp_axi_clk",
+			"iommu_mdp_ahb_clk",
+			"iommu_rot_axi_clk",
+			"iommu_rot_ahb_clk",
+			"mmagic_clk",
+			"vsync_clk";
+		clock-rate = <0 0 412500000 412500000 0 0 0 0>;
+		clock-max-rate = <0 0 412500000 412500000 0 0 0 0>;
+
+		/* interrupt config */
+		interrupt-parent = <&intc>;
+		interrupts = <0 83 0>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		iommus = <&mdp_smmu 0>;
+
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-ctl-off = <0x2000 0x2200 0x2400
+				     0x2600 0x2800>;
+		qcom,sde-mixer-off = <0x45000 0x46000 0x47000
+				      0x48000 0x49000 0x4a000>;
+		qcom,sde-dspp-off = <0x55000 0x57000>;
+		qcom,sde-dspp-ad-off = <0x24000 0x22800>;
+		qcom,sde-dspp-ad-version = <0x00030000>;
+		qcom,sde-wb-off = <0x66000>;
+		qcom,sde-wb-id = <2>;
+		qcom,sde-wb-xin-id = <6>;
+		qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+		qcom,sde-intf-off = <0x6b000 0x6b800
+					0x6c000 0x6c800>;
+		qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
+		qcom,sde-pp-off = <0x71000 0x71800
+					  0x72000 0x72800 0x73000>;
+		qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>;
+		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>;
+		qcom,sde-cdm-off = <0x7a200>;
+		qcom,sde-dsc-off = <0x10000 0x10000 0x0 0x0 0x0>;
+		qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
+
+		qcom,sde-sspp-type = "vig", "vig", "vig",
+				      "vig", "rgb", "rgb",
+				      "rgb", "rgb", "dma",
+				      "dma", "cursor", "cursor";
+
+		qcom,sde-sspp-off = <0x5000 0x7000 0x9000
+				      0xb000 0x15000 0x17000
+				      0x19000 0x1b000 0x25000
+				      0x27000 0x35000 0x37000>;
+
+		qcom,sde-sspp-xin-id = <0 4 8
+					12 1 5
+					9 13 2
+					10 7 7>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+				  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+				  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+				  <0x3b0 16>;
+		qcom,sde-qseed-type = "qseedv2";
+		qcom,sde-csc-type = "csc";
+		qcom,sde-mixer-linewidth = <2560>;
+		qcom,sde-sspp-linewidth = <2560>;
+		qcom,sde-mixer-blendstages = <0x7>;
+		qcom,sde-highest-bank-bit = <0x2>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-has-cdp;
+		qcom,sde-has-src-split;
+		qcom,sde-max-bw-low-kbps = <9600000>;
+		qcom,sde-max-bw-high-kbps = <9600000>;
+		qcom,sde-dram-channels = <2>;
+		qcom,sde-num-nrt-paths = <1>;
+
+		qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>;
+		qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>;
+
+		qcom,sde-vbif-off = <0 0>;
+		qcom,sde-vbif-size = <0x1040>;
+		qcom,sde-vbif-id = <0 1>;
+		qcom,sde-vbif-default-ot-rd-limit = <32>;
+		qcom,sde-vbif-default-ot-wr-limit = <16>;
+		qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>,
+			<124416000 4>, <248832000 16>;
+		qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
+			<124416000 4>, <248832000 16>;
+
+		mmagic-supply = <&gdsc_mmagic_mdss>;
+		vdd-supply = <&gdsc_mdss>;
+
+		qcom,sde-sspp-vig-blocks {
+			qcom,sde-vig-csc-off = <0x320>;
+			qcom,sde-vig-qseed-off = <0x200>;
+			/* Offset from vig top, version of HSIC */
+			qcom,sde-vig-hsic = <0x200 0x00010007>;
+			qcom,sde-vig-memcolor = <0x200 0x00010007>;
+			qcom,sde-vig-pcc = <0x1780 0x00010007>;
+		};
+
+		qcom,sde-sspp-rgb-blocks {
+			qcom,sde-rgb-scaler-off = <0x200>;
+			qcom,sde-rgb-pcc = <0x380 0x00010007>;
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-pcc = <0x1700 0x00010007>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010007>;
+			qcom,sde-dspp-hsic = <0x0 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x0 0x00010007>;
+			qcom,sde-dspp-sixzone = <0x0 0x00010007>;
+			qcom,sde-dspp-gamut = <0x1600 0x00010007>;
+			qcom,sde-dspp-dither = <0x0 0x00010007>;
+			qcom,sde-dspp-hist = <0x0 0x00010007>;
+			qcom,sde-dspp-vlut = <0x0 0x00010007>;
+		};
+
+		qcom,sde-mixer-blocks {
+			qcom,sde-mixer-gc = <0x3c0 0x00010007>;
+		};
+
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "mmagic";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+
+			qcom,platform-supply-entry@1 {
+				reg = <1>;
+				qcom,supply-name = "vdd";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
+			compatible = "qcom,smmu_mdp_unsec";
+			iommus = <&mdp_smmu 0>;
+		};
+
+		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+			compatible = "qcom,smmu_rot_unsec";
+			iommus = <&rot_smmu 0>;
+		};
+
+		smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
+			compatible = "qcom,smmu_mdp_sec";
+			iommus = <&mdp_smmu 1>;
+		};
+
+		smmu_rot_sec: qcom,smmu_rot_sec_cb {
+			compatible = "qcom,smmu_rot_sec";
+			iommus = <&rot_smmu 1>;
+		};
+
+		/* data and reg bus scale settings */
+		qcom,sde-data-bus {
+			qcom,msm-bus,name = "mdss_sde";
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <3>;
+			qcom,msm-bus,vectors-KBps =
+				<22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
+				<22 512 0 6400000>, <23 512 0 6400000>,
+					<25 512 0 6400000>,
+				<22 512 0 6400000>, <23 512 0 6400000>,
+					<25 512 0 6400000>;
+		};
+
+		qcom,sde-reg-bus {
+			qcom,msm-bus,name = "mdss_reg";
+			qcom,msm-bus,num-cases = <4>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,active-only;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>,
+				<1 590 0 160000>,
+				<1 590 0 320000>;
+		};
+	};
+
+	mdss_dsi0: qcom,mdss_dsi_ctrl0@994000 {
+		compatible = "qcom,dsi-ctrl-hw-v1.4";
+		label = "dsi-ctrl-0";
+		cell-index = <0>;
+		reg =   <0x994000 0x400>,
+			<0x828000 0x108>;
+		reg-names = "dsi_ctrl", "mmss_misc";
+
+		gdsc-supply = <&gdsc_mdss>;
+		vdda-supply = <&pm8994_l2>;
+		vcca-supply = <&pm8994_l28>;
+
+		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mmss_misc_ahb_clk>,
+			 <&clock_mmss clk_mdss_axi_clk>,
+			 <&clock_mmss clk_mdss_byte0_clk>,
+			 <&clock_mmss clk_mdss_pclk0_clk>,
+			 <&clock_mmss clk_mdss_esc0_clk>,
+			 <&clock_mmss clk_byte0_clk_src>,
+			 <&clock_mmss clk_pclk0_clk_src>;
+
+		clock-names = "mdp_core_clk", "iface_clk",
+			"core_mmss_clk", "bus_clk",
+			"byte_clk", "pixel_clk", "core_clk",
+			"byte_clk_rcg", "pixel_clk_rcg";
+
+		/* axi bus scale settings */
+		qcom,msm-bus,name = "mdss_dsi0";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<22 512 0 0>,
+			<22 512 0 1000>;
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vcca";
+				qcom,supply-min-voltage = <925000>;
+				qcom,supply-max-voltage = <925000>;
+				qcom,supply-enable-load = <17000>;
+				qcom,supply-disable-load = <32>;
+			};
+
+			qcom,ctrl-supply-entry@1 {
+				reg = <0>;
+				qcom,supply-name = "vdda";
+				qcom,supply-min-voltage = <1250000>;
+				qcom,supply-max-voltage = <1250000>;
+				qcom,supply-enable-load = <18160>;
+				qcom,supply-disable-load = <1>;
+			};
+
+		};
+	};
+
+	mdss_dsi1: qcom,mdss_dsi_ctrl1@996000 {
+		compatible = "qcom,dsi-ctrl-hw-v1.4";
+		label = "dsi-ctrl-1";
+		cell-index = <1>;
+		reg =   <0x996000 0x400>,
+			<0x828000 0x108>;
+		reg-names = "dsi_ctrl", "mmss_misc";
+
+		gdsc-supply = <&gdsc_mdss>;
+		vdda-supply = <&pm8994_l2>;
+		vcca-supply = <&pm8994_l28>;
+
+		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mmss_misc_ahb_clk>,
+			 <&clock_mmss clk_mdss_axi_clk>,
+			 <&clock_mmss clk_mdss_byte1_clk>,
+			 <&clock_mmss clk_mdss_pclk1_clk>,
+			 <&clock_mmss clk_mdss_esc1_clk>,
+			 <&clock_mmss clk_byte1_clk_src>,
+			 <&clock_mmss clk_pclk1_clk_src>;
+		clock-names = "mdp_core_clk", "iface_clk",
+			"core_mmss_clk", "bus_clk",
+			"byte_clk", "pixel_clk", "core_clk",
+			"byte_clk_rcg", "pixel_clk_rcg";
+
+		/* axi bus scale settings */
+		qcom,msm-bus,name = "mdss_dsi1";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<22 512 0 0>,
+			<22 512 0 1000>;
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <5 0>;
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda";
+				qcom,supply-min-voltage = <1250000>;
+				qcom,supply-max-voltage = <1250000>;
+				qcom,supply-enable-load = <18160>;
+				qcom,supply-disable-load = <1>;
+			};
+
+			qcom,ctrl-supply-entry@1 {
+				reg = <0>;
+				qcom,supply-name = "vcca";
+				qcom,supply-min-voltage = <925000>;
+				qcom,supply-max-voltage = <925000>;
+				qcom,supply-enable-load = <18050>;
+				qcom,supply-disable-load = <32>;
+			};
+		};
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy0@994400 {
+		compatible = "qcom,dsi-phy-v4.0";
+		label = "dsi-phy-0";
+		cell-index = <0>;
+		reg = <0x994400 0x588>;
+		reg-names = "dsi_phy";
+
+		gdsc-supply = <&gdsc_mdss>;
+		vdda-supply = <&pm8994_l2>;
+
+		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mmss_misc_ahb_clk>,
+			 <&clock_mmss clk_mdss_axi_clk>;
+		clock-names = "mdp_core_clk", "iface_clk",
+			"core_mmss_clk", "bus_clk";
+
+		qcom,platform-strength-ctrl = [ff 06
+						ff 06
+						ff 06
+						ff 06
+						ff 00];
+		qcom,platform-regulator-settings = [1d
+						1d 1d 1d 1d];
+		qcom,platform-lane-config = [00 00 10 0f
+					00 00 10 0f
+					00 00 10 0f
+					00 00 10 0f
+					00 00 10 8f];
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda";
+				qcom,supply-min-voltage = <1250000>;
+				qcom,supply-max-voltage = <1250000>;
+				qcom,supply-enable-load = <2500>;
+				qcom,supply-disable-load = <1>;
+			};
+		};
+	};
+
+	mdss_dsi_phy1: qcom,mdss_dsi_phy1@996400 {
+		compatible = "qcom,dsi-phy-v4.0";
+		label = "dsi-phy-1";
+		cell-index = <1>;
+		reg = <0x996400 0x588>;
+		reg-names = "dsi_phy";
+
+		gdsc-supply = <&gdsc_mdss>;
+		vdda-supply = <&pm8994_l2>;
+
+		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mmss_misc_ahb_clk>,
+			 <&clock_mmss clk_mdss_axi_clk>;
+		clock-names = "mdp_core_clk", "iface_clk",
+			"core_mmss_clk", "bus_clk";
+
+		qcom,platform-strength-ctrl = [ff 06
+						ff 06
+						ff 06
+						ff 06
+						ff 00];
+		qcom,platform-regulator-settings = [1d
+						1d 1d 1d 1d];
+		qcom,platform-lane-config = [00 00 10 0f
+					00 00 10 0f
+					00 00 10 0f
+					00 00 10 0f
+					00 00 10 8f];
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda";
+				qcom,supply-min-voltage = <1250000>;
+				qcom,supply-max-voltage = <1250000>;
+				qcom,supply-enable-load = <2500>;
+				qcom,supply-disable-load = <1>;
+			};
+		};
+	};
+
+	mdss_hdmi: qcom,hdmi_tx@9a0000 {
+		compatible = "qcom,hdmi-tx-8996";
+
+		reg =	<0x009a0000 0x50c>,
+			<0x00070000 0x6158>,
+			<0x009e0000 0xfff>;
+		reg-names = "core_physical",
+			"qfprom_physical",
+			"hdcp_physical";
+		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
+			 <&clock_mmss clk_mdss_ahb_clk>,
+			 <&clock_mmss clk_mdss_hdmi_clk>,
+			 <&clock_mmss clk_mdss_hdmi_ahb_clk>,
+			 <&clock_mmss clk_mdss_extpclk_clk>;
+		clock-names =
+			"mdp_core_clk",
+			"iface_clk",
+			"core_clk",
+			"alt_iface_clk",
+			"extp_clk";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <8 0>;
+		hpd-gdsc-supply = <&gdsc_mdss>;
+		qcom,hdmi-tx-hpd-gpio = <&pm8994_mpps 4 0>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&mdss_hdmi_hpd_active
+			     &mdss_hdmi_ddc_active
+			     &mdss_hdmi_cec_active>;
+		pinctrl-1 = <&mdss_hdmi_hpd_suspend
+			     &mdss_hdmi_ddc_suspend
+			     &mdss_hdmi_cec_suspend>;
+
+		hdmi_audio: qcom,msm-hdmi-audio-rx {
+			compatible = "qcom,msm-hdmi-audio-codec-rx";
+		};
+	};
+};
+
+/* dummy nodes for compatibility with 8996 mdss dtsi */
+&soc {
+	mdss_dsi: qcom,mdss_dsi_dummy {
+		/* dummy node for backward compatibility */
+	};
+
+	mdss_hdmi_tx: qcom,mdss_hdmi_tx_dummy {
+		/* dummy node for backward compatibility */
+	};
+
+	mdss_fb2: qcom,mdss_fb2_dummy {
+		/* dummy node for backward compatibility */
+	};
+};
diff --git a/arch/arm/boot/dts/qcom/msm8996-v2.dtsi b/arch/arm/boot/dts/qcom/msm8996-v2.dtsi
index d3c262f42aceeeb6f5eb0aa3e6a0612ec3c85a2e..9725bc3ee5303be7b833269b1640ecec863fc589 100644
--- a/arch/arm/boot/dts/qcom/msm8996-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-v2.dtsi
@@ -480,7 +480,11 @@
 	gdsc-venus-supply = <&gdsc_venus>;
 };
 
-&mdss_dsi {
+&mdss_hdmi {
+	hpd-gdsc-venus-supply = <&gdsc_venus>;
+};
+
+&mdss_dsi0 {
 	gdsc-venus-supply = <&gdsc_venus>;
 	qcom,core-supply-entries {
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi
index f69c388fbbef07c85d65b8c75643dc649554a779..49eafeaa5d70e6ce82cfea5a1755b9b6869686e6 100644
--- a/arch/arm/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996.dtsi
@@ -237,7 +237,7 @@
 };
 
 #include "msm8996-ion.dtsi"
-#include "msm8996-mdss.dtsi"
+#include "msm8996-sde.dtsi"
 #include "msm8996-mdss-pll.dtsi"
 #include "msm8996-smp2p.dtsi"
 #include "msm8996-ipcrouter.dtsi"
diff --git a/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi
index dff374962e024fd2d2661865cf47483fa5b4b210..f91b29bca493d6e1a94a48e696ecffef556c39dd 100644
--- a/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi
@@ -331,7 +331,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi
index 4bf3dc08ab3e078ba8ded106961e9d28b6d8b3c8..40bb8727cc3027220eb2a6170f9f9e502d9c1834 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi
@@ -311,7 +311,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi
index a9306475e24e1d5a10ad62e17ec42414b677c849..d652b456cb1c1c6924de3cb487cdfc97b1783957 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi
@@ -336,7 +336,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi
index bfe29ff56413ed7d00d2e512b85e0634a2455334..d0d13332595aa5ecd5f1726db65903958f14b678 100644
--- a/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi
@@ -174,7 +174,7 @@
 	qcom,mdss-dsi-t-clk-pre = <0x22>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-panel-timings = [00 1a 06 06 0a 11 05 07 05 03 04 00];
 	qcom,mdss-dsi-t-clk-post = <0x07>;
 	qcom,mdss-dsi-t-clk-pre = <0x28>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi
index a0e56f630eb7bd525a4e4a43b2b7c91aba227b46..4aadd4802b51997deb9375c861bc96e35ebd943d 100644
--- a/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi
@@ -364,7 +364,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi
index af533bbfbc83bdce90d9df46b6ba67799c78abd0..fb69a793a680f200b9533f9c6ac1bece368b3eaf 100644
--- a/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi
@@ -352,7 +352,7 @@
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
 };
 
-&dsi_jdi_1080_vid {
+&dsi_jdi_1080p_video {
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig
index 56bbe80542644e52d5c9733260af9f70aaaf600e..97154767b1a37f27e469d3e3d1a7638a4af41e59 100644
--- a/arch/arm64/configs/msm-perf_defconfig
+++ b/arch/arm64/configs/msm-perf_defconfig
@@ -344,7 +344,6 @@ CONFIG_THERMAL_TSENS8974=y
 CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_WCD9335_CODEC=y
-CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_QPNP=y
@@ -394,13 +393,15 @@ CONFIG_MSM_VIDC_VMEM=y
 CONFIG_MSM_VIDC_GOVERNORS=y
 CONFIG_MSM_SDE_ROTATOR=y
 CONFIG_QCOM_KGSL=y
-CONFIG_FB=y
+CONFIG_DRM=y
 CONFIG_FB_MSM=y
 CONFIG_FB_MSM_MDSS=y
 CONFIG_FB_MSM_MDSS_WRITEBACK=y
 CONFIG_FB_MSM_MDSS_HDMI_PANEL=y
 CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
@@ -516,7 +517,6 @@ CONFIG_MSM_IPC_ROUTER_MHI_XPRT=y
 CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y
 CONFIG_MSM_GLINK_PKT=y
 CONFIG_MSM_SPM=y
-CONFIG_QCOM_SCM=y
 CONFIG_QCOM_SCM_XPU=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_MEMORY_DUMP_V2=y
@@ -560,7 +560,6 @@ CONFIG_EXT4_FS_ICE_ENCRYPTION=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ECRYPT_FS=y
 CONFIG_ECRYPT_FS_MESSAGING=y
diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig
index c39a9311e056e6288a96cdf6b7d93960a5a86039..22036f2ccf9748dfe6b79b43b7f439fcba5bfed8 100644
--- a/arch/arm64/configs/msm_defconfig
+++ b/arch/arm64/configs/msm_defconfig
@@ -331,7 +331,6 @@ CONFIG_THERMAL_TSENS8974=y
 CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_WCD9335_CODEC=y
-CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_QPNP=y
@@ -382,13 +381,15 @@ CONFIG_MSM_VIDC_VMEM=y
 CONFIG_MSM_VIDC_GOVERNORS=y
 CONFIG_MSM_SDE_ROTATOR=y
 CONFIG_QCOM_KGSL=y
-CONFIG_FB=y
+CONFIG_DRM=y
 CONFIG_FB_MSM=y
 CONFIG_FB_MSM_MDSS=y
 CONFIG_FB_MSM_MDSS_WRITEBACK=y
 CONFIG_FB_MSM_MDSS_HDMI_PANEL=y
 CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
@@ -517,7 +518,6 @@ CONFIG_MSM_IPC_ROUTER_MHI_XPRT=y
 CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y
 CONFIG_MSM_GLINK_PKT=y
 CONFIG_MSM_SPM=y
-CONFIG_QCOM_SCM=y
 CONFIG_QCOM_SCM_XPU=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_MEMORY_DUMP_V2=y
@@ -567,7 +567,6 @@ CONFIG_EXT4_FS_ICE_ENCRYPTION=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ECRYPT_FS=y
 CONFIG_ECRYPT_FS_MESSAGING=y
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index c4bf9a1cf4a65d927003314bb230ebe3f1e57288..f4554b39d5d9e5b52712512ff6b9c5cfa41a3713 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -8,6 +8,7 @@ menuconfig DRM
 	tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
 	depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU && HAS_DMA
 	select HDMI
+	select FB
 	select FB_CMDLINE
 	select I2C
 	select I2C_ALGOBIT
@@ -52,7 +53,7 @@ config DRM_FBDEV_EMULATION
 	depends on DRM
 	select DRM_KMS_HELPER
 	select DRM_KMS_FB_HELPER
-	default y
+	default n
 	help
 	  Choose this option if you have a need for the legacy fbdev
 	  support. Note that this support also provides the linux console
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 2d5ca8eec13a9611668a90756a756f6f40a0506b..e944b0c456ed7de21d40fd0a531356192c2d5f96 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -335,7 +335,7 @@ int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
 		return -EINVAL;
 
 	memset(packet, 0, sizeof(*packet));
-	packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
+	packet->header[2] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
 
 	/* TODO: compute ECC if hardware support is not available */
 
@@ -347,16 +347,16 @@ int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
 	 * and 2.
 	 */
 	if (mipi_dsi_packet_format_is_long(msg->type)) {
-		packet->header[1] = (msg->tx_len >> 0) & 0xff;
-		packet->header[2] = (msg->tx_len >> 8) & 0xff;
+		packet->header[0] = (msg->tx_len >> 0) & 0xff;
+		packet->header[1] = (msg->tx_len >> 8) & 0xff;
 
 		packet->payload_length = msg->tx_len;
 		packet->payload = msg->tx_buf;
 	} else {
 		const u8 *tx = msg->tx_buf;
 
-		packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0;
-		packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0;
+		packet->header[0] = (msg->tx_len > 0) ? tx[0] : 0;
+		packet->header[1] = (msg->tx_len > 1) ? tx[1] : 0;
 	}
 
 	packet->size = sizeof(packet->header) + packet->payload_length;
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 84d3ec98e6b9e045699c748fb05d80e608d8e06a..afd94a1e85d3713ace43fb1d712461da48a7efd7 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -3,7 +3,7 @@ config DRM_MSM
 	tristate "MSM DRM"
 	depends on DRM
 	depends on ARCH_QCOM || (ARM && COMPILE_TEST)
-	depends on OF && COMMON_CLK
+	depends on OF
 	select REGULATOR
 	select DRM_KMS_HELPER
 	select DRM_PANEL
@@ -33,6 +33,18 @@ config DRM_MSM_DSI
 	  Choose this option if you have a need for MIPI DSI connector
 	  support.
 
+config DRM_MSM_DSI_STAGING
+	bool "Enable new DSI driver support in MSM DRM driver"
+	depends on DRM_MSM
+	select DRM_PANEL
+	select DRM_MIPI_DSI
+	default y
+	help
+	  Choose this option if you need MIPI DSI connector support on MSM
+	  which conforms to DRM. MIPI stands for Mobile Industry Processor
+	  Interface and DSI stands for Display Serial Interface which powers
+	  the primary display of your mobile device.
+
 config DRM_MSM_DSI_PLL
 	bool "Enable DSI PLL driver in MSM DRM"
 	depends on DRM_MSM_DSI && COMMON_CLK
@@ -54,3 +66,25 @@ config DRM_MSM_DSI_20NM_PHY
 	default y
 	help
 	  Choose this option if the 20nm DSI PHY is used on the platform.
+
+config DRM_MSM_MDP4
+	tristate "MSM MDP4 DRM driver"
+	depends on DRM_MSM
+	default n
+	help
+	  Choose this option if MSM MDP4 revision support is needed in DRM/KMS.
+
+config DRM_MSM_HDCP
+	tristate "HDCP for MSM DRM"
+	depends on DRM_MSM
+	default n
+	help
+	  Chose this option if HDCP supported is needed in DRM/KMS driver.
+
+config DRM_SDE_WB
+	bool "Enable Writeback support in SDE DRM"
+	depends on DRM_MSM
+	default y
+	help
+	  Choose this option for writeback connector support.
+
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 1c90290be716de80108c07839f96c422fab67b3f..4ca16fc01e1c0abb38a790aff07ddc5e756e82fe 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,11 +1,10 @@
-ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
+ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -Idrivers/gpu/drm/msm/dsi-staging
 ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
+ccflags-$(CONFIG_SYNC) += -Idrivers/staging/android
+ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
+ccflags-y += -Idrivers/gpu/drm/msm/sde
 
-msm-y := \
-	adreno/adreno_device.o \
-	adreno/adreno_gpu.o \
-	adreno/a3xx_gpu.o \
-	adreno/a4xx_gpu.o \
+msm_drm-y := \
 	hdmi/hdmi.o \
 	hdmi/hdmi_audio.o \
 	hdmi/hdmi_bridge.o \
@@ -23,13 +22,6 @@ msm-y := \
 	edp/edp_phy.o \
 	mdp/mdp_format.o \
 	mdp/mdp_kms.o \
-	mdp/mdp4/mdp4_crtc.o \
-	mdp/mdp4/mdp4_dtv_encoder.o \
-	mdp/mdp4/mdp4_lcdc_encoder.o \
-	mdp/mdp4/mdp4_lvds_connector.o \
-	mdp/mdp4/mdp4_irq.o \
-	mdp/mdp4/mdp4_kms.o \
-	mdp/mdp4/mdp4_plane.o \
 	mdp/mdp5/mdp5_cfg.o \
 	mdp/mdp5/mdp5_ctl.o \
 	mdp/mdp5/mdp5_crtc.o \
@@ -38,6 +30,91 @@ msm-y := \
 	mdp/mdp5/mdp5_kms.o \
 	mdp/mdp5/mdp5_plane.o \
 	mdp/mdp5/mdp5_smp.o \
+	sde/sde_crtc.o \
+	sde/sde_encoder.o \
+	sde/sde_encoder_phys_vid.o \
+	sde/sde_encoder_phys_cmd.o \
+	sde/sde_irq.o \
+	sde/sde_core_irq.o \
+	sde/sde_core_perf.o \
+	sde/sde_rm.o \
+	sde/sde_kms_utils.o \
+	sde/sde_kms.o \
+	sde/sde_plane.o \
+	sde/sde_connector.o \
+	sde/sde_backlight.o \
+	sde/sde_color_processing.o \
+	sde/sde_vbif.o \
+	sde_dbg_evtlog.o
+
+# use drm gpu driver only if qcom_kgsl driver not available
+ifneq ($(CONFIG_QCOM_KGSL),y)
+msm_drm-y += adreno/adreno_device.o \
+	adreno/adreno_gpu.o \
+	adreno/a3xx_gpu.o \
+	adreno/a4xx_gpu.o
+endif
+
+msm_drm-$(CONFIG_DRM_MSM_MDP4) += mdp/mdp4/mdp4_crtc.o \
+	mdp/mdp4/mdp4_dtv_encoder.o \
+	mdp/mdp4/mdp4_lcdc_encoder.o \
+	mdp/mdp4/mdp4_lvds_connector.o \
+	mdp/mdp4/mdp4_irq.o \
+	mdp/mdp4/mdp4_kms.o \
+	mdp/mdp4/mdp4_plane.o
+
+msm_drm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
+msm_drm-$(CONFIG_SYNC) += sde/sde_fence.o
+msm_drm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
+
+msm_drm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
+			dsi/dsi_cfg.o \
+			dsi/dsi_host.o \
+			dsi/dsi_manager.o \
+			dsi/phy/dsi_phy.o \
+			dsi/dsi_manager.o \
+			mdp/mdp5/mdp5_cmd_encoder.o
+
+msm_drm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
+msm_drm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
+
+msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
+				dsi-staging/dsi_clk_pwr.o \
+				dsi-staging/dsi_phy.o \
+				dsi-staging/dsi_phy_hw_v4_0.o \
+				dsi-staging/dsi_ctrl_hw_1_4.o \
+				dsi-staging/dsi_ctrl.o \
+				dsi-staging/dsi_catalog.o \
+				dsi-staging/dsi_drm.o \
+				dsi-staging/dsi_display.o \
+				dsi-staging/dsi_panel.o \
+				dsi-staging/dsi_display_test.o
+
+msm_drm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
+				dsi/pll/dsi_pll_28nm.o
+
+msm_drm-$(CONFIG_DRM_MSM) += \
+	sde/sde_hw_catalog.o \
+	sde/sde_hw_cdm.o \
+	sde/sde_hw_dspp.o \
+	sde/sde_hw_intf.o \
+	sde/sde_hw_lm.o \
+	sde/sde_hw_ctl.o \
+	sde/sde_hw_util.o \
+	sde/sde_hw_sspp.o \
+	sde/sde_hw_wb.o \
+	sde/sde_hw_pingpong.o \
+	sde/sde_hw_top.o \
+	sde/sde_hw_interrupts.o \
+	sde/sde_hw_vbif.o \
+	sde/sde_formats.o \
+	sde_power_handle.o \
+	sde/sde_hw_color_processing_v1_7.o
+
+msm_drm-$(CONFIG_DRM_SDE_WB) += sde/sde_wb.o \
+	sde/sde_encoder_phys_wb.o
+
+msm_drm-$(CONFIG_DRM_MSM) += \
 	msm_atomic.o \
 	msm_drv.o \
 	msm_fb.o \
@@ -46,26 +123,10 @@ msm-y := \
 	msm_gem_submit.o \
 	msm_gpu.o \
 	msm_iommu.o \
+	msm_smmu.o \
 	msm_perf.o \
 	msm_rd.o \
-	msm_ringbuffer.o
-
-msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
-msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
-
-msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
-			dsi/dsi_cfg.o \
-			dsi/dsi_host.o \
-			dsi/dsi_manager.o \
-			dsi/phy/dsi_phy.o \
-			mdp/mdp5/mdp5_cmd_encoder.o
-
-msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
-msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
-
-ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
-msm-y += dsi/pll/dsi_pll.o
-msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
-endif
+	msm_ringbuffer.o \
+	msm_prop.o
 
-obj-$(CONFIG_DRM_MSM)	+= msm.o
+obj-$(CONFIG_DRM_MSM)	+= msm_drm.o
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
new file mode 100644
index 0000000000000000000000000000000000000000..06027a963be13bf65600dfe8780297b6f575ca9c
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "msm-dsi-catalog:[%s] " fmt, __func__
+#include <linux/errno.h>
+
+#include "dsi_catalog.h"
+
+/**
+ * dsi_catalog_14_init() - catalog init for dsi controller v1.4
+ */
+static void dsi_catalog_14_init(struct dsi_ctrl_hw *ctrl)
+{
+	ctrl->ops.host_setup             = dsi_ctrl_hw_14_host_setup;
+	ctrl->ops.setup_lane_map         = dsi_ctrl_hw_14_setup_lane_map;
+	ctrl->ops.video_engine_en        = dsi_ctrl_hw_14_video_engine_en;
+	ctrl->ops.video_engine_setup     = dsi_ctrl_hw_14_video_engine_setup;
+	ctrl->ops.set_video_timing       = dsi_ctrl_hw_14_set_video_timing;
+	ctrl->ops.cmd_engine_setup       = dsi_ctrl_hw_14_cmd_engine_setup;
+	ctrl->ops.setup_cmd_stream       = dsi_ctrl_hw_14_setup_cmd_stream;
+	ctrl->ops.ctrl_en                = dsi_ctrl_hw_14_ctrl_en;
+	ctrl->ops.cmd_engine_en          = dsi_ctrl_hw_14_cmd_engine_en;
+	ctrl->ops.phy_sw_reset           = dsi_ctrl_hw_14_phy_sw_reset;
+	ctrl->ops.soft_reset             = dsi_ctrl_hw_14_soft_reset;
+	ctrl->ops.kickoff_command        = dsi_ctrl_hw_14_kickoff_command;
+	ctrl->ops.kickoff_fifo_command   = dsi_ctrl_hw_14_kickoff_fifo_command;
+	ctrl->ops.reset_cmd_fifo         = dsi_ctrl_hw_14_reset_cmd_fifo;
+	ctrl->ops.trigger_command_dma    = dsi_ctrl_hw_14_trigger_command_dma;
+	ctrl->ops.ulps_request           = dsi_ctrl_hw_14_ulps_request;
+	ctrl->ops.ulps_exit              = dsi_ctrl_hw_14_ulps_exit;
+	ctrl->ops.clear_ulps_request     = dsi_ctrl_hw_14_clear_ulps_request;
+	ctrl->ops.get_lanes_in_ulps      = dsi_ctrl_hw_14_get_lanes_in_ulps;
+	ctrl->ops.clamp_enable           = dsi_ctrl_hw_14_clamp_enable;
+	ctrl->ops.clamp_disable          = dsi_ctrl_hw_14_clamp_disable;
+	ctrl->ops.get_interrupt_status   = dsi_ctrl_hw_14_get_interrupt_status;
+	ctrl->ops.get_error_status       = dsi_ctrl_hw_14_get_error_status;
+	ctrl->ops.clear_error_status     = dsi_ctrl_hw_14_clear_error_status;
+	ctrl->ops.clear_interrupt_status =
+		dsi_ctrl_hw_14_clear_interrupt_status;
+	ctrl->ops.enable_status_interrupts =
+		dsi_ctrl_hw_14_enable_status_interrupts;
+	ctrl->ops.enable_error_interrupts =
+		dsi_ctrl_hw_14_enable_error_interrupts;
+	ctrl->ops.video_test_pattern_setup =
+		dsi_ctrl_hw_14_video_test_pattern_setup;
+	ctrl->ops.cmd_test_pattern_setup =
+		dsi_ctrl_hw_14_cmd_test_pattern_setup;
+	ctrl->ops.test_pattern_enable    = dsi_ctrl_hw_14_test_pattern_enable;
+	ctrl->ops.trigger_cmd_test_pattern =
+		dsi_ctrl_hw_14_trigger_cmd_test_pattern;
+	ctrl->ops.reg_dump_to_buffer    = dsi_ctrl_hw_14_reg_dump_to_buffer;
+}
+
+/**
+ * dsi_catalog_20_init() - catalog init for dsi controller v2.0
+ */
+static void dsi_catalog_20_init(struct dsi_ctrl_hw *ctrl)
+{
+	set_bit(DSI_CTRL_CPHY, ctrl->feature_map);
+}
+
+/**
+ * dsi_catalog_ctrl_setup() - return catalog info for dsi controller
+ * @ctrl:        Pointer to DSI controller hw object.
+ * @version:     DSI controller version.
+ * @index:       DSI controller instance ID.
+ *
+ * This function setups the catalog information in the dsi_ctrl_hw object.
+ *
+ * return: error code for failure and 0 for success.
+ */
+int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
+			   enum dsi_ctrl_version version,
+			   u32 index)
+{
+	int rc = 0;
+
+	if (version == DSI_CTRL_VERSION_UNKNOWN ||
+	    version >= DSI_CTRL_VERSION_MAX) {
+		pr_err("Unsupported version: %d\n", version);
+		return -ENOTSUPP;
+	}
+
+	ctrl->index = index;
+	set_bit(DSI_CTRL_VIDEO_TPG, ctrl->feature_map);
+	set_bit(DSI_CTRL_CMD_TPG, ctrl->feature_map);
+	set_bit(DSI_CTRL_VARIABLE_REFRESH_RATE, ctrl->feature_map);
+	set_bit(DSI_CTRL_DYNAMIC_REFRESH, ctrl->feature_map);
+	set_bit(DSI_CTRL_DESKEW_CALIB, ctrl->feature_map);
+	set_bit(DSI_CTRL_DPHY, ctrl->feature_map);
+
+	switch (version) {
+	case DSI_CTRL_VERSION_1_4:
+		dsi_catalog_14_init(ctrl);
+		break;
+	case DSI_CTRL_VERSION_2_0:
+		dsi_catalog_20_init(ctrl);
+		break;
+	default:
+		return -ENOTSUPP;
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_catalog_phy_4_0_init() - catalog init for DSI PHY v4.0
+ */
+static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
+{
+	phy->ops.regulator_enable = dsi_phy_hw_v4_0_regulator_enable;
+	phy->ops.regulator_disable = dsi_phy_hw_v4_0_regulator_disable;
+	phy->ops.enable = dsi_phy_hw_v4_0_enable;
+	phy->ops.disable = dsi_phy_hw_v4_0_disable;
+	phy->ops.calculate_timing_params =
+		dsi_phy_hw_v4_0_calculate_timing_params;
+}
+
+/**
+ * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
+ * @ctrl:        Pointer to DSI PHY hw object.
+ * @version:     DSI PHY version.
+ * @index:       DSI PHY instance ID.
+ *
+ * This function setups the catalog information in the dsi_phy_hw object.
+ *
+ * return: error code for failure and 0 for success.
+ */
+int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
+			  enum dsi_phy_version version,
+			  u32 index)
+{
+	int rc = 0;
+
+	if (version == DSI_PHY_VERSION_UNKNOWN ||
+	    version >= DSI_PHY_VERSION_MAX) {
+		pr_err("Unsupported version: %d\n", version);
+		return -ENOTSUPP;
+	}
+
+	phy->index = index;
+	set_bit(DSI_PHY_DPHY, phy->feature_map);
+
+	switch (version) {
+	case DSI_PHY_VERSION_4_0:
+		dsi_catalog_phy_4_0_init(phy);
+		break;
+	case DSI_PHY_VERSION_1_0:
+	case DSI_PHY_VERSION_2_0:
+	case DSI_PHY_VERSION_3_0:
+	default:
+		return -ENOTSUPP;
+	}
+
+	return rc;
+}
+
+
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
new file mode 100644
index 0000000000000000000000000000000000000000..98bd9b039f0974ba705732e40c5829774c0b92dc
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CATALOG_H_
+#define _DSI_CATALOG_H_
+
+#include "dsi_ctrl_hw.h"
+#include "dsi_phy_hw.h"
+
+/**
+ * dsi_catalog_ctrl_setup() - return catalog info for dsi controller
+ * @ctrl:        Pointer to DSI controller hw object.
+ * @version:     DSI controller version.
+ * @index:       DSI controller instance ID.
+ *
+ * This function setups the catalog information in the dsi_ctrl_hw object.
+ *
+ * return: error code for failure and 0 for success.
+ */
+int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
+			   enum dsi_ctrl_version version,
+			   u32 index);
+
+/**
+ * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
+ * @ctrl:        Pointer to DSI PHY hw object.
+ * @version:     DSI PHY version.
+ * @index:       DSI PHY instance ID.
+ *
+ * This function setups the catalog information in the dsi_phy_hw object.
+ *
+ * return: error code for failure and 0 for success.
+ */
+int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
+			  enum dsi_phy_version version,
+			  u32 index);
+
+/* Definitions for 4.0 PHY hardware driver */
+void dsi_phy_hw_v4_0_regulator_enable(struct dsi_phy_hw *phy,
+				      struct dsi_phy_per_lane_cfgs *cfg);
+void dsi_phy_hw_v4_0_regulator_disable(struct dsi_phy_hw *phy);
+void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
+void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy);
+int dsi_phy_hw_v4_0_calculate_timing_params(struct dsi_phy_hw *phy,
+					    struct dsi_mode_info *mode,
+					    struct dsi_host_common_cfg *cfg,
+					   struct dsi_phy_per_lane_cfgs
+					   *timing);
+
+/* Definitions for 1.4 controller hardware driver */
+void dsi_ctrl_hw_14_host_setup(struct dsi_ctrl_hw *ctrl,
+			       struct dsi_host_common_cfg *config);
+void dsi_ctrl_hw_14_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
+void dsi_ctrl_hw_14_video_engine_setup(struct dsi_ctrl_hw *ctrl,
+				       struct dsi_host_common_cfg *common_cfg,
+				       struct dsi_video_engine_cfg *cfg);
+void dsi_ctrl_hw_14_set_video_timing(struct dsi_ctrl_hw *ctrl,
+			 struct dsi_mode_info *mode);
+
+void dsi_ctrl_hw_14_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
+				     struct dsi_host_common_cfg *common_cfg,
+				     struct dsi_cmd_engine_cfg *cfg);
+
+void dsi_ctrl_hw_14_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on);
+void dsi_ctrl_hw_14_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
+
+void dsi_ctrl_hw_14_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
+				     u32 width_in_pixels,
+				     u32 h_stride,
+				     u32 height_in_lines,
+				     u32 vc_id);
+void dsi_ctrl_hw_14_phy_sw_reset(struct dsi_ctrl_hw *ctrl);
+void dsi_ctrl_hw_14_soft_reset(struct dsi_ctrl_hw *ctrl);
+
+void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
+		       struct dsi_lane_mapping *lane_map);
+void dsi_ctrl_hw_14_kickoff_command(struct dsi_ctrl_hw *ctrl,
+			struct dsi_ctrl_cmd_dma_info *cmd,
+			u32 flags);
+
+void dsi_ctrl_hw_14_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
+			     struct dsi_ctrl_cmd_dma_fifo_info *cmd,
+			     u32 flags);
+void dsi_ctrl_hw_14_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);
+void dsi_ctrl_hw_14_trigger_command_dma(struct dsi_ctrl_hw *ctrl);
+
+void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
+void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
+void dsi_ctrl_hw_14_clear_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
+u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);
+
+void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
+				 u32 lanes,
+				 bool enable_ulps);
+
+void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
+				  u32 lanes,
+				  bool disable_ulps);
+u32 dsi_ctrl_hw_14_get_interrupt_status(struct dsi_ctrl_hw *ctrl);
+void dsi_ctrl_hw_14_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);
+void dsi_ctrl_hw_14_enable_status_interrupts(struct dsi_ctrl_hw *ctrl,
+					     u32 ints);
+
+u64 dsi_ctrl_hw_14_get_error_status(struct dsi_ctrl_hw *ctrl);
+void dsi_ctrl_hw_14_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors);
+void dsi_ctrl_hw_14_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
+					    u64 errors);
+
+void dsi_ctrl_hw_14_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
+				 enum dsi_test_pattern type,
+				 u32 init_val);
+void dsi_ctrl_hw_14_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
+			       enum dsi_test_pattern  type,
+			       u32 init_val,
+			       u32 stream_id);
+void dsi_ctrl_hw_14_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable);
+void dsi_ctrl_hw_14_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
+				 u32 stream_id);
+ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
+					  char *buf,
+					  u32 size);
+#endif /* _DSI_CATALOG_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c
new file mode 100644
index 0000000000000000000000000000000000000000..7def847f6f2a328e686fad569a2648b809e5b381
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "dsi_clk_pwr.h"
+
+#define INC_REFCOUNT(s, start_func) \
+	({ \
+		int rc = 0; \
+		if ((s)->refcount == 0) { \
+			rc = start_func(s); \
+			if (rc) \
+				pr_err("failed to enable, rc = %d\n", rc); \
+		} \
+		(s)->refcount++; \
+		rc; \
+	})
+
+#define DEC_REFCOUNT(s, stop_func) \
+	({ \
+		int rc = 0; \
+		if ((s)->refcount == 0) { \
+			pr_err("unbalanced refcount\n"); \
+		} else { \
+			(s)->refcount--; \
+			if ((s)->refcount == 0) { \
+				rc = stop_func(s); \
+				if (rc) \
+					pr_err("disable failed, rc=%d\n", rc); \
+			} \
+		} \
+		rc; \
+	})
+
+static int dsi_core_clk_start(struct dsi_core_clk_info *clks)
+{
+	int rc = 0;
+
+	rc = clk_prepare_enable(clks->mdp_core_clk);
+	if (rc) {
+		pr_err("failed to enable mdp_core_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = clk_prepare_enable(clks->iface_clk);
+	if (rc) {
+		pr_err("failed to enable iface_clk, rc=%d\n", rc);
+		goto error_disable_core_clk;
+	}
+
+	rc = clk_prepare_enable(clks->bus_clk);
+	if (rc) {
+		pr_err("failed to enable bus_clk, rc=%d\n", rc);
+		goto error_disable_iface_clk;
+	}
+
+	rc = clk_prepare_enable(clks->core_mmss_clk);
+	if (rc) {
+		pr_err("failed to enable core_mmss_clk, rc=%d\n", rc);
+		goto error_disable_bus_clk;
+	}
+
+	return rc;
+
+error_disable_bus_clk:
+	clk_disable_unprepare(clks->bus_clk);
+error_disable_iface_clk:
+	clk_disable_unprepare(clks->iface_clk);
+error_disable_core_clk:
+	clk_disable_unprepare(clks->mdp_core_clk);
+error:
+	return rc;
+}
+
+static int dsi_core_clk_stop(struct dsi_core_clk_info *clks)
+{
+	clk_disable_unprepare(clks->core_mmss_clk);
+	clk_disable_unprepare(clks->bus_clk);
+	clk_disable_unprepare(clks->iface_clk);
+	clk_disable_unprepare(clks->mdp_core_clk);
+
+	return 0;
+}
+
+static int dsi_link_clk_set_rate(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(l_clks->esc_clk, l_clks->esc_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for esc_clk rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = clk_set_rate(l_clks->byte_clk, l_clks->byte_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for byte_clk rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = clk_set_rate(l_clks->pixel_clk, l_clks->pixel_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for pixel_clk rc = %d\n", rc);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_link_clk_prepare(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_prepare(l_clks->esc_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi esc clk, rc=%d\n", rc);
+		goto esc_clk_err;
+	}
+
+	rc = clk_prepare(l_clks->byte_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi byte clk, rc=%d\n", rc);
+		goto byte_clk_err;
+	}
+
+	rc = clk_prepare(l_clks->pixel_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi pixel clk, rc=%d\n", rc);
+		goto pixel_clk_err;
+	}
+
+	return rc;
+
+pixel_clk_err:
+	clk_unprepare(l_clks->byte_clk);
+byte_clk_err:
+	clk_unprepare(l_clks->esc_clk);
+esc_clk_err:
+	return rc;
+}
+
+static void dsi_link_clk_unprepare(struct dsi_link_clk_info *l_clks)
+{
+	clk_unprepare(l_clks->pixel_clk);
+	clk_unprepare(l_clks->byte_clk);
+	clk_unprepare(l_clks->esc_clk);
+}
+
+static int dsi_link_clk_enable(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_enable(l_clks->esc_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi esc clk, rc=%d\n", rc);
+		goto esc_clk_err;
+	}
+
+	rc = clk_enable(l_clks->byte_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi byte clk, rc=%d\n", rc);
+		goto byte_clk_err;
+	}
+
+	rc = clk_enable(l_clks->pixel_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi pixel clk, rc=%d\n", rc);
+		goto pixel_clk_err;
+	}
+
+	return rc;
+
+pixel_clk_err:
+	clk_disable(l_clks->byte_clk);
+byte_clk_err:
+	clk_disable(l_clks->esc_clk);
+esc_clk_err:
+	return rc;
+}
+
+static void dsi_link_clk_disable(struct dsi_link_clk_info *l_clks)
+{
+	clk_disable(l_clks->esc_clk);
+	clk_disable(l_clks->pixel_clk);
+	clk_disable(l_clks->byte_clk);
+}
+
+/**
+ * dsi_link_clk_start() - enable dsi link clocks
+ */
+static int dsi_link_clk_start(struct dsi_link_clk_info *clks)
+{
+	int rc = 0;
+
+	if (clks->set_new_rate) {
+		rc = dsi_link_clk_set_rate(clks);
+		if (rc) {
+			pr_err("failed to set clk rates, rc = %d\n", rc);
+			goto error;
+		} else {
+			clks->set_new_rate = false;
+		}
+	}
+
+	rc = dsi_link_clk_prepare(clks);
+	if (rc) {
+		pr_err("failed to prepare link clks, rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_link_clk_enable(clks);
+	if (rc) {
+		pr_err("failed to enable link clks, rc = %d\n", rc);
+		goto error_unprepare;
+	}
+
+	pr_debug("Link clocks are enabled\n");
+	return rc;
+error_unprepare:
+	dsi_link_clk_unprepare(clks);
+error:
+	return rc;
+}
+
+/**
+ * dsi_link_clk_stop() - Stop DSI link clocks.
+ */
+static int dsi_link_clk_stop(struct dsi_link_clk_info *clks)
+{
+	dsi_link_clk_disable(clks);
+	dsi_link_clk_unprepare(clks);
+
+	pr_debug("Link clocks disabled\n");
+
+	return 0;
+}
+
+/*
+ * dsi_pwr_parse_supply_node() - parse power supply node from root device node
+ */
+static int dsi_pwr_parse_supply_node(struct device_node *root,
+				     struct dsi_regulator_info *regs)
+{
+	int rc = 0;
+	int i = 0;
+	u32 tmp = 0;
+	struct device_node *node = NULL;
+
+	for_each_child_of_node(root, node) {
+		const char *st = NULL;
+
+		rc = of_property_read_string(node, "qcom,supply-name", &st);
+		if (rc) {
+			pr_err("failed to read name, rc = %d\n", rc);
+			goto error;
+		}
+
+		snprintf(regs->vregs[i].vreg_name,
+			 ARRAY_SIZE(regs->vregs[i].vreg_name),
+			 "%s", st);
+
+		rc = of_property_read_u32(node, "qcom,supply-min-voltage",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read min voltage, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].min_voltage = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-max-voltage",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read max voltage, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].max_voltage = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-enable-load",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read enable load, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].enable_load = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-disable-load",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read disable load, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].disable_load = tmp;
+
+		/* Optional values */
+		rc = of_property_read_u32(node, "qcom,supply-pre-on-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("pre-on-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].pre_on_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-pre-off-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("pre-off-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].pre_off_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-post-on-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("post-on-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].post_on_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-post-off-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("post-off-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].post_off_sleep = tmp;
+		}
+
+		++i;
+		pr_debug("[%s] minv=%d maxv=%d, en_load=%d, dis_load=%d\n",
+			 regs->vregs[i].vreg_name,
+			 regs->vregs[i].min_voltage,
+			 regs->vregs[i].max_voltage,
+			 regs->vregs[i].enable_load,
+			 regs->vregs[i].disable_load);
+	}
+
+error:
+	return rc;
+}
+
+/**
+ * dsi_pwr_enable_vregs() - enable/disable regulators
+ */
+static int dsi_pwr_enable_vregs(struct dsi_regulator_info *regs, bool enable)
+{
+	int rc = 0, i = 0;
+	struct dsi_vreg *vreg;
+	int num_of_v = 0;
+
+	if (enable) {
+		for (i = 0; i < regs->count; i++) {
+			vreg = &regs->vregs[i];
+			if (vreg->pre_on_sleep)
+				msleep(vreg->pre_on_sleep);
+
+			rc = regulator_set_load(vreg->vreg,
+						vreg->enable_load);
+			if (rc < 0) {
+				pr_err("Setting optimum mode failed for %s\n",
+				       vreg->vreg_name);
+				goto error;
+			}
+			num_of_v = regulator_count_voltages(vreg->vreg);
+			if (num_of_v > 0) {
+				rc = regulator_set_voltage(vreg->vreg,
+							   vreg->min_voltage,
+							   vreg->max_voltage);
+				if (rc) {
+					pr_err("Set voltage(%s) fail, rc=%d\n",
+						 vreg->vreg_name, rc);
+					goto error_disable_opt_mode;
+				}
+			}
+
+			rc = regulator_enable(vreg->vreg);
+			if (rc) {
+				pr_err("enable failed for %s, rc=%d\n",
+				       vreg->vreg_name, rc);
+				goto error_disable_voltage;
+			}
+
+			if (vreg->post_on_sleep)
+				msleep(vreg->post_on_sleep);
+		}
+	} else {
+		for (i = (regs->count - 1); i >= 0; i--) {
+			if (regs->vregs[i].pre_off_sleep)
+				msleep(regs->vregs[i].pre_off_sleep);
+
+			(void)regulator_set_load(regs->vregs[i].vreg,
+						regs->vregs[i].disable_load);
+			(void)regulator_disable(regs->vregs[i].vreg);
+
+			if (regs->vregs[i].post_off_sleep)
+				msleep(regs->vregs[i].post_off_sleep);
+		}
+	}
+
+	return 0;
+error_disable_opt_mode:
+	(void)regulator_set_load(regs->vregs[i].vreg,
+				 regs->vregs[i].disable_load);
+
+error_disable_voltage:
+	if (num_of_v > 0)
+		(void)regulator_set_voltage(regs->vregs[i].vreg,
+					    0, regs->vregs[i].max_voltage);
+error:
+	for (i--; i >= 0; i--) {
+		if (regs->vregs[i].pre_off_sleep)
+			msleep(regs->vregs[i].pre_off_sleep);
+
+		(void)regulator_set_load(regs->vregs[i].vreg,
+					 regs->vregs[i].disable_load);
+
+		num_of_v = regulator_count_voltages(regs->vregs[i].vreg);
+		if (num_of_v > 0)
+			(void)regulator_set_voltage(regs->vregs[i].vreg,
+					    0, regs->vregs[i].max_voltage);
+
+		(void)regulator_disable(regs->vregs[i].vreg);
+
+		if (regs->vregs[i].post_off_sleep)
+			msleep(regs->vregs[i].post_off_sleep);
+	}
+
+	return rc;
+}
+
+/**
+* dsi_clk_pwr_of_get_vreg_data - Parse regulator supply information
+* @of_node:        Device of node to parse for supply information.
+* @regs:           Pointer where regulator information will be copied to.
+* @supply_name:    Name of the supply node.
+*
+* return: error code in case of failure or 0 for success.
+*/
+int dsi_clk_pwr_of_get_vreg_data(struct device_node *of_node,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name)
+{
+	int rc = 0;
+	struct device_node *supply_root_node = NULL;
+
+	if (!of_node || !regs) {
+		pr_err("Bad params\n");
+		return -EINVAL;
+	}
+
+	regs->count = 0;
+	supply_root_node = of_get_child_by_name(of_node, supply_name);
+	if (!supply_root_node) {
+		supply_root_node = of_parse_phandle(of_node, supply_name, 0);
+		if (!supply_root_node) {
+			pr_err("No supply entry present for %s\n", supply_name);
+			return -EINVAL;
+		}
+	}
+
+	regs->count = of_get_available_child_count(supply_root_node);
+	if (regs->count == 0) {
+		pr_err("No vregs defined for %s\n", supply_name);
+		return -EINVAL;
+	}
+
+	regs->vregs = kcalloc(regs->count, sizeof(*regs->vregs), GFP_KERNEL);
+	if (!regs->vregs) {
+		regs->count = 0;
+		return -ENOMEM;
+	}
+
+	rc = dsi_pwr_parse_supply_node(supply_root_node, regs);
+	if (rc) {
+		pr_err("failed to parse supply node for %s, rc = %d\n",
+			supply_name, rc);
+
+		kfree(regs->vregs);
+		regs->vregs = NULL;
+		regs->count = 0;
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_clk_pwr_get_dt_vreg_data - parse regulator supply information
+ * @dev:            Device whose of_node needs to be parsed.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_get_dt_vreg_data(struct device *dev,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name)
+{
+	int rc = 0;
+	struct device_node *of_node = NULL;
+	struct device_node *supply_node = NULL;
+	struct device_node *supply_root_node = NULL;
+
+	if (!dev || !regs) {
+		pr_err("Bad params\n");
+		return -EINVAL;
+	}
+
+	of_node = dev->of_node;
+	regs->count = 0;
+	supply_root_node = of_get_child_by_name(of_node, supply_name);
+	if (!supply_root_node) {
+		supply_root_node = of_parse_phandle(of_node, supply_name, 0);
+		if (!supply_root_node) {
+			pr_err("No supply entry present for %s\n", supply_name);
+			return -EINVAL;
+		}
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node)
+		regs->count++;
+
+	if (regs->count == 0) {
+		pr_err("No vregs defined for %s\n", supply_name);
+		return -EINVAL;
+	}
+
+	regs->vregs = devm_kcalloc(dev, regs->count, sizeof(*regs->vregs),
+				   GFP_KERNEL);
+	if (!regs->vregs) {
+		regs->count = 0;
+		return -ENOMEM;
+	}
+
+	rc = dsi_pwr_parse_supply_node(supply_root_node, regs);
+	if (rc) {
+		pr_err("failed to parse supply node for %s, rc = %d\n",
+		       supply_name, rc);
+		devm_kfree(dev, regs->vregs);
+		regs->vregs = NULL;
+		regs->count = 0;
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_pwr_enable_regulator() - enable a set of regulators
+ * @regs:       Pointer to set of regulators to enable or disable.
+ * @enable:     Enable/Disable regulators.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_pwr_enable_regulator(struct dsi_regulator_info *regs, bool enable)
+{
+	int rc = 0;
+
+	if (enable) {
+		if (regs->refcount == 0) {
+			rc = dsi_pwr_enable_vregs(regs, true);
+			if (rc)
+				pr_err("failed to enable regulators\n");
+		}
+		regs->refcount++;
+	} else {
+		if (regs->refcount == 0) {
+			pr_err("Unbalanced regulator off\n");
+		} else {
+			regs->refcount--;
+			if (regs->refcount == 0) {
+				rc = dsi_pwr_enable_vregs(regs, false);
+				if (rc)
+					pr_err("failed to disable vregs\n");
+			}
+		}
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_clk_enable_core_clks() - enable DSI core clocks
+ * @clks:      DSI core clock information.
+ * @enable:    enable/disable DSI core clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_core_clks(struct dsi_core_clk_info *clks, bool enable)
+{
+	int rc = 0;
+
+	if (enable)
+		rc = INC_REFCOUNT(clks, dsi_core_clk_start);
+	else
+		rc = DEC_REFCOUNT(clks, dsi_core_clk_stop);
+
+	return rc;
+}
+
+/**
+ * dsi_clk_enable_link_clks() - enable DSI link clocks
+ * @clks:      DSI link clock information.
+ * @enable:    enable/disable DSI link clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_link_clks(struct dsi_link_clk_info *clks, bool enable)
+{
+	int rc = 0;
+
+	if (enable)
+		rc = INC_REFCOUNT(clks, dsi_link_clk_start);
+	else
+		rc = DEC_REFCOUNT(clks, dsi_link_clk_stop);
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_link_frequencies() - set frequencies for link clks
+ * @clks:         Link clock information
+ * @pixel_clk:    pixel clock frequency in KHz.
+ * @byte_clk:     Byte clock frequency in KHz.
+ * @esc_clk:      Escape clock frequency in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_link_frequencies(struct dsi_link_clk_info *clks,
+				 u64 pixel_clk,
+				 u64 byte_clk,
+				 u64 esc_clk)
+{
+	int rc = 0;
+
+	clks->pixel_clk_rate = pixel_clk;
+	clks->byte_clk_rate = byte_clk;
+	clks->esc_clk_rate = esc_clk;
+	clks->set_new_rate = true;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
+ * @clks:      DSI link clock information.
+ * @pixel_clk: Pixel clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_pixel_clk_rate(struct dsi_link_clk_info *clks, u64 pixel_clk)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(clks->pixel_clk, pixel_clk);
+	if (rc)
+		pr_err("failed to set clk rate for pixel clk, rc=%d\n", rc);
+	else
+		clks->pixel_clk_rate = pixel_clk;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_byte_clk_rate() - set frequency for byte clock
+ * @clks:      DSI link clock information.
+ * @byte_clk: Byte clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_byte_clk_rate(struct dsi_link_clk_info *clks, u64 byte_clk)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(clks->byte_clk, byte_clk);
+	if (rc)
+		pr_err("failed to set clk rate for byte clk, rc=%d\n", rc);
+	else
+		clks->byte_clk_rate = byte_clk;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_update_parent() - update parent clocks for specified clock
+ * @parent:       link clock pair which are set as parent.
+ * @child:        link clock pair whose parent has to be set.
+ */
+int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
+			  struct dsi_clk_link_set *child)
+{
+	int rc = 0;
+
+	rc = clk_set_parent(child->byte_clk, parent->byte_clk);
+	if (rc) {
+		pr_err("failed to set byte clk parent\n");
+		goto error;
+	}
+
+	rc = clk_set_parent(child->pixel_clk, parent->pixel_clk);
+	if (rc) {
+		pr_err("failed to set pixel clk parent\n");
+		goto error;
+	}
+error:
+	return rc;
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h
new file mode 100644
index 0000000000000000000000000000000000000000..223ca4ec4290257c611298f69312675888db777b
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CLK_PWR_H_
+#define _DSI_CLK_PWR_H_
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+
+/**
+ * struct dsi_vreg - regulator information for DSI regulators
+ * @vreg:            Handle to the regulator.
+ * @vreg_name:       Regulator name.
+ * @min_voltage:     Minimum voltage in uV.
+ * @max_voltage:     Maximum voltage in uV.
+ * @enable_load:     Load, in uA, when enabled.
+ * @disable_load:    Load, in uA, when disabled.
+ * @pre_on_sleep:    Sleep, in ms, before enabling the regulator.
+ * @post_on_sleep:   Sleep, in ms, after enabling the regulator.
+ * @pre_off_sleep:   Sleep, in ms, before disabling the regulator.
+ * @post_off_sleep:  Sleep, in ms, after disabling the regulator.
+ */
+struct dsi_vreg {
+	struct regulator *vreg;
+	char vreg_name[32];
+	u32 min_voltage;
+	u32 max_voltage;
+	u32 enable_load;
+	u32 disable_load;
+	u32 pre_on_sleep;
+	u32 post_on_sleep;
+	u32 pre_off_sleep;
+	u32 post_off_sleep;
+};
+
+/**
+ * struct dsi_regulator_info - set of vregs that are turned on/off together.
+ * @vregs:       Array of dsi_vreg structures.
+ * @count:       Number of vregs.
+ * @refcount:    Reference counting for enabling.
+ */
+struct dsi_regulator_info {
+	struct dsi_vreg *vregs;
+	u32 count;
+	u32 refcount;
+};
+
+/**
+ * struct dsi_core_clk_info - Core clock information for DSI hardware
+ * @mdp_core_clk:        Handle to MDP core clock.
+ * @iface_clk:           Handle to MDP interface clock.
+ * @core_mmss_clk:       Handle to MMSS core clock.
+ * @bus_clk:             Handle to bus clock.
+ * @refcount:            Reference count for core clocks.
+ * @clk_state:           Current clock state.
+ */
+struct dsi_core_clk_info {
+	struct clk *mdp_core_clk;
+	struct clk *iface_clk;
+	struct clk *core_mmss_clk;
+	struct clk *bus_clk;
+
+	u32 refcount;
+	u32 clk_state;
+};
+
+/**
+ * struct dsi_link_clk_info - Link clock information for DSI hardware.
+ * @byte_clk:        Handle to DSI byte clock.
+ * @byte_clk_rate:   Frequency of DSI byte clock in KHz.
+ * @pixel_clk:       Handle to DSI pixel clock.
+ * @pixel_clk_rate:  Frequency of DSI pixel clock in KHz.
+ * @esc_clk:         Handle to DSI escape clock.
+ * @esc_clk_rate:    Frequency of DSI escape clock in KHz.
+ * @refcount:        Reference count for link clocks.
+ * @clk_state:       Current clock state.
+ * @set_new_rate:    private flag used by clock utility.
+ */
+struct dsi_link_clk_info {
+	struct clk *byte_clk;
+	u64 byte_clk_rate;
+
+	struct clk *pixel_clk;
+	u64 pixel_clk_rate;
+
+	struct clk *esc_clk;
+	u64 esc_clk_rate;
+
+	u32 refcount;
+	u32 clk_state;
+	bool set_new_rate;
+};
+
+/**
+ * struct dsi_clk_link_set - Pair of clock handles to describe link clocks
+ * @byte_clk:     Handle to DSi byte clock.
+ * @pixel_clk:    Handle to DSI pixel clock.
+ */
+struct dsi_clk_link_set {
+	struct clk *byte_clk;
+	struct clk *pixel_clk;
+};
+
+/**
+ * dsi_clk_pwr_of_get_vreg_data - parse regulator supply information
+ * @of_node:        Device of node to parse for supply information.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_of_get_vreg_data(struct device_node *of_node,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name);
+
+/**
+ * dsi_clk_pwr_get_dt_vreg_data - parse regulator supply information
+ * @dev:            Device whose of_node needs to be parsed.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_get_dt_vreg_data(struct device *dev,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name);
+
+/**
+ * dsi_pwr_enable_regulator() - enable a set of regulators
+ * @regs:       Pointer to set of regulators to enable or disable.
+ * @enable:     Enable/Disable regulators.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_pwr_enable_regulator(struct dsi_regulator_info *regs, bool enable);
+
+/**
+ * dsi_clk_enable_core_clks() - enable DSI core clocks
+ * @clks:      DSI core clock information.
+ * @enable:    enable/disable DSI core clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_core_clks(struct dsi_core_clk_info *clks, bool enable);
+
+/**
+ * dsi_clk_enable_link_clks() - enable DSI link clocks
+ * @clks:      DSI link clock information.
+ * @enable:    enable/disable DSI link clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_link_clks(struct dsi_link_clk_info *clks, bool enable);
+
+/**
+ * dsi_clk_set_link_frequencies() - set frequencies for link clks
+ * @clks:         Link clock information
+ * @pixel_clk:    pixel clock frequency in KHz.
+ * @byte_clk:     Byte clock frequency in KHz.
+ * @esc_clk:      Escape clock frequency in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_link_frequencies(struct dsi_link_clk_info *clks,
+				 u64 pixel_clk,
+				 u64 byte_clk,
+				 u64 esc_clk);
+
+/**
+ * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
+ * @clks:      DSI link clock information.
+ * @pixel_clk: Pixel clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_pixel_clk_rate(struct dsi_link_clk_info *clks, u64 pixel_clk);
+
+/**
+ * dsi_clk_set_byte_clk_rate() - set frequency for byte clock
+ * @clks:      DSI link clock information.
+ * @byte_clk: Byte clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_byte_clk_rate(struct dsi_link_clk_info *clks, u64 byte_clk);
+
+/**
+ * dsi_clk_update_parent() - update parent clocks for specified clock
+ * @parent:       link clock pair which are set as parent.
+ * @child:        link clock pair whose parent has to be set.
+ */
+int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
+			  struct dsi_clk_link_set *child);
+#endif /* _DSI_CLK_PWR_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
new file mode 100644
index 0000000000000000000000000000000000000000..b8520aadbc0c82e258a25e9f2cbf253d75919c4d
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -0,0 +1,2302 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"dsi-ctrl:[%s] " fmt, __func__
+
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/msm-bus.h>
+#include <linux/of_irq.h>
+#include <video/mipi_display.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_gpu.h"
+#include "dsi_ctrl.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_catalog.h"
+
+#define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL"
+
+#define DSI_CTRL_TX_TO_MS     200
+
+#define TO_ON_OFF(x) ((x) ? "ON" : "OFF")
+/**
+ * enum dsi_ctrl_driver_ops - controller driver ops
+ */
+enum dsi_ctrl_driver_ops {
+	DSI_CTRL_OP_POWER_STATE_CHANGE,
+	DSI_CTRL_OP_CMD_ENGINE,
+	DSI_CTRL_OP_VID_ENGINE,
+	DSI_CTRL_OP_HOST_ENGINE,
+	DSI_CTRL_OP_CMD_TX,
+	DSI_CTRL_OP_ULPS_TOGGLE,
+	DSI_CTRL_OP_CLAMP_TOGGLE,
+	DSI_CTRL_OP_SET_CLK_SOURCE,
+	DSI_CTRL_OP_HOST_INIT,
+	DSI_CTRL_OP_TPG,
+	DSI_CTRL_OP_PHY_SW_RESET,
+	DSI_CTRL_OP_ASYNC_TIMING,
+	DSI_CTRL_OP_MAX
+};
+
+struct dsi_ctrl_list_item {
+	struct dsi_ctrl *ctrl;
+	struct list_head list;
+};
+
+static LIST_HEAD(dsi_ctrl_list);
+static DEFINE_MUTEX(dsi_ctrl_list_lock);
+
+static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;
+static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;
+
+static const struct of_device_id msm_dsi_of_match[] = {
+	{
+		.compatible = "qcom,dsi-ctrl-hw-v1.4",
+		.data = &dsi_ctrl_v1_4,
+	},
+	{
+		.compatible = "qcom,dsi-ctrl-hw-v2.0",
+		.data = &dsi_ctrl_v2_0,
+	},
+	{}
+};
+
+static ssize_t debugfs_state_info_read(struct file *file,
+				       char __user *buff,
+				       size_t count,
+				       loff_t *ppos)
+{
+	struct dsi_ctrl *dsi_ctrl = file->private_data;
+	char *buf;
+	u32 len = 0;
+
+	if (!dsi_ctrl)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0;
+
+	buf = kzalloc(SZ_4K, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	/* Dump current state */
+	len += snprintf((buf + len), (SZ_4K - len), "Current State:\n");
+	len += snprintf((buf + len), (SZ_4K - len),
+			"\tPOWER_STATUS = %s\n\tCORE_CLOCK = %s\n",
+			TO_ON_OFF(dsi_ctrl->current_state.pwr_enabled),
+			TO_ON_OFF(dsi_ctrl->current_state.core_clk_enabled));
+	len += snprintf((buf + len), (SZ_4K - len),
+			"\tLINK_CLOCK = %s\n\tULPS_STATUS = %s\n",
+			TO_ON_OFF(dsi_ctrl->current_state.link_clk_enabled),
+			TO_ON_OFF(dsi_ctrl->current_state.ulps_enabled));
+	len += snprintf((buf + len), (SZ_4K - len),
+			"\tCLAMP_STATUS = %s\n\tCTRL_ENGINE = %s\n",
+			TO_ON_OFF(dsi_ctrl->current_state.clamp_enabled),
+			TO_ON_OFF(dsi_ctrl->current_state.controller_state));
+	len += snprintf((buf + len), (SZ_4K - len),
+			"\tVIDEO_ENGINE = %s\n\tCOMMAND_ENGINE = %s\n",
+			TO_ON_OFF(dsi_ctrl->current_state.vid_engine_state),
+			TO_ON_OFF(dsi_ctrl->current_state.cmd_engine_state));
+
+	/* Dump clock information */
+	len += snprintf((buf + len), (SZ_4K - len), "\nClock Info:\n");
+	len += snprintf((buf + len), (SZ_4K - len),
+			"\tBYTE_CLK = %llu, PIXEL_CLK = %llu, ESC_CLK = %llu\n",
+			dsi_ctrl->clk_info.link_clks.byte_clk_rate,
+			dsi_ctrl->clk_info.link_clks.pixel_clk_rate,
+			dsi_ctrl->clk_info.link_clks.esc_clk_rate);
+
+	/* TODO: make sure that this does not exceed 4K */
+	if (copy_to_user(buff, buf, len)) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+	kfree(buf);
+	return len;
+}
+
+static ssize_t debugfs_reg_dump_read(struct file *file,
+				     char __user *buff,
+				     size_t count,
+				     loff_t *ppos)
+{
+	struct dsi_ctrl *dsi_ctrl = file->private_data;
+	char *buf;
+	u32 len = 0;
+
+	if (!dsi_ctrl)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0;
+
+	buf = kzalloc(SZ_4K, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	if (dsi_ctrl->current_state.core_clk_enabled) {
+		len = dsi_ctrl->hw.ops.reg_dump_to_buffer(&dsi_ctrl->hw,
+							  buf,
+							  SZ_4K);
+	} else {
+		len = snprintf((buf + len), (SZ_4K - len),
+			       "Core clocks are not turned on, cannot read\n");
+	}
+
+	/* TODO: make sure that this does not exceed 4K */
+	if (copy_to_user(buff, buf, len)) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+	kfree(buf);
+	return len;
+}
+
+static const struct file_operations state_info_fops = {
+	.open = simple_open,
+	.read = debugfs_state_info_read,
+};
+
+static const struct file_operations reg_dump_fops = {
+	.open = simple_open,
+	.read = debugfs_reg_dump_read,
+};
+
+static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl,
+				 struct dentry *parent)
+{
+	int rc = 0;
+	struct dentry *dir, *state_file, *reg_dump;
+
+	dir = debugfs_create_dir(dsi_ctrl->name, parent);
+	if (IS_ERR_OR_NULL(dir)) {
+		rc = PTR_ERR(dir);
+		pr_err("[DSI_%d] debugfs create dir failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	state_file = debugfs_create_file("state_info",
+					 0444,
+					 dir,
+					 dsi_ctrl,
+					 &state_info_fops);
+	if (IS_ERR_OR_NULL(state_file)) {
+		rc = PTR_ERR(state_file);
+		pr_err("[DSI_%d] state file failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error_remove_dir;
+	}
+
+	reg_dump = debugfs_create_file("reg_dump",
+				       0444,
+				       dir,
+				       dsi_ctrl,
+				       &reg_dump_fops);
+	if (IS_ERR_OR_NULL(reg_dump)) {
+		rc = PTR_ERR(reg_dump);
+		pr_err("[DSI_%d] reg dump file failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error_remove_dir;
+	}
+
+	dsi_ctrl->debugfs_root = dir;
+error_remove_dir:
+	debugfs_remove(dir);
+error:
+	return rc;
+}
+
+static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	debugfs_remove(dsi_ctrl->debugfs_root);
+	return 0;
+}
+
+static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl,
+				enum dsi_ctrl_driver_ops op,
+				u32 op_state)
+{
+	int rc = 0;
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	switch (op) {
+	case DSI_CTRL_OP_POWER_STATE_CHANGE:
+		if (state->power_state == op_state) {
+			pr_debug("[%d] No change in state, pwr_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			if ((state->cmd_engine_state == DSI_CTRL_ENGINE_ON) ||
+			    (state->vid_engine_state == DSI_CTRL_ENGINE_ON) ||
+			    (state->controller_state == DSI_CTRL_ENGINE_ON)) {
+				pr_debug("[%d]State error: op=%d: %d, %d, %d\n",
+				       dsi_ctrl->index,
+				       op_state,
+				       state->cmd_engine_state,
+				       state->vid_engine_state,
+				       state->controller_state);
+				rc = -EINVAL;
+			}
+		}
+		break;
+	case DSI_CTRL_OP_CMD_ENGINE:
+		if (state->cmd_engine_state == op_state) {
+			pr_debug("[%d] No change in state, cmd_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_VID_ENGINE:
+		if (state->vid_engine_state == op_state) {
+			pr_debug("[%d] No change in state, cmd_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_HOST_ENGINE:
+		if (state->controller_state == op_state) {
+			pr_debug("[%d] No change in state, ctrl_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) {
+			pr_debug("[%d]State error (link is off): op=%d:, %d\n",
+			       dsi_ctrl->index,
+			       op_state,
+			       state->power_state);
+			rc = -EINVAL;
+		} else if ((op_state == DSI_CTRL_ENGINE_OFF) &&
+			   ((state->cmd_engine_state != DSI_CTRL_ENGINE_OFF) ||
+			    (state->vid_engine_state != DSI_CTRL_ENGINE_OFF))) {
+			pr_debug("[%d]State error (eng on): op=%d: %d, %d\n",
+				  dsi_ctrl->index,
+				  op_state,
+				  state->cmd_engine_state,
+				  state->vid_engine_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_CMD_TX:
+		if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+		    (state->host_initialized != true) ||
+		    (state->cmd_engine_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->host_initialized,
+			       state->cmd_engine_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_HOST_INIT:
+		if (state->host_initialized == op_state) {
+			pr_debug("[%d] No change in state, host_init=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state != DSI_CTRL_POWER_CORE_CLK_ON) {
+			pr_debug("[%d]State error: op=%d: %d\n",
+			       dsi_ctrl->index, op, state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_ULPS_TOGGLE:
+		if (state->ulps_enabled == op_state) {
+			pr_debug("[%d] No change in state, ulps_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_CLAMP_TOGGLE:
+		if (state->clamp_enabled == op_state) {
+			pr_debug("[%d] No change in state, clamp_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_SET_CLK_SOURCE:
+		if (state->power_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			pr_debug("[%d] State error: op=%d: %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_TPG:
+		if (state->tpg_enabled == op_state) {
+			pr_debug("[%d] No change in state, tpg_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_PHY_SW_RESET:
+		if (state->power_state != DSI_CTRL_POWER_CORE_CLK_ON) {
+			pr_debug("[%d]State error: op=%d: %d\n",
+			       dsi_ctrl->index, op, state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_ASYNC_TIMING:
+		if (state->vid_engine_state != op_state) {
+			pr_err("[%d] Unexpected engine state vid_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		}
+		break;
+	default:
+		rc = -ENOTSUPP;
+		break;
+	}
+
+	return rc;
+}
+
+static void dsi_ctrl_update_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_ctrl_driver_ops op,
+				  u32 op_state)
+{
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	switch (op) {
+	case DSI_CTRL_OP_POWER_STATE_CHANGE:
+		state->power_state = op_state;
+		if (op_state == DSI_CTRL_POWER_OFF) {
+			state->pwr_enabled = false;
+			state->core_clk_enabled = false;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_VREG_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = false;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_CORE_CLK_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = true;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = true;
+			state->link_clk_enabled = true;
+		}
+		break;
+	case DSI_CTRL_OP_CMD_ENGINE:
+		state->cmd_engine_state = op_state;
+		break;
+	case DSI_CTRL_OP_VID_ENGINE:
+		state->vid_engine_state = op_state;
+		break;
+	case DSI_CTRL_OP_HOST_ENGINE:
+		state->controller_state = op_state;
+		break;
+	case DSI_CTRL_OP_ULPS_TOGGLE:
+		state->ulps_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_CLAMP_TOGGLE:
+		state->clamp_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_SET_CLK_SOURCE:
+		state->clk_source_set = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_HOST_INIT:
+		state->host_initialized = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_TPG:
+		state->tpg_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_CMD_TX:
+	case DSI_CTRL_OP_PHY_SW_RESET:
+	default:
+		break;
+	}
+}
+
+static int dsi_ctrl_init_regmap(struct platform_device *pdev,
+				struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	void __iomem *ptr;
+
+	ptr = msm_ioremap(pdev, "dsi_ctrl", ctrl->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	ctrl->hw.base = ptr;
+	pr_debug("[%s] map dsi_ctrl registers to %p\n", ctrl->name,
+		 ctrl->hw.base);
+
+	ptr = msm_ioremap(pdev, "mmss_misc", ctrl->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	ctrl->hw.mmss_misc_base = ptr;
+	pr_debug("[%s] map mmss_misc registers to %p\n", ctrl->name,
+		 ctrl->hw.mmss_misc_base);
+	return rc;
+}
+
+static int dsi_ctrl_clocks_deinit(struct dsi_ctrl *ctrl)
+{
+	struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
+	struct dsi_link_clk_info *link = &ctrl->clk_info.link_clks;
+	struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
+
+	if (core->mdp_core_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->mdp_core_clk);
+	if (core->iface_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->iface_clk);
+	if (core->core_mmss_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->core_mmss_clk);
+	if (core->bus_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->bus_clk);
+
+	memset(core, 0x0, sizeof(*core));
+
+	if (link->byte_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->byte_clk);
+	if (link->pixel_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->pixel_clk);
+	if (link->esc_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->esc_clk);
+
+	memset(link, 0x0, sizeof(*link));
+
+	if (rcg->byte_clk)
+		devm_clk_put(&ctrl->pdev->dev, rcg->byte_clk);
+	if (rcg->pixel_clk)
+		devm_clk_put(&ctrl->pdev->dev, rcg->pixel_clk);
+
+	memset(rcg, 0x0, sizeof(*rcg));
+
+	return 0;
+}
+
+static int dsi_ctrl_clocks_init(struct platform_device *pdev,
+				struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
+	struct dsi_link_clk_info *link = &ctrl->clk_info.link_clks;
+	struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
+
+	core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
+	if (IS_ERR(core->mdp_core_clk)) {
+		rc = PTR_ERR(core->mdp_core_clk);
+		pr_err("failed to get mdp_core_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
+	if (IS_ERR(core->iface_clk)) {
+		rc = PTR_ERR(core->iface_clk);
+		pr_err("failed to get iface_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
+	if (IS_ERR(core->core_mmss_clk)) {
+		rc = PTR_ERR(core->core_mmss_clk);
+		pr_err("failed to get core_mmss_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
+	if (IS_ERR(core->bus_clk)) {
+		rc = PTR_ERR(core->bus_clk);
+		pr_err("failed to get bus_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->byte_clk = devm_clk_get(&pdev->dev, "byte_clk");
+	if (IS_ERR(link->byte_clk)) {
+		rc = PTR_ERR(link->byte_clk);
+		pr_err("failed to get byte_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk");
+	if (IS_ERR(link->pixel_clk)) {
+		rc = PTR_ERR(link->pixel_clk);
+		pr_err("failed to get pixel_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->esc_clk = devm_clk_get(&pdev->dev, "core_clk");
+	if (IS_ERR(link->esc_clk)) {
+		rc = PTR_ERR(link->esc_clk);
+		pr_err("failed to get esc_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rcg->byte_clk = devm_clk_get(&pdev->dev, "byte_clk_rcg");
+	if (IS_ERR(rcg->byte_clk)) {
+		rc = PTR_ERR(rcg->byte_clk);
+		pr_err("failed to get byte_clk_rcg, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rcg->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk_rcg");
+	if (IS_ERR(rcg->pixel_clk)) {
+		rc = PTR_ERR(rcg->pixel_clk);
+		pr_err("failed to get pixel_clk_rcg, rc=%d\n", rc);
+		goto fail;
+	}
+
+	return 0;
+fail:
+	dsi_ctrl_clocks_deinit(ctrl);
+	return rc;
+}
+
+static int dsi_ctrl_supplies_deinit(struct dsi_ctrl *ctrl)
+{
+	int i = 0;
+	int rc = 0;
+	struct dsi_regulator_info *regs;
+
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	regs = &ctrl->pwr_info.host_pwr;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	if (!ctrl->pwr_info.host_pwr.vregs) {
+		devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.host_pwr.vregs);
+		ctrl->pwr_info.host_pwr.vregs = NULL;
+		ctrl->pwr_info.host_pwr.count = 0;
+	}
+
+	if (!ctrl->pwr_info.digital.vregs) {
+		devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.digital.vregs);
+		ctrl->pwr_info.digital.vregs = NULL;
+		ctrl->pwr_info.digital.count = 0;
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_supplies_init(struct platform_device *pdev,
+				  struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_regulator_info *regs;
+	struct regulator *vreg = NULL;
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &ctrl->pwr_info.digital,
+					  "qcom,core-supply-entries");
+	if (rc) {
+		pr_err("failed to get digital supply, rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &ctrl->pwr_info.host_pwr,
+					  "qcom,ctrl-supply-entries");
+	if (rc) {
+		pr_err("failed to get host power supplies, rc = %d\n", rc);
+		goto error_digital;
+	}
+
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		if (IS_ERR(vreg)) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			rc = PTR_ERR(vreg);
+			goto error_host_pwr;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	regs = &ctrl->pwr_info.host_pwr;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		if (IS_ERR(vreg)) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			for (--i; i >= 0; i--)
+				devm_regulator_put(regs->vregs[i].vreg);
+			rc = PTR_ERR(vreg);
+			goto error_digital_put;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	return rc;
+
+error_digital_put:
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++)
+		devm_regulator_put(regs->vregs[i].vreg);
+error_host_pwr:
+	devm_kfree(&pdev->dev, ctrl->pwr_info.host_pwr.vregs);
+	ctrl->pwr_info.host_pwr.vregs = NULL;
+	ctrl->pwr_info.host_pwr.count = 0;
+error_digital:
+	devm_kfree(&pdev->dev, ctrl->pwr_info.digital.vregs);
+	ctrl->pwr_info.digital.vregs = NULL;
+	ctrl->pwr_info.digital.count = 0;
+error:
+	return rc;
+}
+
+static int dsi_ctrl_axi_bus_client_init(struct platform_device *pdev,
+					struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
+
+	bus->bus_scale_table = msm_bus_cl_get_pdata(pdev);
+	if (IS_ERR_OR_NULL(bus->bus_scale_table)) {
+		rc = PTR_ERR(bus->bus_scale_table);
+		pr_err("msm_bus_cl_get_pdata() failed, rc = %d\n", rc);
+		bus->bus_scale_table = NULL;
+		return rc;
+	}
+
+	bus->bus_handle = msm_bus_scale_register_client(bus->bus_scale_table);
+	if (!bus->bus_handle) {
+		rc = -EINVAL;
+		pr_err("failed to register axi bus client\n");
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl *ctrl)
+{
+	struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
+
+	if (bus->bus_handle) {
+		msm_bus_scale_unregister_client(bus->bus_handle);
+
+		bus->bus_handle = 0;
+	}
+
+	return 0;
+}
+
+static int dsi_ctrl_validate_panel_info(struct dsi_ctrl *dsi_ctrl,
+					struct dsi_host_config *config)
+{
+	int rc = 0;
+	struct dsi_host_common_cfg *host_cfg = &config->common_config;
+
+	if (config->panel_mode >= DSI_OP_MODE_MAX) {
+		pr_err("Invalid dsi operation mode (%d)\n", config->panel_mode);
+		rc = -EINVAL;
+		goto err;
+	}
+
+	if ((host_cfg->data_lanes & (DSI_CLOCK_LANE - 1)) == 0) {
+		pr_err("No data lanes are enabled\n");
+		rc = -EINVAL;
+		goto err;
+	}
+err:
+	return rc;
+}
+
+static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
+				      struct dsi_host_config *config)
+{
+	int rc = 0;
+	u32 num_of_lanes = 0;
+	u32 bpp = 3;
+	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
+	    byte_clk_rate;
+	struct dsi_host_common_cfg *host_cfg = &config->common_config;
+	struct dsi_mode_info *timing = &config->video_timing;
+
+	if (host_cfg->data_lanes & DSI_DATA_LANE_0)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_1)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_2)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_3)
+		num_of_lanes++;
+
+	h_period = DSI_H_TOTAL(timing);
+	v_period = DSI_V_TOTAL(timing);
+
+	bit_rate = h_period * v_period * timing->refresh_rate * bpp * 8;
+	bit_rate_per_lane = bit_rate;
+	do_div(bit_rate_per_lane, num_of_lanes);
+	pclk_rate = bit_rate;
+	do_div(pclk_rate, (8 * bpp));
+	byte_clk_rate = bit_rate_per_lane;
+	do_div(byte_clk_rate, 8);
+	pr_debug("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
+		 bit_rate, bit_rate_per_lane);
+	pr_debug("byte_clk_rate = %llu, pclk_rate = %llu\n",
+		  byte_clk_rate, pclk_rate);
+
+	rc = dsi_clk_set_link_frequencies(&dsi_ctrl->clk_info.link_clks,
+					  pclk_rate,
+					  byte_clk_rate,
+					  config->esc_clk_rate_hz);
+	if (rc)
+		pr_err("Failed to update link frequencies\n");
+
+	return rc;
+}
+
+static int dsi_ctrl_enable_supplies(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (enable) {
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.host_pwr,
+					      true);
+		if (rc) {
+			pr_err("failed to enable host power regs, rc=%d\n", rc);
+			goto error;
+		}
+
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
+					      true);
+		if (rc) {
+			pr_err("failed to enable gdsc, rc=%d\n", rc);
+			(void)dsi_pwr_enable_regulator(
+						&dsi_ctrl->pwr_info.host_pwr,
+						false
+						);
+			goto error;
+		}
+	} else {
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
+					      false);
+		if (rc) {
+			pr_err("failed to disable gdsc, rc=%d\n", rc);
+			goto error;
+		}
+
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.host_pwr,
+					      false);
+		if (rc) {
+			pr_err("failed to disable host power regs, rc=%d\n",
+			       rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_ctrl_vote_for_bandwidth(struct dsi_ctrl *dsi_ctrl, bool on)
+{
+	int rc = 0;
+	bool changed = false;
+	struct dsi_ctrl_bus_scale_info *axi_bus = &dsi_ctrl->axi_bus_info;
+
+	if (on) {
+		if (axi_bus->refcount == 0)
+			changed = true;
+
+		axi_bus->refcount++;
+	} else {
+		if (axi_bus->refcount != 0) {
+			axi_bus->refcount--;
+
+			if (axi_bus->refcount == 0)
+				changed = true;
+		} else {
+			pr_err("bus bw votes are not balanced\n");
+		}
+	}
+
+	if (changed) {
+		rc = msm_bus_scale_client_update_request(axi_bus->bus_handle,
+							 on ? 1 : 0);
+		if (rc)
+			pr_err("bus scale client update failed, rc=%d\n", rc);
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl,
+				     const struct mipi_dsi_packet *packet,
+				     u8 **buffer,
+				     u32 *size)
+{
+	int rc = 0;
+	u8 *buf = NULL;
+	u32 len, i;
+
+	len = packet->size;
+	len += 0x3; len &= ~0x03; /* Align to 32 bits */
+
+	buf = devm_kzalloc(&dsi_ctrl->pdev->dev, len * sizeof(u8), GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	for (i = 0; i < len; i++) {
+		if (i >= packet->size)
+			buf[i] = 0xFF;
+		else if (i < sizeof(packet->header))
+			buf[i] = packet->header[i];
+		else
+			buf[i] = packet->payload[i - sizeof(packet->header)];
+	}
+
+	if (packet->payload_length > 0)
+		buf[3] |= BIT(6);
+
+	buf[3] |= BIT(7);
+	*buffer = buf;
+	*size = len;
+
+	return rc;
+}
+
+static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+	struct mipi_dsi_packet packet;
+	struct dsi_ctrl_cmd_dma_fifo_info cmd;
+	u32 hw_flags = 0;
+	u32 length = 0;
+	u8 *buffer = NULL;
+
+	if (!(flags & DSI_CTRL_CMD_FIFO_STORE)) {
+		pr_err("Memory DMA is not supported, use FIFO\n");
+		goto error;
+	}
+
+	rc = mipi_dsi_create_packet(&packet, msg);
+	if (rc) {
+		pr_err("Failed to create message packet, rc=%d\n", rc);
+		goto error;
+	}
+
+	if (flags & DSI_CTRL_CMD_FIFO_STORE) {
+		rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl,
+					       &packet,
+					       &buffer,
+					       &length);
+		if (rc) {
+			pr_err("[%s] failed to copy message, rc=%d\n",
+			       dsi_ctrl->name, rc);
+			goto error;
+		}
+		cmd.command =  (u32 *)buffer;
+		cmd.size = length;
+		cmd.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ?
+				     true : false;
+		cmd.is_master = (flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
+				  true : false;
+		cmd.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
+				  true : false;
+	}
+
+	hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ?
+			DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0;
+
+	if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER))
+		reinit_completion(&dsi_ctrl->int_info.cmd_dma_done);
+
+	if (flags & DSI_CTRL_CMD_FIFO_STORE)
+		dsi_ctrl->hw.ops.kickoff_fifo_command(&dsi_ctrl->hw,
+						      &cmd,
+						      hw_flags);
+
+	if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
+		u32 retry = 10;
+		u32 status = 0;
+		u64 error = 0;
+		u32 mask = (DSI_CMD_MODE_DMA_DONE);
+
+		while ((status == 0) && (retry > 0)) {
+			udelay(1000);
+			status = dsi_ctrl->hw.ops.get_interrupt_status(
+								&dsi_ctrl->hw);
+			error = dsi_ctrl->hw.ops.get_error_status(
+								&dsi_ctrl->hw);
+			status &= mask;
+			retry--;
+			dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
+								status);
+			dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
+							    error);
+		}
+		pr_debug("INT STATUS = %x, retry = %d\n", status, retry);
+		if (retry == 0)
+			pr_err("[DSI_%d]Command transfer failed\n",
+			       dsi_ctrl->index);
+
+		dsi_ctrl->hw.ops.reset_cmd_fifo(&dsi_ctrl->hw);
+	}
+error:
+	if (buffer)
+		devm_kfree(&dsi_ctrl->pdev->dev, buffer);
+	return rc;
+}
+
+static int dsi_set_max_return_size(struct dsi_ctrl *dsi_ctrl,
+				   const struct mipi_dsi_msg *rx_msg,
+				   u32 size)
+{
+	int rc = 0;
+	u8 tx[2] = { (u8)(size & 0xFF), (u8)(size >> 8) };
+	struct mipi_dsi_msg msg = {
+		.channel = rx_msg->channel,
+		.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
+		.tx_len = 2,
+		.tx_buf = tx,
+	};
+
+	rc = dsi_message_tx(dsi_ctrl, &msg, 0x0);
+	if (rc)
+		pr_err("failed to send max return size packet, rc=%d\n", rc);
+
+	return rc;
+}
+
+static int dsi_message_rx(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+	u32 rd_pkt_size;
+	u32 total_read_len;
+	u32 bytes_read = 0, tot_bytes_read = 0;
+	u32 current_read_len;
+	bool short_resp = false;
+	bool read_done = false;
+
+	if (msg->rx_len <= 2) {
+		short_resp = true;
+		rd_pkt_size = msg->rx_len;
+		total_read_len = 4;
+	} else {
+		short_resp = false;
+		current_read_len = 10;
+		if (msg->rx_len < current_read_len)
+			rd_pkt_size = msg->rx_len;
+		else
+			rd_pkt_size = current_read_len;
+
+		total_read_len = current_read_len + 6;
+	}
+
+	while (!read_done) {
+		rc = dsi_set_max_return_size(dsi_ctrl, msg, rd_pkt_size);
+		if (rc) {
+			pr_err("Failed to set max return packet size, rc=%d\n",
+			       rc);
+			goto error;
+		}
+
+		rc = dsi_message_tx(dsi_ctrl, msg, flags);
+		if (rc) {
+			pr_err("Message transmission failed, rc=%d\n", rc);
+			goto error;
+		}
+
+
+		tot_bytes_read += bytes_read;
+		if (short_resp)
+			read_done = true;
+		else if (msg->rx_len <= tot_bytes_read)
+			read_done = true;
+	}
+error:
+	return rc;
+}
+
+
+static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 lanes;
+	u32 ulps_lanes;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+	dsi_ctrl->hw.ops.ulps_request(&dsi_ctrl->hw, lanes);
+
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+
+	if ((lanes & ulps_lanes) != lanes) {
+		pr_err("Failed to enter ULPS, request=0x%x, actual=0x%x\n",
+		       lanes, ulps_lanes);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 ulps_lanes, lanes = 0;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+
+	if ((lanes & ulps_lanes) != lanes)
+		pr_err("Mismatch between lanes in ULPS\n");
+
+	lanes &= ulps_lanes;
+
+	dsi_ctrl->hw.ops.ulps_exit(&dsi_ctrl->hw, lanes);
+
+	/* 1 ms delay is recommended by specification */
+	udelay(1000);
+
+	dsi_ctrl->hw.ops.clear_ulps_request(&dsi_ctrl->hw, lanes);
+
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+	if (ulps_lanes & lanes) {
+		pr_err("Lanes (0x%x) stuck in ULPS\n", ulps_lanes);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	bool splash_enabled = false;
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	if (!splash_enabled) {
+		state->power_state = DSI_CTRL_POWER_OFF;
+		state->cmd_engine_state = DSI_CTRL_ENGINE_OFF;
+		state->vid_engine_state = DSI_CTRL_ENGINE_OFF;
+		state->pwr_enabled = false;
+		state->core_clk_enabled = false;
+		state->link_clk_enabled = false;
+		state->ulps_enabled = false;
+		state->clamp_enabled = false;
+		state->clk_source_set = false;
+	}
+
+	return rc;
+}
+
+int dsi_ctrl_intr_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	struct dsi_ctrl_interrupts *ints = &dsi_ctrl->int_info;
+
+	devm_free_irq(&dsi_ctrl->pdev->dev, ints->irq, dsi_ctrl);
+
+	return 0;
+}
+
+static int dsi_ctrl_buffer_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	if (dsi_ctrl->tx_cmd_buf) {
+		msm_gem_put_iova(dsi_ctrl->tx_cmd_buf, 0);
+
+		msm_gem_free_object(dsi_ctrl->tx_cmd_buf);
+		dsi_ctrl->tx_cmd_buf = NULL;
+	}
+
+	return 0;
+}
+
+int dsi_ctrl_buffer_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 iova = 0;
+
+	dsi_ctrl->tx_cmd_buf = msm_gem_new(dsi_ctrl->drm_dev,
+					   SZ_4K,
+					   MSM_BO_UNCACHED);
+
+	if (IS_ERR(dsi_ctrl->tx_cmd_buf)) {
+		rc = PTR_ERR(dsi_ctrl->tx_cmd_buf);
+		pr_err("failed to allocate gem, rc=%d\n", rc);
+		dsi_ctrl->tx_cmd_buf = NULL;
+		goto error;
+	}
+
+	dsi_ctrl->cmd_buffer_size = SZ_4K;
+
+	rc = msm_gem_get_iova(dsi_ctrl->tx_cmd_buf, 0, &iova);
+	if (rc) {
+		pr_err("failed to get iova, rc=%d\n", rc);
+		(void)dsi_ctrl_buffer_deinit(dsi_ctrl);
+		goto error;
+	}
+
+	if (iova & 0x07) {
+		pr_err("Tx command buffer is not 8 byte aligned\n");
+		rc = -ENOTSUPP;
+		(void)dsi_ctrl_buffer_deinit(dsi_ctrl);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_enable_io_clamp(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	bool en_ulps = dsi_ctrl->current_state.ulps_enabled;
+	u32 lanes = 0;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+
+	if (enable)
+		dsi_ctrl->hw.ops.clamp_enable(&dsi_ctrl->hw, lanes, en_ulps);
+	else
+		dsi_ctrl->hw.ops.clamp_disable(&dsi_ctrl->hw, lanes, en_ulps);
+
+	return 0;
+}
+
+static int dsi_ctrl_dev_probe(struct platform_device *pdev)
+{
+	struct dsi_ctrl *dsi_ctrl;
+	struct dsi_ctrl_list_item *item;
+	const struct of_device_id *id;
+	enum dsi_ctrl_version version;
+	u32 index = 0;
+	int rc = 0;
+
+	id = of_match_node(msm_dsi_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+
+	version = *(enum dsi_ctrl_version *)id->data;
+
+	item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
+	if (!item)
+		return -ENOMEM;
+
+	dsi_ctrl = devm_kzalloc(&pdev->dev, sizeof(*dsi_ctrl), GFP_KERNEL);
+	if (!dsi_ctrl)
+		return -ENOMEM;
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
+	if (rc) {
+		pr_debug("cell index not set, default to 0\n");
+		index = 0;
+	}
+
+	dsi_ctrl->index = index;
+
+	dsi_ctrl->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!dsi_ctrl->name)
+		dsi_ctrl->name = DSI_CTRL_DEFAULT_LABEL;
+
+	rc = dsi_ctrl_init_regmap(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse register information, rc = %d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_ctrl_clocks_init(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse clock information, rc = %d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_ctrl_supplies_init(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse voltage supplies, rc = %d\n", rc);
+		goto fail_clks;
+	}
+
+	dsi_ctrl->version = version;
+	rc = dsi_catalog_ctrl_setup(&dsi_ctrl->hw, dsi_ctrl->version,
+				    dsi_ctrl->index);
+	if (rc) {
+		pr_err("Catalog does not support version (%d)\n",
+		       dsi_ctrl->version);
+		goto fail_supplies;
+	}
+
+	rc = dsi_ctrl_axi_bus_client_init(pdev, dsi_ctrl);
+	if (rc)
+		pr_err("failed to init axi bus client, rc = %d\n", rc);
+
+	item->ctrl = dsi_ctrl;
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_add(&item->list, &dsi_ctrl_list);
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	mutex_init(&dsi_ctrl->ctrl_lock);
+
+	dsi_ctrl->pdev = pdev;
+	platform_set_drvdata(pdev, dsi_ctrl);
+
+	pr_debug("Probe successful for %s\n", dsi_ctrl->name);
+
+	return 0;
+
+fail_supplies:
+	(void)dsi_ctrl_supplies_deinit(dsi_ctrl);
+fail_clks:
+	(void)dsi_ctrl_clocks_deinit(dsi_ctrl);
+fail:
+	return rc;
+}
+
+static int dsi_ctrl_dev_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_ctrl *dsi_ctrl;
+	struct list_head *pos, *tmp;
+
+	dsi_ctrl = platform_get_drvdata(pdev);
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
+		struct dsi_ctrl_list_item *n = list_entry(pos,
+						  struct dsi_ctrl_list_item,
+						  list);
+		if (n->ctrl == dsi_ctrl) {
+			list_del(&n->list);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_axi_bus_client_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize axi bus client, rc = %d\n", rc);
+
+	rc = dsi_ctrl_supplies_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize voltage supplies, rc=%d\n", rc);
+
+	rc = dsi_ctrl_clocks_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize clocks, rc=%d\n", rc);
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+
+	mutex_destroy(&dsi_ctrl->ctrl_lock);
+	devm_kfree(&pdev->dev, dsi_ctrl);
+
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+static struct platform_driver dsi_ctrl_driver = {
+	.probe = dsi_ctrl_dev_probe,
+	.remove = dsi_ctrl_dev_remove,
+	.driver = {
+		.name = "drm_dsi_ctrl",
+		.of_match_table = msm_dsi_of_match,
+	},
+};
+
+/**
+ * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
+ * @of_node:    of_node of the DSI controller.
+ *
+ * Gets the DSI controller handle for the corresponding of_node. The ref count
+ * is incremented to one and all subsequent gets will fail until the original
+ * clients calls a put.
+ *
+ * Return: DSI Controller handle.
+ */
+struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node)
+{
+	struct list_head *pos, *tmp;
+	struct dsi_ctrl *ctrl = NULL;
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
+		struct dsi_ctrl_list_item *n;
+
+		n = list_entry(pos, struct dsi_ctrl_list_item, list);
+		if (n->ctrl->pdev->dev.of_node == of_node) {
+			ctrl = n->ctrl;
+			break;
+		}
+	}
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	if (!ctrl) {
+		pr_err("Device with of node not found\n");
+		ctrl = ERR_PTR(-EPROBE_DEFER);
+		return ctrl;
+	}
+
+	mutex_lock(&ctrl->ctrl_lock);
+	if (ctrl->refcount == 1) {
+		pr_err("[%s] Device in use\n", ctrl->name);
+		ctrl = ERR_PTR(-EBUSY);
+	} else {
+		ctrl->refcount++;
+	}
+	mutex_unlock(&ctrl->ctrl_lock);
+	return ctrl;
+}
+
+/**
+ * dsi_ctrl_put() - releases a dsi controller handle.
+ * @dsi_ctrl:       DSI controller handle.
+ *
+ * Releases the DSI controller. Driver will clean up all resources and puts back
+ * the DSI controller into reset state.
+ */
+void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl)
+{
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	if (dsi_ctrl->refcount == 0)
+		pr_err("Unbalanced dsi_ctrl_put call\n");
+	else
+		dsi_ctrl->refcount--;
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+}
+
+/**
+ * dsi_ctrl_drv_init() - initialize dsi controller driver.
+ * @dsi_ctrl:      DSI controller handle.
+ * @parent:        Parent directory for debug fs.
+ *
+ * Initializes DSI controller driver. Driver should be initialized after
+ * dsi_ctrl_get() succeeds.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || !parent) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_drv_state_init(dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to initialize driver state, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_debugfs_init(dsi_ctrl, parent);
+	if (rc) {
+		pr_err("[DSI_%d] failed to init debug fs, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Releases all resources acquired by dsi_ctrl_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_debugfs_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to release debugfs root, rc=%d\n", rc);
+
+	rc = dsi_ctrl_buffer_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("Failed to free cmd buffers, rc=%d\n", rc);
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
+ * @dsi_ctrl:         DSI controller handle.
+ *
+ * Performs a PHY software reset on the DSI controller. Reset should be done
+ * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
+ * not enabled.
+ *
+ * This function will fail if driver is in any other state.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	dsi_ctrl->hw.ops.phy_sw_reset(&dsi_ctrl->hw);
+
+	pr_debug("[DSI_%d] PHY soft reset done\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_seamless_timing_update() - update only controller timing
+ * @dsi_ctrl:          DSI controller handle.
+ * @timing:            New DSI timing info
+ *
+ * Updates host timing values to conduct a seamless transition to new timing
+ * For example, to update the porch values in a dynamic fps switch.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
+		struct dsi_mode_info *timing)
+{
+	struct dsi_mode_info *host_mode;
+	int rc = 0;
+
+	if (!dsi_ctrl || !timing) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,
+			DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto exit;
+	}
+
+	host_mode = &dsi_ctrl->host_config.video_timing;
+	memcpy(host_mode, timing, sizeof(*host_mode));
+
+	dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw, host_mode);
+
+exit:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_host_init() - Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * Initializes DSI controller hardware with host configuration provided by
+ * dsi_ctrl_update_host_config(). Initialization can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
+ * performed.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.lane_map);
+
+	dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
+				    &dsi_ctrl->host_config.common_config);
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) {
+		dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.common_config,
+					&dsi_ctrl->host_config.u.cmd_engine);
+
+		dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,
+				dsi_ctrl->host_config.video_timing.h_active,
+				dsi_ctrl->host_config.video_timing.h_active * 3,
+				dsi_ctrl->host_config.video_timing.v_active,
+				0x0);
+	} else {
+		dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.common_config,
+					&dsi_ctrl->host_config.u.video_engine);
+		dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
+					  &dsi_ctrl->host_config.video_timing);
+	}
+
+
+
+	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
+	dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw, 0x0);
+
+	/* Perform a soft reset before enabling dsi controller */
+	dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+	pr_debug("[DSI_%d]Host initialization complete\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * De-initializes DSI controller hardware. It can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		pr_err("driver state check failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] Host deinitization complete\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_update_host_config() - update dsi host configuration
+ * @dsi_ctrl:          DSI controller handle.
+ * @config:            DSI host configuration.
+ * @flags:             dsi_mode_flags modifying the behavior
+ *
+ * Updates driver with new Host configuration to use for host initialization.
+ * This function call will only update the software context. The stored
+ * configuration information will be used when the host is initialized.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
+				struct dsi_host_config *config,
+				int flags)
+{
+	int rc = 0;
+
+	if (!ctrl || !config) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_validate_panel_info(ctrl, config);
+	if (rc) {
+		pr_err("panel validation failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	if (!(flags & DSI_MODE_FLAG_SEAMLESS)) {
+		rc = dsi_ctrl_update_link_freqs(ctrl, config);
+		if (rc) {
+			pr_err("[%s] failed to update link frequencies, rc=%d\n",
+			       ctrl->name, rc);
+			goto error;
+		}
+	}
+
+	pr_debug("[DSI_%d]Host config updated\n", ctrl->index);
+	memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config));
+error:
+	mutex_unlock(&ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_validate_timing() - validate a video timing configuration
+ * @dsi_ctrl:       DSI controller handle.
+ * @timing:         Pointer to timing data.
+ *
+ * Driver will validate if the timing configuration is supported on the
+ * controller hardware.
+ *
+ * Return: error code if timing is not supported.
+ */
+int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
+			     struct dsi_mode_info *mode)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+
+	return rc;
+}
+
+/**
+ * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
+ * @dsi_ctrl:             DSI controller handle.
+ * @msg:                  Message to transfer on DSI link.
+ * @flags:                Modifiers for message transfer.
+ *
+ * Command transfer can be done only when command engine is enabled. The
+ * transfer API will block until either the command transfer finishes or
+ * the timeout value is reached. If the trigger is deferred, it will return
+ * without triggering the transfer. Command parameters are programmed to
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || !msg) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_vote_for_bandwidth(dsi_ctrl, true);
+	if (rc) {
+		pr_err("bandwidth request failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	if (flags & DSI_CTRL_CMD_READ) {
+		rc = dsi_message_rx(dsi_ctrl, msg, flags);
+		if (rc)
+			pr_err("read message failed, rc=%d\n", rc);
+	} else {
+		rc = dsi_message_tx(dsi_ctrl, msg, flags);
+		if (rc)
+			pr_err("command msg transfer failed, rc = %d\n", rc);
+	}
+
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
+
+	(void)dsi_ctrl_vote_for_bandwidth(dsi_ctrl, false);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
+ * @dsi_ctrl:              DSI controller handle.
+ * @flags:                 Modifiers.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
+{
+	int rc = 0;
+	u32 status = 0;
+	u32 mask = (DSI_CMD_MODE_DMA_DONE);
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	reinit_completion(&dsi_ctrl->int_info.cmd_dma_done);
+
+	dsi_ctrl->hw.ops.trigger_command_dma(&dsi_ctrl->hw);
+
+	if ((flags & DSI_CTRL_CMD_BROADCAST) &&
+	    (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
+		u32 retry = 10;
+
+		while ((status == 0) && (retry > 0)) {
+			udelay(1000);
+			status = dsi_ctrl->hw.ops.get_interrupt_status(
+								&dsi_ctrl->hw);
+			status &= mask;
+			retry--;
+			dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
+								status);
+		}
+		pr_debug("INT STATUS = %x, retry = %d\n", status, retry);
+		if (retry == 0)
+			pr_err("[DSI_%d]Command transfer failed\n",
+			       dsi_ctrl->index);
+	}
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_power_state() - set power state for dsi controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @state:             Power state.
+ *
+ * Set power state for DSI controller. Power state can be changed only when
+ * Controller, Video and Command engines are turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
+			     enum dsi_power_state state)
+{
+	int rc = 0;
+	bool core_clk_enable = false;
+	bool link_clk_enable = false;
+	bool reg_enable = false;
+	struct dsi_ctrl_state_info *drv_state;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_POWER_MAX)) {
+		pr_err("Invalid Params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE,
+				  state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_POWER_LINK_CLK_ON)
+		reg_enable = core_clk_enable = link_clk_enable = true;
+	else if (state == DSI_CTRL_POWER_CORE_CLK_ON)
+		reg_enable = core_clk_enable = true;
+	else if (state == DSI_CTRL_POWER_VREG_ON)
+		reg_enable = true;
+
+	drv_state = &dsi_ctrl->current_state;
+
+	if ((reg_enable) && (reg_enable != drv_state->pwr_enabled)) {
+		rc = dsi_ctrl_enable_supplies(dsi_ctrl, true);
+		if (rc) {
+			pr_err("[%d]failed to enable voltage supplies, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((core_clk_enable) &&
+	    (core_clk_enable != drv_state->core_clk_enabled)) {
+		rc = dsi_clk_enable_core_clks(&dsi_ctrl->clk_info.core_clks,
+					      true);
+		if (rc) {
+			pr_err("[%d] failed to enable core clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if (link_clk_enable != drv_state->link_clk_enabled) {
+		rc = dsi_clk_enable_link_clks(&dsi_ctrl->clk_info.link_clks,
+					      link_clk_enable);
+		if (rc) {
+			pr_err("[%d] failed to enable link clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((!core_clk_enable) &&
+	    (core_clk_enable != drv_state->core_clk_enabled)) {
+		rc = dsi_clk_enable_core_clks(&dsi_ctrl->clk_info.core_clks,
+					      false);
+		if (rc) {
+			pr_err("[%d] failed to disable core clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((!reg_enable) && (reg_enable != drv_state->pwr_enabled)) {
+		rc = dsi_ctrl_enable_supplies(dsi_ctrl, false);
+		if (rc) {
+			pr_err("[%d]failed to disable vreg supplies, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	pr_debug("[DSI_%d] Power state updated to %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @on:                enable/disable test pattern.
+ *
+ * Test pattern can be enabled only after Video engine (for video mode panels)
+ * or command engine (for cmd mode panels) is enabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (on) {
+		if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
+			dsi_ctrl->hw.ops.video_test_pattern_setup(&dsi_ctrl->hw,
+							  DSI_TEST_PATTERN_INC,
+							  0xFFFF);
+		} else {
+			dsi_ctrl->hw.ops.cmd_test_pattern_setup(
+							&dsi_ctrl->hw,
+							DSI_TEST_PATTERN_INC,
+							0xFFFF,
+							0x0);
+		}
+	}
+	dsi_ctrl->hw.ops.test_pattern_enable(&dsi_ctrl->hw, on);
+
+	pr_debug("[DSI_%d]Set test pattern state=%d\n", dsi_ctrl->index, on);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_host_engine_state() - set host engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Host engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
+				   enum dsi_engine_state state)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_ENGINE_ON)
+		dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
+	else
+		dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, false);
+
+	pr_debug("[DSI_%d] Set host engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_cmd_engine_state() - set command engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Command engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_ENGINE_ON)
+		dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
+	else
+		dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, false);
+
+	pr_debug("[DSI_%d] Set cmd engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_vid_engine_state() - set video engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Video engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state)
+{
+	int rc = 0;
+	bool on;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	on = (state == DSI_CTRL_ENGINE_ON) ? true : false;
+	dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
+
+	/* perform a reset when turning off video engine */
+	if (!on)
+		dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+
+	pr_debug("[DSI_%d] Set video engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
+ * @dsi_ctrl:         DSI controller handle.
+ * @enable:           enable/disable ULPS.
+ *
+ * ULPS can be enabled/disabled after DSI host engine is turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ULPS_TOGGLE, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (enable)
+		rc = dsi_enable_ulps(dsi_ctrl);
+	else
+		rc = dsi_disable_ulps(dsi_ctrl);
+
+	if (rc) {
+		pr_err("[DSI_%d] Ulps state change(%d) failed, rc=%d\n",
+		       dsi_ctrl->index, enable, rc);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] ULPS state = %d\n", dsi_ctrl->index, enable);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_ULPS_TOGGLE, enable);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
+ * @dsi_ctrl:             DSI controller handle.
+ * @enable:               enable/disable clamping.
+ *
+ * Clamps can be enabled/disabled while DSI contoller is still turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CLAMP_TOGGLE, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_enable_io_clamp(dsi_ctrl, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Failed to enable IO clamp\n", dsi_ctrl->index);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] Clamp state = %d\n", dsi_ctrl->index, enable);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CLAMP_TOGGLE, enable);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
+ * @dsi_ctrl:        DSI controller handle.
+ * @source_clks:     Source clocks for DSI link clocks.
+ *
+ * Clock source should be changed while link clocks are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
+			      struct dsi_clk_link_set *source_clks)
+{
+	int rc = 0;
+	u32 op_state = 0;
+
+	if (!dsi_ctrl || !source_clks) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	if (source_clks->pixel_clk && source_clks->byte_clk)
+		op_state = 1;
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_SET_CLK_SOURCE,
+				 op_state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_clk_update_parent(source_clks, &dsi_ctrl->clk_info.rcg_clks);
+	if (rc) {
+		pr_err("[DSI_%d]Failed to update link clk parent, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		(void)dsi_clk_update_parent(&dsi_ctrl->clk_info.pll_op_clks,
+					    &dsi_ctrl->clk_info.rcg_clks);
+		goto error;
+	}
+
+	dsi_ctrl->clk_info.pll_op_clks.byte_clk = source_clks->byte_clk;
+	dsi_ctrl->clk_info.pll_op_clks.pixel_clk = source_clks->pixel_clk;
+
+	pr_debug("[DSI_%d] Source clocks are updated\n", dsi_ctrl->index);
+
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_SET_CLK_SOURCE, op_state);
+
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_drv_register() - register platform driver for dsi controller
+ */
+void dsi_ctrl_drv_register(void)
+{
+	platform_driver_register(&dsi_ctrl_driver);
+}
+
+/**
+ * dsi_ctrl_drv_unregister() - unregister platform driver
+ */
+void dsi_ctrl_drv_unregister(void)
+{
+	platform_driver_unregister(&dsi_ctrl_driver);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..993a35cbf84a1572ef87b8138a63afa1a63cefad
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
@@ -0,0 +1,489 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CTRL_H_
+#define _DSI_CTRL_H_
+
+#include <linux/debugfs.h>
+
+#include "dsi_defs.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_clk_pwr.h"
+#include "drm_mipi_dsi.h"
+
+/*
+ * DSI Command transfer modifiers
+ * @DSI_CTRL_CMD_READ:             The current transfer involves reading data.
+ * @DSI_CTRL_CMD_BROADCAST:        The current transfer needs to be done in
+ *				   broadcast mode to multiple slaves.
+ * @DSI_CTRL_CMD_BROADCAST_MASTER: This controller is the master and the slaves
+ *				   sync to this trigger.
+ * @DSI_CTRL_CMD_DEFER_TRIGGER:    Defer the command trigger to later.
+ * @DSI_CTRL_CMD_FIFO_STORE:       Use FIFO for command transfer in place of
+ *				   reading data from memory.
+ */
+#define DSI_CTRL_CMD_READ             0x1
+#define DSI_CTRL_CMD_BROADCAST        0x2
+#define DSI_CTRL_CMD_BROADCAST_MASTER 0x4
+#define DSI_CTRL_CMD_DEFER_TRIGGER    0x8
+#define DSI_CTRL_CMD_FIFO_STORE       0x10
+
+/**
+ * enum dsi_power_state - defines power states for dsi controller.
+ * @DSI_CTRL_POWER_OFF:         DSI controller is powered down.
+ * @DSI_CTRL_POWER_VREG_ON:     Digital and analog supplies for DSI controller
+ *				are powered on.
+ * @DSI_CTRL_POWER_CORE_CLK_ON: DSI core clocks for register access are enabled.
+ * @DSI_CTRL_POWER_LINK_CLK_ON: DSI link clocks for link transfer are enabled.
+ * @DSI_CTRL_POWER_MAX:         Maximum value.
+ */
+enum dsi_power_state {
+	DSI_CTRL_POWER_OFF = 0,
+	DSI_CTRL_POWER_VREG_ON,
+	DSI_CTRL_POWER_CORE_CLK_ON,
+	DSI_CTRL_POWER_LINK_CLK_ON,
+	DSI_CTRL_POWER_MAX,
+};
+
+/**
+ * enum dsi_engine_state - define engine status for dsi controller.
+ * @DSI_CTRL_ENGINE_OFF:  Engine is turned off.
+ * @DSI_CTRL_ENGINE_ON:   Engine is turned on.
+ * @DSI_CTRL_ENGINE_MAX:  Maximum value.
+ */
+enum dsi_engine_state {
+	DSI_CTRL_ENGINE_OFF = 0,
+	DSI_CTRL_ENGINE_ON,
+	DSI_CTRL_ENGINE_MAX,
+};
+
+/**
+ * struct dsi_ctrl_power_info - digital and analog power supplies for dsi host
+ * @digital:  Digital power supply required to turn on DSI controller hardware.
+ * @host_pwr: Analog power supplies required to turn on DSI controller hardware.
+ *            Even though DSI controller it self does not require an analog
+ *            power supply, supplies required for PLL can be defined here to
+ *            allow proper control over these supplies.
+ */
+struct dsi_ctrl_power_info {
+	struct dsi_regulator_info digital;
+	struct dsi_regulator_info host_pwr;
+};
+
+/**
+ * struct dsi_ctrl_clk_info - clock information for DSI controller
+ * @core_clks:          Core clocks needed to access DSI controller registers.
+ * @link_clks:          Link clocks required to transmit data over DSI link.
+ * @rcg_clks:           Root clock generation clocks generated in MMSS_CC. The
+ *			output of the PLL is set as parent for these root
+ *			clocks. These clocks are specific to controller
+ *			instance.
+ * @mux_clks:           Mux clocks used for Dynamic refresh feature.
+ * @ext_clks:           External byte/pixel clocks from the MMSS block. These
+ *			clocks are set as parent to rcg clocks.
+ * @pll_op_clks:        TODO:
+ * @shadow_clks:        TODO:
+ */
+struct dsi_ctrl_clk_info {
+	/* Clocks parsed from DT */
+	struct dsi_core_clk_info core_clks;
+	struct dsi_link_clk_info link_clks;
+	struct dsi_clk_link_set rcg_clks;
+
+	/* Clocks set by DSI Manager */
+	struct dsi_clk_link_set mux_clks;
+	struct dsi_clk_link_set ext_clks;
+	struct dsi_clk_link_set pll_op_clks;
+	struct dsi_clk_link_set shadow_clks;
+};
+
+/**
+ * struct dsi_ctrl_bus_scale_info - Bus scale info for msm-bus bandwidth voting
+ * @bus_scale_table:        Bus scale voting usecases.
+ * @bus_handle:             Handle used for voting bandwidth.
+ * @refcount:               reference count.
+ */
+struct dsi_ctrl_bus_scale_info {
+	struct msm_bus_scale_pdata *bus_scale_table;
+	u32 bus_handle;
+	u32 refcount;
+};
+
+/**
+ * struct dsi_ctrl_state_info - current driver state information
+ * @power_state:        Controller power state.
+ * @cmd_engine_state:   Status of DSI command engine.
+ * @vid_engine_state:   Status of DSI video engine.
+ * @controller_state:   Status of DSI Controller engine.
+ * @pwr_enabled:        Set to true, if voltage supplies are enabled.
+ * @core_clk_enabled:   Set to true, if core clocks are enabled.
+ * @lin_clk_enabled:    Set to true, if link clocks are enabled.
+ * @ulps_enabled:       Set to true, if lanes are in ULPS state.
+ * @clamp_enabled:      Set to true, if PHY output is clamped.
+ * @clk_source_set:     Set to true, if parent is set for DSI link clocks.
+ */
+struct dsi_ctrl_state_info {
+	enum dsi_power_state power_state;
+	enum dsi_engine_state cmd_engine_state;
+	enum dsi_engine_state vid_engine_state;
+	enum dsi_engine_state controller_state;
+	bool pwr_enabled;
+	bool core_clk_enabled;
+	bool link_clk_enabled;
+	bool ulps_enabled;
+	bool clamp_enabled;
+	bool clk_source_set;
+	bool host_initialized;
+	bool tpg_enabled;
+};
+
+/**
+ * struct dsi_ctrl_interrupts - define interrupt information
+ * @irq:                   IRQ id for the DSI controller.
+ * @intr_lock:             Spinlock to protect access to interrupt registers.
+ * @interrupt_status:      Status interrupts which need to be serviced.
+ * @error_status:          Error interurpts which need to be serviced.
+ * @interrupts_enabled:    Status interrupts which are enabled.
+ * @errors_enabled:        Error interrupts which are enabled.
+ * @cmd_dma_done:          Completion signal for DSI_CMD_MODE_DMA_DONE interrupt
+ * @vid_frame_done:        Completion signal for DSI_VIDEO_MODE_FRAME_DONE int.
+ * @cmd_frame_done:        Completion signal for DSI_CMD_FRAME_DONE interrupt.
+ * @interrupt_done_work:   Work item for servicing status interrupts.
+ * @error_status_work:     Work item for servicing error interrupts.
+ */
+struct dsi_ctrl_interrupts {
+	u32 irq;
+	spinlock_t intr_lock; /* protects access to interrupt registers */
+	u32 interrupt_status;
+	u64 error_status;
+
+	u32 interrupts_enabled;
+	u64 errors_enabled;
+
+	struct completion cmd_dma_done;
+	struct completion vid_frame_done;
+	struct completion cmd_frame_done;
+
+	struct work_struct interrupt_done_work;
+	struct work_struct error_status_work;
+};
+
+/**
+ * struct dsi_ctrl - DSI controller object
+ * @pdev:                Pointer to platform device.
+ * @index:               Instance id.
+ * @name:                Name of the controller instance.
+ * @refcount:            ref counter.
+ * @ctrl_lock:           Mutex for hardware and object access.
+ * @drm_dev:             Pointer to DRM device.
+ * @version:             DSI controller version.
+ * @hw:                  DSI controller hardware object.
+ * @current_state;       Current driver and hardware state.
+ * @int_info:            Interrupt information.
+ * @clk_info:            Clock information.
+ * @pwr_info:            Power information.
+ * @axi_bus_info:        AXI bus information.
+ * @host_config:         Current host configuration.
+ * @tx_cmd_buf:          Tx command buffer.
+ * @cmd_buffer_size:     Size of command buffer.
+ * @debugfs_root:        Root for debugfs entries.
+ */
+struct dsi_ctrl {
+	struct platform_device *pdev;
+	u32 index;
+	const char *name;
+	u32 refcount;
+	struct mutex ctrl_lock;
+	struct drm_device *drm_dev;
+
+	enum dsi_ctrl_version version;
+	struct dsi_ctrl_hw hw;
+
+	/* Current state */
+	struct dsi_ctrl_state_info current_state;
+
+	struct dsi_ctrl_interrupts int_info;
+	/* Clock and power states */
+	struct dsi_ctrl_clk_info clk_info;
+	struct dsi_ctrl_power_info pwr_info;
+	struct dsi_ctrl_bus_scale_info axi_bus_info;
+
+	struct dsi_host_config host_config;
+	/* Command tx and rx */
+	struct drm_gem_object *tx_cmd_buf;
+	u32 cmd_buffer_size;
+
+	/* Debug Information */
+	struct dentry *debugfs_root;
+
+};
+
+/**
+ * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
+ * @of_node:    of_node of the DSI controller.
+ *
+ * Gets the DSI controller handle for the corresponding of_node. The ref count
+ * is incremented to one and all subsequent gets will fail until the original
+ * clients calls a put.
+ *
+ * Return: DSI Controller handle.
+ */
+struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node);
+
+/**
+ * dsi_ctrl_put() - releases a dsi controller handle.
+ * @dsi_ctrl:       DSI controller handle.
+ *
+ * Releases the DSI controller. Driver will clean up all resources and puts back
+ * the DSI controller into reset state.
+ */
+void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_drv_init() - initialize dsi controller driver.
+ * @dsi_ctrl:      DSI controller handle.
+ * @parent:        Parent directory for debug fs.
+ *
+ * Initializes DSI controller driver. Driver should be initialized after
+ * dsi_ctrl_get() succeeds.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent);
+
+/**
+ * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Releases all resources acquired by dsi_ctrl_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_validate_timing() - validate a video timing configuration
+ * @dsi_ctrl:       DSI controller handle.
+ * @timing:         Pointer to timing data.
+ *
+ * Driver will validate if the timing configuration is supported on the
+ * controller hardware.
+ *
+ * Return: error code if timing is not supported.
+ */
+int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
+			     struct dsi_mode_info *timing);
+
+/**
+ * dsi_ctrl_update_host_config() - update dsi host configuration
+ * @dsi_ctrl:          DSI controller handle.
+ * @config:            DSI host configuration.
+ * @flags:             dsi_mode_flags modifying the behavior
+ *
+ * Updates driver with new Host configuration to use for host initialization.
+ * This function call will only update the software context. The stored
+ * configuration information will be used when the host is initialized.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_update_host_config(struct dsi_ctrl *dsi_ctrl,
+				struct dsi_host_config *config,
+				int flags);
+
+/**
+ * dsi_ctrl_async_timing_update() - update only controller timing
+ * @dsi_ctrl:          DSI controller handle.
+ * @timing:            New DSI timing info
+ *
+ * Updates host timing values to asynchronously transition to new timing
+ * For example, to update the porch values in a seamless/dynamic fps switch.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
+		struct dsi_mode_info *timing);
+
+/**
+ * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
+ * @dsi_ctrl:         DSI controller handle.
+ *
+ * Performs a PHY software reset on the DSI controller. Reset should be done
+ * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
+ * not enabled.
+ *
+ * This function will fail if driver is in any other state.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_host_init() - Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * Initializes DSI controller hardware with host configuration provided by
+ * dsi_ctrl_update_host_config(). Initialization can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
+ * performed.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * De-initializes DSI controller hardware. It can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @on:                enable/disable test pattern.
+ *
+ * Test pattern can be enabled only after Video engine (for video mode panels)
+ * or command engine (for cmd mode panels) is enabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on);
+
+/**
+ * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
+ * @dsi_ctrl:             DSI controller handle.
+ * @msg:                  Message to transfer on DSI link.
+ * @flags:                Modifiers for message transfer.
+ *
+ * Command transfer can be done only when command engine is enabled. The
+ * transfer API will until either the command transfer finishes or the timeout
+ * value is reached. If the trigger is deferred, it will return without
+ * triggering the transfer. Command parameters are programmed to hardware.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags);
+
+/**
+ * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
+ * @dsi_ctrl:              DSI controller handle.
+ * @flags:                 Modifiers.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags);
+
+/**
+ * dsi_ctrl_set_power_state() - set power state for dsi controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @state:             Power state.
+ *
+ * Set power state for DSI controller. Power state can be changed only when
+ * Controller, Video and Command engines are turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
+			     enum dsi_power_state state);
+
+/**
+ * dsi_ctrl_set_cmd_engine_state() - set command engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Command engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_vid_engine_state() - set video engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Video engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_host_engine_state() - set host engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Host engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
+				   enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
+ * @dsi_ctrl:         DSI controller handle.
+ * @enable:           enable/disable ULPS.
+ *
+ * ULPS can be enabled/disabled after DSI host engine is turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable);
+
+/**
+ * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
+ * @dsi_ctrl:             DSI controller handle.
+ * @enable:               enable/disable clamping.
+ *
+ * Clamps can be enabled/disabled while DSI contoller is still turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_Ctrl, bool enable);
+
+/**
+ * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
+ * @dsi_ctrl:        DSI controller handle.
+ * @source_clks:     Source clocks for DSI link clocks.
+ *
+ * Clock source should be changed while link clocks are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
+			      struct dsi_clk_link_set *source_clks);
+
+/**
+ * dsi_ctrl_drv_register() - register platform driver for dsi controller
+ */
+void dsi_ctrl_drv_register(void);
+
+/**
+ * dsi_ctrl_drv_unregister() - unregister platform driver
+ */
+void dsi_ctrl_drv_unregister(void);
+
+#endif /* _DSI_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..b81cdaf4ba02f8b917818a9299e9fa7ba8dce738
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
@@ -0,0 +1,578 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CTRL_HW_H_
+#define _DSI_CTRL_HW_H_
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/bitmap.h>
+
+#include "dsi_defs.h"
+
+/**
+ * Modifier flag for command transmission. If this flag is set, command
+ * information is programmed to hardware and transmission is not triggered.
+ * Caller should call the trigger_command_dma() to start the transmission. This
+ * flag is valed for kickoff_command() and kickoff_fifo_command() operations.
+ */
+#define DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER            0x1
+
+/**
+ * enum dsi_ctrl_version - version of the dsi host controller
+ * @DSI_CTRL_VERSION_UNKNOWN: Unknown controller version
+ * @DSI_CTRL_VERSION_1_4:     DSI host v1.4 controller
+ * @DSI_CTRL_VERSION_2_0:     DSI host v2.0 controller
+ * @DSI_CTRL_VERSION_MAX:     max version
+ */
+enum dsi_ctrl_version {
+	DSI_CTRL_VERSION_UNKNOWN,
+	DSI_CTRL_VERSION_1_4,
+	DSI_CTRL_VERSION_2_0,
+	DSI_CTRL_VERSION_MAX
+};
+
+/**
+ * enum dsi_ctrl_hw_features - features supported by dsi host controller
+ * @DSI_CTRL_VIDEO_TPG:               Test pattern support for video mode.
+ * @DSI_CTRL_CMD_TPG:                 Test pattern support for command mode.
+ * @DSI_CTRL_VARIABLE_REFRESH_RATE:   variable panel timing
+ * @DSI_CTRL_DYNAMIC_REFRESH:         variable pixel clock rate
+ * @DSI_CTRL_NULL_PACKET_INSERTION:   NULL packet insertion
+ * @DSI_CTRL_DESKEW_CALIB:            Deskew calibration support
+ * @DSI_CTRL_DPHY:                    Controller support for DPHY
+ * @DSI_CTRL_CPHY:                    Controller support for CPHY
+ * @DSI_CTRL_MAX_FEATURES:
+ */
+enum dsi_ctrl_hw_features {
+	DSI_CTRL_VIDEO_TPG,
+	DSI_CTRL_CMD_TPG,
+	DSI_CTRL_VARIABLE_REFRESH_RATE,
+	DSI_CTRL_DYNAMIC_REFRESH,
+	DSI_CTRL_NULL_PACKET_INSERTION,
+	DSI_CTRL_DESKEW_CALIB,
+	DSI_CTRL_DPHY,
+	DSI_CTRL_CPHY,
+	DSI_CTRL_MAX_FEATURES
+};
+
+/**
+ * enum dsi_test_pattern - test pattern type
+ * @DSI_TEST_PATTERN_FIXED:     Test pattern is fixed, based on init value.
+ * @DSI_TEST_PATTERN_INC:       Incremental test pattern, base on init value.
+ * @DSI_TEST_PATTERN_POLY:      Pattern generated from polynomial and init val.
+ * @DSI_TEST_PATTERN_MAX:
+ */
+enum dsi_test_pattern {
+	DSI_TEST_PATTERN_FIXED = 0,
+	DSI_TEST_PATTERN_INC,
+	DSI_TEST_PATTERN_POLY,
+	DSI_TEST_PATTERN_MAX
+};
+
+/**
+ * enum dsi_status_int_type - status interrupts generated by DSI controller
+ * @DSI_CMD_MODE_DMA_DONE:        Command mode DMA packets are sent out.
+ * @DSI_CMD_STREAM0_FRAME_DONE:   A frame of command mode stream0 is sent out.
+ * @DSI_CMD_STREAM1_FRAME_DONE:   A frame of command mode stream1 is sent out.
+ * @DSI_CMD_STREAM2_FRAME_DONE:   A frame of command mode stream2 is sent out.
+ * @DSI_VIDEO_MODE_FRAME_DONE:    A frame of video mode stream is sent out.
+ * @DSI_BTA_DONE:                 A BTA is completed.
+ * @DSI_CMD_FRAME_DONE:           A frame of selected command mode stream is
+ *                                sent out by MDP.
+ * @DSI_DYN_REFRESH_DONE:         The dynamic refresh operation has completed.
+ * @DSI_DESKEW_DONE:              The deskew calibration operation has completed
+ * @DSI_DYN_BLANK_DMA_DONE:       The dynamic blankin DMA operation has
+ *                                completed.
+ */
+enum dsi_status_int_type {
+	DSI_CMD_MODE_DMA_DONE = BIT(0),
+	DSI_CMD_STREAM0_FRAME_DONE = BIT(1),
+	DSI_CMD_STREAM1_FRAME_DONE = BIT(2),
+	DSI_CMD_STREAM2_FRAME_DONE = BIT(3),
+	DSI_VIDEO_MODE_FRAME_DONE = BIT(4),
+	DSI_BTA_DONE = BIT(5),
+	DSI_CMD_FRAME_DONE = BIT(6),
+	DSI_DYN_REFRESH_DONE = BIT(7),
+	DSI_DESKEW_DONE = BIT(8),
+	DSI_DYN_BLANK_DMA_DONE = BIT(9)
+};
+
+/**
+ * enum dsi_error_int_type - error interrupts generated by DSI controller
+ * @DSI_RDBK_SINGLE_ECC_ERR:        Single bit ECC error in read packet.
+ * @DSI_RDBK_MULTI_ECC_ERR:         Multi bit ECC error in read packet.
+ * @DSI_RDBK_CRC_ERR:               CRC error in read packet.
+ * @DSI_RDBK_INCOMPLETE_PKT:        Incomplete read packet.
+ * @DSI_PERIPH_ERROR_PKT:           Error packet returned from peripheral,
+ * @DSI_LP_RX_TIMEOUT:              Low power reverse transmission timeout.
+ * @DSI_HS_TX_TIMEOUT:              High speed forward transmission timeout.
+ * @DSI_BTA_TIMEOUT:                BTA timeout.
+ * @DSI_PLL_UNLOCK:                 PLL has unlocked.
+ * @DSI_DLN0_ESC_ENTRY_ERR:         Incorrect LP Rx escape entry.
+ * @DSI_DLN0_ESC_SYNC_ERR:          LP Rx data is not byte aligned.
+ * @DSI_DLN0_LP_CONTROL_ERR:        Incorrect LP Rx state sequence.
+ * @DSI_PENDING_HS_TX_TIMEOUT:      Pending High-speed transfer timeout.
+ * @DSI_INTERLEAVE_OP_CONTENTION:   Interleave operation contention.
+ * @DSI_CMD_DMA_FIFO_UNDERFLOW:     Command mode DMA FIFO underflow.
+ * @DSI_CMD_MDP_FIFO_UNDERFLOW:     Command MDP FIFO underflow (failed to
+ *                                  receive one complete line from MDP).
+ * @DSI_DLN0_HS_FIFO_OVERFLOW:      High speed FIFO for data lane 0 overflows.
+ * @DSI_DLN1_HS_FIFO_OVERFLOW:      High speed FIFO for data lane 1 overflows.
+ * @DSI_DLN2_HS_FIFO_OVERFLOW:      High speed FIFO for data lane 2 overflows.
+ * @DSI_DLN3_HS_FIFO_OVERFLOW:      High speed FIFO for data lane 3 overflows.
+ * @DSI_DLN0_HS_FIFO_UNDERFLOW:     High speed FIFO for data lane 0 underflows.
+ * @DSI_DLN1_HS_FIFO_UNDERFLOW:     High speed FIFO for data lane 1 underflows.
+ * @DSI_DLN2_HS_FIFO_UNDERFLOW:     High speed FIFO for data lane 2 underflows.
+ * @DSI_DLN3_HS_FIFO_UNDERFLOW:     High speed FIFO for data lane 3 undeflows.
+ * @DSI_DLN0_LP0_CONTENTION:        PHY level contention while lane 0 is low.
+ * @DSI_DLN1_LP0_CONTENTION:        PHY level contention while lane 1 is low.
+ * @DSI_DLN2_LP0_CONTENTION:        PHY level contention while lane 2 is low.
+ * @DSI_DLN3_LP0_CONTENTION:        PHY level contention while lane 3 is low.
+ * @DSI_DLN0_LP1_CONTENTION:        PHY level contention while lane 0 is high.
+ * @DSI_DLN1_LP1_CONTENTION:        PHY level contention while lane 1 is high.
+ * @DSI_DLN2_LP1_CONTENTION:        PHY level contention while lane 2 is high.
+ * @DSI_DLN3_LP1_CONTENTION:        PHY level contention while lane 3 is high.
+ */
+enum dsi_error_int_type {
+	DSI_RDBK_SINGLE_ECC_ERR = BIT(0),
+	DSI_RDBK_MULTI_ECC_ERR = BIT(1),
+	DSI_RDBK_CRC_ERR = BIT(2),
+	DSI_RDBK_INCOMPLETE_PKT = BIT(3),
+	DSI_PERIPH_ERROR_PKT = BIT(4),
+	DSI_LP_RX_TIMEOUT = BIT(5),
+	DSI_HS_TX_TIMEOUT = BIT(6),
+	DSI_BTA_TIMEOUT = BIT(7),
+	DSI_PLL_UNLOCK = BIT(8),
+	DSI_DLN0_ESC_ENTRY_ERR = BIT(9),
+	DSI_DLN0_ESC_SYNC_ERR = BIT(10),
+	DSI_DLN0_LP_CONTROL_ERR = BIT(11),
+	DSI_PENDING_HS_TX_TIMEOUT = BIT(12),
+	DSI_INTERLEAVE_OP_CONTENTION = BIT(13),
+	DSI_CMD_DMA_FIFO_UNDERFLOW = BIT(14),
+	DSI_CMD_MDP_FIFO_UNDERFLOW = BIT(15),
+	DSI_DLN0_HS_FIFO_OVERFLOW = BIT(16),
+	DSI_DLN1_HS_FIFO_OVERFLOW = BIT(17),
+	DSI_DLN2_HS_FIFO_OVERFLOW = BIT(18),
+	DSI_DLN3_HS_FIFO_OVERFLOW = BIT(19),
+	DSI_DLN0_HS_FIFO_UNDERFLOW = BIT(20),
+	DSI_DLN1_HS_FIFO_UNDERFLOW = BIT(21),
+	DSI_DLN2_HS_FIFO_UNDERFLOW = BIT(22),
+	DSI_DLN3_HS_FIFO_UNDERFLOW = BIT(23),
+	DSI_DLN0_LP0_CONTENTION = BIT(24),
+	DSI_DLN1_LP0_CONTENTION = BIT(25),
+	DSI_DLN2_LP0_CONTENTION = BIT(26),
+	DSI_DLN3_LP0_CONTENTION = BIT(27),
+	DSI_DLN0_LP1_CONTENTION = BIT(28),
+	DSI_DLN1_LP1_CONTENTION = BIT(29),
+	DSI_DLN2_LP1_CONTENTION = BIT(30),
+	DSI_DLN3_LP1_CONTENTION = BIT(31),
+};
+
+/**
+ * struct dsi_ctrl_cmd_dma_info - command buffer information
+ * @offset:        IOMMU VA for command buffer address.
+ * @length:        Length of the command buffer.
+ * @en_broadcast:  Enable broadcast mode if set to true.
+ * @is_master:     Is master in broadcast mode.
+ * @use_lpm:       Use low power mode for command transmission.
+ */
+struct dsi_ctrl_cmd_dma_info {
+	u32 offset;
+	u32 length;
+	bool en_broadcast;
+	bool is_master;
+	bool use_lpm;
+};
+
+/**
+ * struct dsi_ctrl_cmd_dma_fifo_info - command payload tp be sent using FIFO
+ * @command:        VA for command buffer.
+ * @size:           Size of the command buffer.
+ * @en_broadcast:   Enable broadcast mode if set to true.
+ * @is_master:      Is master in broadcast mode.
+ * @use_lpm:        Use low power mode for command transmission.
+ */
+struct dsi_ctrl_cmd_dma_fifo_info {
+	u32 *command;
+	u32 size;
+	bool en_broadcast;
+	bool is_master;
+	bool use_lpm;
+};
+
+struct dsi_ctrl_hw;
+
+/**
+ * struct dsi_ctrl_hw_ops - operations supported by dsi host hardware
+ */
+struct dsi_ctrl_hw_ops {
+
+	/**
+	 * host_setup() - Setup DSI host configuration
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @config:        Configuration for DSI host controller
+	 */
+	void (*host_setup)(struct dsi_ctrl_hw *ctrl,
+			   struct dsi_host_common_cfg *config);
+
+	/**
+	 * video_engine_en() - enable DSI video engine
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @on:            Enable/disabel video engine.
+	 */
+	void (*video_engine_en)(struct dsi_ctrl_hw *ctrl, bool on);
+
+	/**
+	 * video_engine_setup() - Setup dsi host controller for video mode
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @common_cfg:    Common configuration parameters.
+	 * @cfg:           Video mode configuration.
+	 *
+	 * Set up DSI video engine with a specific configuration. Controller and
+	 * video engine are not enabled as part of this function.
+	 */
+	void (*video_engine_setup)(struct dsi_ctrl_hw *ctrl,
+				   struct dsi_host_common_cfg *common_cfg,
+				   struct dsi_video_engine_cfg *cfg);
+
+	/**
+	 * set_video_timing() - set up the timing for video frame
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @mode:          Video mode information.
+	 *
+	 * Set up the video timing parameters for the DSI video mode operation.
+	 */
+	void (*set_video_timing)(struct dsi_ctrl_hw *ctrl,
+				 struct dsi_mode_info *mode);
+
+	/**
+	 * cmd_engine_setup() - setup dsi host controller for command mode
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @common_cfg:    Common configuration parameters.
+	 * @cfg:           Command mode configuration.
+	 *
+	 * Setup DSI CMD engine with a specific configuration. Controller and
+	 * command engine are not enabled as part of this function.
+	 */
+	void (*cmd_engine_setup)(struct dsi_ctrl_hw *ctrl,
+				 struct dsi_host_common_cfg *common_cfg,
+				 struct dsi_cmd_engine_cfg *cfg);
+
+	/**
+	 * setup_cmd_stream() - set up parameters for command pixel streams
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @width_in_pixels:   Width of the stream in pixels.
+	 * @h_stride:          Horizontal stride in bytes.
+	 * @height_inLines:    Number of lines in the stream.
+	 * @vc_id:             stream_id.
+	 *
+	 * Setup parameters for command mode pixel stream size.
+	 */
+	void (*setup_cmd_stream)(struct dsi_ctrl_hw *ctrl,
+				 u32 width_in_pixels,
+				 u32 h_stride,
+				 u32 height_in_lines,
+				 u32 vc_id);
+
+	/**
+	 * ctrl_en() - enable DSI controller engine
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @on:            turn on/off the DSI controller engine.
+	 */
+	void (*ctrl_en)(struct dsi_ctrl_hw *ctrl, bool on);
+
+	/**
+	 * cmd_engine_en() - enable DSI controller command engine
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @on:            Turn on/off the DSI command engine.
+	 */
+	void (*cmd_engine_en)(struct dsi_ctrl_hw *ctrl, bool on);
+
+	/**
+	 * phy_sw_reset() - perform a soft reset on the PHY.
+	 * @ctrl:        Pointer to the controller host hardware.
+	 */
+	void (*phy_sw_reset)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * soft_reset() - perform a soft reset on DSI controller
+	 * @ctrl:          Pointer to the controller host hardware.
+	 *
+	 * The video, command and controller engines will be disable before the
+	 * reset is triggered. These engines will not be enabled after the reset
+	 * is complete. Caller must re-enable the engines.
+	 *
+	 * If the reset is done while MDP timing engine is turned on, the video
+	 * enigne should be re-enabled only during the vertical blanking time.
+	 */
+	void (*soft_reset)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * setup_lane_map() - setup mapping between logical and physical lanes
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @lane_map:      Structure defining the mapping between DSI logical
+	 *                 lanes and physical lanes.
+	 */
+	void (*setup_lane_map)(struct dsi_ctrl_hw *ctrl,
+			       struct dsi_lane_mapping *lane_map);
+
+	/**
+	 * kickoff_command() - transmits commands stored in memory
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @cmd:           Command information.
+	 * @flags:         Modifiers for command transmission.
+	 *
+	 * The controller hardware is programmed with address and size of the
+	 * command buffer. The transmission is kicked off if
+	 * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
+	 * set, caller should make a separate call to trigger_command_dma() to
+	 * transmit the command.
+	 */
+	void (*kickoff_command)(struct dsi_ctrl_hw *ctrl,
+				struct dsi_ctrl_cmd_dma_info *cmd,
+				u32 flags);
+
+	/**
+	 * kickoff_fifo_command() - transmits a command using FIFO in dsi
+	 *                          hardware.
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @cmd:           Command information.
+	 * @flags:         Modifiers for command transmission.
+	 *
+	 * The controller hardware FIFO is programmed with command header and
+	 * payload. The transmission is kicked off if
+	 * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
+	 * set, caller should make a separate call to trigger_command_dma() to
+	 * transmit the command.
+	 */
+	void (*kickoff_fifo_command)(struct dsi_ctrl_hw *ctrl,
+				     struct dsi_ctrl_cmd_dma_fifo_info *cmd,
+				     u32 flags);
+
+	void (*reset_cmd_fifo)(struct dsi_ctrl_hw *ctrl);
+	/**
+	 * trigger_command_dma() - trigger transmission of command buffer.
+	 * @ctrl:          Pointer to the controller host hardware.
+	 *
+	 * This trigger can be only used if there was a prior call to
+	 * kickoff_command() of kickoff_fifo_command() with
+	 * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag.
+	 */
+	void (*trigger_command_dma)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * get_cmd_read_data() - get data read from the peripheral
+	 * @ctrl:           Pointer to the controller host hardware.
+	 * @rd_buf:         Buffer where data will be read into.
+	 * @total_read_len: Number of bytes to read.
+	 */
+	u32 (*get_cmd_read_data)(struct dsi_ctrl_hw *ctrl,
+				 u8 *rd_buf,
+				 u32 total_read_len);
+
+	/**
+	 * ulps_request() - request ulps entry for specified lanes
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @lanes:         ORed list of lanes (enum dsi_data_lanes) which need
+	 *                 to enter ULPS.
+	 *
+	 * Caller should check if lanes are in ULPS mode by calling
+	 * get_lanes_in_ulps() operation.
+	 */
+	void (*ulps_request)(struct dsi_ctrl_hw *ctrl, u32 lanes);
+
+	/**
+	 * ulps_exit() - exit ULPS on specified lanes
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @lanes:         ORed list of lanes (enum dsi_data_lanes) which need
+	 *                 to exit ULPS.
+	 *
+	 * Caller should check if lanes are in active mode by calling
+	 * get_lanes_in_ulps() operation.
+	 */
+	void (*ulps_exit)(struct dsi_ctrl_hw *ctrl, u32 lanes);
+
+	/**
+	 * clear_ulps_request() - clear ulps request once all lanes are active
+	 * @ctrl:          Pointer to controller host hardware.
+	 * @lanes:         ORed list of lanes (enum dsi_data_lanes).
+	 *
+	 * ULPS request should be cleared after the lanes have exited ULPS.
+	 */
+	void (*clear_ulps_request)(struct dsi_ctrl_hw *ctrl, u32 lanes);
+
+	/**
+	 * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
+	 * @ctrl:          Pointer to the controller host hardware.
+	 *
+	 * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
+	 * state. If 0 is returned, all the lanes are active.
+	 *
+	 * Return: List of lanes in ULPS state.
+	 */
+	u32 (*get_lanes_in_ulps)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * clamp_enable() - enable DSI clamps to keep PHY driving a stable link
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @lanes:         ORed list of lanes which need to be clamped.
+	 * @enable_ulps:   TODO:??
+	 */
+	void (*clamp_enable)(struct dsi_ctrl_hw *ctrl,
+			     u32 lanes,
+			     bool enable_ulps);
+
+	/**
+	 * clamp_disable() - disable DSI clamps
+	 * @ctrl:         Pointer to the controller host hardware.
+	 * @lanes:        ORed list of lanes which need to have clamps released.
+	 * @disable_ulps: TODO:??
+	 */
+	void (*clamp_disable)(struct dsi_ctrl_hw *ctrl,
+			      u32 lanes,
+			      bool disable_ulps);
+
+	/**
+	 * get_interrupt_status() - returns the interrupt status
+	 * @ctrl:          Pointer to the controller host hardware.
+	 *
+	 * Returns the ORed list of interrupts(enum dsi_status_int_type) that
+	 * are active. This list does not include any error interrupts. Caller
+	 * should call get_error_status for error interrupts.
+	 *
+	 * Return: List of active interrupts.
+	 */
+	u32 (*get_interrupt_status)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * clear_interrupt_status() - clears the specified interrupts
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @ints:          List of interrupts to be cleared.
+	 */
+	void (*clear_interrupt_status)(struct dsi_ctrl_hw *ctrl, u32 ints);
+
+	/**
+	 * enable_status_interrupts() - enable the specified interrupts
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @ints:          List of interrupts to be enabled.
+	 *
+	 * Enables the specified interrupts. This list will override the
+	 * previous interrupts enabled through this function. Caller has to
+	 * maintain the state of the interrupts enabled. To disable all
+	 * interrupts, set ints to 0.
+	 */
+	void (*enable_status_interrupts)(struct dsi_ctrl_hw *ctrl, u32 ints);
+
+	/**
+	 * get_error_status() - returns the error status
+	 * @ctrl:          Pointer to the controller host hardware.
+	 *
+	 * Returns the ORed list of errors(enum dsi_error_int_type) that are
+	 * active. This list does not include any status interrupts. Caller
+	 * should call get_interrupt_status for status interrupts.
+	 *
+	 * Return: List of active error interrupts.
+	 */
+	u64 (*get_error_status)(struct dsi_ctrl_hw *ctrl);
+
+	/**
+	 * clear_error_status() - clears the specified errors
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @errors:          List of errors to be cleared.
+	 */
+	void (*clear_error_status)(struct dsi_ctrl_hw *ctrl, u64 errors);
+
+	/**
+	 * enable_error_interrupts() - enable the specified interrupts
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @errors:        List of errors to be enabled.
+	 *
+	 * Enables the specified interrupts. This list will override the
+	 * previous interrupts enabled through this function. Caller has to
+	 * maintain the state of the interrupts enabled. To disable all
+	 * interrupts, set errors to 0.
+	 */
+	void (*enable_error_interrupts)(struct dsi_ctrl_hw *ctrl, u64 errors);
+
+	/**
+	 * video_test_pattern_setup() - setup test pattern engine for video mode
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @type:          Type of test pattern.
+	 * @init_val:      Initial value to use for generating test pattern.
+	 */
+	void (*video_test_pattern_setup)(struct dsi_ctrl_hw *ctrl,
+					 enum dsi_test_pattern type,
+					 u32 init_val);
+
+	/**
+	 * cmd_test_pattern_setup() - setup test patttern engine for cmd mode
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @type:          Type of test pattern.
+	 * @init_val:      Initial value to use for generating test pattern.
+	 * @stream_id:     Stream Id on which packets are generated.
+	 */
+	void (*cmd_test_pattern_setup)(struct dsi_ctrl_hw *ctrl,
+				       enum dsi_test_pattern  type,
+				       u32 init_val,
+				       u32 stream_id);
+
+	/**
+	 * test_pattern_enable() - enable test pattern engine
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @enable:        Enable/Disable test pattern engine.
+	 */
+	void (*test_pattern_enable)(struct dsi_ctrl_hw *ctrl, bool enable);
+
+	/**
+	 * trigger_cmd_test_pattern() - trigger a command mode frame update with
+	 *                              test pattern
+	 * @ctrl:          Pointer to the controller host hardware.
+	 * @stream_id:     Stream on which frame update is sent.
+	 */
+	void (*trigger_cmd_test_pattern)(struct dsi_ctrl_hw *ctrl,
+					 u32 stream_id);
+
+	ssize_t (*reg_dump_to_buffer)(struct dsi_ctrl_hw *ctrl,
+				      char *buf,
+				      u32 size);
+};
+
+/*
+ * struct dsi_ctrl_hw - DSI controller hardware object specific to an instance
+ * @base:           VA for the DSI controller base address.
+ * @length:         Length of the DSI controller register map.
+ * @index:          Instance ID of the controller.
+ * @feature_map:    Features supported by the DSI controller.
+ * @ops:            Function pointers to the operations supported by the
+ *                  controller.
+ */
+struct dsi_ctrl_hw {
+	void __iomem *base;
+	u32 length;
+	void __iomem *mmss_misc_base;
+	u32 mmss_misc_length;
+	u32 index;
+
+	/* features */
+	DECLARE_BITMAP(feature_map, DSI_CTRL_MAX_FEATURES);
+	struct dsi_ctrl_hw_ops ops;
+
+	/* capabilities */
+	u32 supported_interrupts;
+	u64 supported_errors;
+};
+
+#endif /* _DSI_CTRL_HW_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..ca04eedd6af19ed24046447730ed2176a13591ea
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c
@@ -0,0 +1,1512 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "dsi-hw:" fmt
+#include <linux/delay.h>
+
+#include "dsi_ctrl_hw.h"
+#include "dsi_ctrl_reg_1_4.h"
+#include "dsi_hw.h"
+
+#define MMSS_MISC_CLAMP_REG_OFF           0x0014
+
+/* Unsupported formats default to RGB888 */
+static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
+	0x6, 0x7, 0x8, 0x8, 0x0, 0x3, 0x4 };
+static const u8 video_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
+	0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3 };
+
+
+/**
+ * dsi_setup_trigger_controls() - setup dsi trigger configurations
+ * @ctrl:             Pointer to the controller host hardware.
+ * @cfg:              DSI host configuration that is common to both video and
+ *                    command modes.
+ */
+static void dsi_setup_trigger_controls(struct dsi_ctrl_hw *ctrl,
+				       struct dsi_host_common_cfg *cfg)
+{
+	u32 reg = 0;
+	const u8 trigger_map[DSI_TRIGGER_MAX] = {
+		0x0, 0x2, 0x1, 0x4, 0x5, 0x6 };
+
+	reg |= (cfg->te_mode == DSI_TE_ON_EXT_PIN) ? BIT(31) : 0;
+	reg |= (trigger_map[cfg->dma_cmd_trigger] & 0x7);
+	reg |= (trigger_map[cfg->mdp_cmd_trigger] & 0x7) << 4;
+	DSI_W32(ctrl, DSI_TRIG_CTRL, reg);
+}
+
+/**
+ * dsi_ctrl_hw_14_host_setup() - setup dsi host configuration
+ * @ctrl:             Pointer to the controller host hardware.
+ * @cfg:              DSI host configuration that is common to both video and
+ *                    command modes.
+ */
+void dsi_ctrl_hw_14_host_setup(struct dsi_ctrl_hw *ctrl,
+			       struct dsi_host_common_cfg *cfg)
+{
+	u32 reg_value = 0;
+
+	dsi_setup_trigger_controls(ctrl, cfg);
+
+	/* Setup clocking timing controls */
+	reg_value = ((cfg->t_clk_post & 0x3F) << 8);
+	reg_value |= (cfg->t_clk_pre & 0x3F);
+	DSI_W32(ctrl, DSI_CLKOUT_TIMING_CTRL, reg_value);
+
+	/* EOT packet control */
+	reg_value = cfg->append_tx_eot ? 1 : 0;
+	reg_value |= (cfg->ignore_rx_eot ? (1 << 4) : 0);
+	DSI_W32(ctrl, DSI_EOT_PACKET_CTRL, reg_value);
+
+	/* Turn on dsi clocks */
+	DSI_W32(ctrl, DSI_CLK_CTRL, 0x23F);
+
+	/* Setup DSI control register */
+	reg_value = 0;
+	reg_value |= (cfg->en_crc_check ? BIT(24) : 0);
+	reg_value |= (cfg->en_ecc_check ? BIT(20) : 0);
+	reg_value |= BIT(8); /* Clock lane */
+	reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_3) ? BIT(7) : 0);
+	reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_2) ? BIT(6) : 0);
+	reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_1) ? BIT(5) : 0);
+	reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_0) ? BIT(4) : 0);
+
+	DSI_W32(ctrl, DSI_CTRL, reg_value);
+
+	pr_debug("[DSI_%d]Host configuration complete\n", ctrl->index);
+}
+
+/**
+ * phy_sw_reset() - perform a soft reset on the PHY.
+ * @ctrl:        Pointer to the controller host hardware.
+ */
+void dsi_ctrl_hw_14_phy_sw_reset(struct dsi_ctrl_hw *ctrl)
+{
+	DSI_W32(ctrl, DSI_PHY_SW_RESET, 0x1);
+	udelay(1000);
+	DSI_W32(ctrl, DSI_PHY_SW_RESET, 0x0);
+	udelay(100);
+
+	pr_debug("[DSI_%d] phy sw reset done\n", ctrl->index);
+}
+
+/**
+ * soft_reset() - perform a soft reset on DSI controller
+ * @ctrl:          Pointer to the controller host hardware.
+ *
+ * The video, command and controller engines will be disable before the
+ * reset is triggered. These engines will not be enabled after the reset
+ * is complete. Caller must re-enable the engines.
+ *
+ * If the reset is done while MDP timing engine is turned on, the video
+ * enigne should be re-enabled only during the vertical blanking time.
+ */
+void dsi_ctrl_hw_14_soft_reset(struct dsi_ctrl_hw *ctrl)
+{
+	u32 reg = 0;
+	u32 reg_ctrl = 0;
+
+	/* Clear DSI_EN, VIDEO_MODE_EN, CMD_MODE_EN */
+	reg_ctrl = DSI_R32(ctrl, DSI_CTRL);
+	DSI_W32(ctrl, DSI_CTRL, reg_ctrl & ~0x7);
+
+	/* Force enable PCLK, BYTECLK, AHBM_HCLK */
+	reg = DSI_R32(ctrl, DSI_CLK_CTRL);
+	reg |= 0x23F;
+	DSI_W32(ctrl, DSI_CLK_CTRL, reg);
+
+	/* Trigger soft reset */
+	DSI_W32(ctrl, DSI_SOFT_RESET, 0x1);
+	udelay(1);
+	DSI_W32(ctrl, DSI_SOFT_RESET, 0x0);
+
+	/* Disable force clock on */
+	reg &= ~(BIT(20) | BIT(11));
+	DSI_W32(ctrl, DSI_CLK_CTRL, reg);
+
+	/* Re-enable DSI controller */
+	DSI_W32(ctrl, DSI_CTRL, reg_ctrl);
+	pr_debug("[DSI_%d] ctrl soft reset done\n", ctrl->index);
+}
+
+/**
+ * set_video_timing() - set up the timing for video frame
+ * @ctrl:          Pointer to controller host hardware.
+ * @mode:          Video mode information.
+ *
+ * Set up the video timing parameters for the DSI video mode operation.
+ */
+void dsi_ctrl_hw_14_set_video_timing(struct dsi_ctrl_hw *ctrl,
+				     struct dsi_mode_info *mode)
+{
+	u32 reg = 0;
+	u32 hs_start = 0;
+	u32 hs_end, active_h_start, active_h_end, h_total;
+	u32 vs_start = 0, vs_end = 0;
+	u32 vpos_start = 0, vpos_end, active_v_start, active_v_end, v_total;
+
+	hs_end = mode->h_sync_width;
+	active_h_start = mode->h_sync_width + mode->h_back_porch;
+	active_h_end = active_h_start + mode->h_active;
+	h_total = (mode->h_sync_width + mode->h_back_porch + mode->h_active +
+		   mode->h_front_porch) - 1;
+
+	vpos_end = mode->v_sync_width;
+	active_v_start = mode->v_sync_width + mode->v_back_porch;
+	active_v_end = active_v_start + mode->v_active;
+	v_total = (mode->v_sync_width + mode->v_back_porch + mode->v_active +
+		   mode->v_front_porch) - 1;
+
+	reg = ((active_h_end & 0xFFFF) << 16) | (active_h_start & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_H, reg);
+
+	reg = ((active_v_end & 0xFFFF) << 16) | (active_v_start & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_V, reg);
+
+	reg = ((v_total & 0xFFFF) << 16) | (h_total & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_TOTAL, reg);
+
+	reg = ((hs_end & 0xFFFF) << 16) | (hs_start & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_HSYNC, reg);
+
+	reg = ((vs_end & 0xFFFF) << 16) | (vs_start & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC, reg);
+
+	reg = ((vpos_end & 0xFFFF) << 16) | (vpos_start & 0xFFFF);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC_VPOS, reg);
+
+	/* TODO: HS TIMER value? */
+	DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08);
+	DSI_W32(ctrl, DSI_MISR_VIDEO_CTRL, 0x10100);
+	DSI_W32(ctrl, DSI_DSI_TIMING_FLUSH, 0x1);
+	pr_debug("[DSI_%d] ctrl video parameters updated\n", ctrl->index);
+}
+
+/**
+ * setup_cmd_stream() - set up parameters for command pixel streams
+ * @ctrl:          Pointer to controller host hardware.
+ * @width_in_pixels:   Width of the stream in pixels.
+ * @h_stride:          Horizontal stride in bytes.
+ * @height_inLines:    Number of lines in the stream.
+ * @vc_id:             stream_id
+ *
+ * Setup parameters for command mode pixel stream size.
+ */
+void dsi_ctrl_hw_14_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
+				     u32 width_in_pixels,
+				     u32 h_stride,
+				     u32 height_in_lines,
+				     u32 vc_id)
+{
+	u32 reg = 0;
+
+	reg = (h_stride + 1) << 16;
+	reg |= (vc_id & 0x3) << 8;
+	reg |= 0x39; /* packet data type */
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_CTRL, reg);
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_CTRL, reg);
+
+	reg = (height_in_lines << 16) | width_in_pixels;
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL, reg);
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL, reg);
+}
+
+/**
+ * video_engine_setup() - Setup dsi host controller for video mode
+ * @ctrl:          Pointer to controller host hardware.
+ * @common_cfg:    Common configuration parameters.
+ * @cfg:           Video mode configuration.
+ *
+ * Set up DSI video engine with a specific configuration. Controller and
+ * video engine are not enabled as part of this function.
+ */
+void dsi_ctrl_hw_14_video_engine_setup(struct dsi_ctrl_hw *ctrl,
+				       struct dsi_host_common_cfg *common_cfg,
+				       struct dsi_video_engine_cfg *cfg)
+{
+	u32 reg = 0;
+
+	reg |= (cfg->last_line_interleave_en ? BIT(31) : 0);
+	reg |= (cfg->pulse_mode_hsa_he ? BIT(28) : 0);
+	reg |= (cfg->hfp_lp11_en ? BIT(24) : 0);
+	reg |= (cfg->hbp_lp11_en ? BIT(20) : 0);
+	reg |= (cfg->hsa_lp11_en ? BIT(16) : 0);
+	reg |= (cfg->eof_bllp_lp11_en ? BIT(15) : 0);
+	reg |= (cfg->bllp_lp11_en ? BIT(12) : 0);
+	reg |= (cfg->traffic_mode & 0x3) << 8;
+	reg |= (cfg->vc_id & 0x3);
+	reg |= (video_mode_format_map[common_cfg->dst_format] & 0x3) << 4;
+	DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
+
+	reg = (common_cfg->swap_mode & 0x7) << 12;
+	reg |= (common_cfg->bit_swap_red ? BIT(0) : 0);
+	reg |= (common_cfg->bit_swap_green ? BIT(4) : 0);
+	reg |= (common_cfg->bit_swap_blue ? BIT(8) : 0);
+	DSI_W32(ctrl, DSI_VIDEO_MODE_DATA_CTRL, reg);
+	/* Enable Timing double buffering */
+	DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x1);
+
+
+	pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index);
+}
+
+/**
+ * cmd_engine_setup() - setup dsi host controller for command mode
+ * @ctrl:          Pointer to the controller host hardware.
+ * @common_cfg:    Common configuration parameters.
+ * @cfg:           Command mode configuration.
+ *
+ * Setup DSI CMD engine with a specific configuration. Controller and
+ * command engine are not enabled as part of this function.
+ */
+void dsi_ctrl_hw_14_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
+				     struct dsi_host_common_cfg *common_cfg,
+				     struct dsi_cmd_engine_cfg *cfg)
+{
+	u32 reg = 0;
+
+	reg = (cfg->max_cmd_packets_interleave & 0xF) << 20;
+	reg |= (common_cfg->bit_swap_red ? BIT(4) : 0);
+	reg |= (common_cfg->bit_swap_green ? BIT(8) : 0);
+	reg |= (common_cfg->bit_swap_blue ? BIT(12) : 0);
+	reg |= cmd_mode_format_map[common_cfg->dst_format];
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL, reg);
+
+	reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2);
+	reg |= BIT(16);
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg);
+
+	reg = cfg->wr_mem_start & 0xFF;
+	reg |= (cfg->wr_mem_continue & 0xFF) << 8;
+	reg |= (cfg->insert_dcs_command ? BIT(16) : 0);
+	DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg);
+
+	pr_debug("[DSI_%d] Cmd engine setup done\n", ctrl->index);
+}
+
+/**
+ * video_engine_en() - enable DSI video engine
+ * @ctrl:          Pointer to controller host hardware.
+ * @on:            Enable/disabel video engine.
+ */
+void dsi_ctrl_hw_14_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
+{
+	u32 reg = 0;
+
+	/* Set/Clear VIDEO_MODE_EN bit */
+	reg = DSI_R32(ctrl, DSI_CTRL);
+	if (on)
+		reg |= BIT(1);
+	else
+		reg &= ~BIT(1);
+
+	DSI_W32(ctrl, DSI_CTRL, reg);
+
+	pr_debug("[DSI_%d] Video engine = %d\n", ctrl->index, on);
+}
+
+/**
+ * ctrl_en() - enable DSI controller engine
+ * @ctrl:          Pointer to the controller host hardware.
+ * @on:            turn on/off the DSI controller engine.
+ */
+void dsi_ctrl_hw_14_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on)
+{
+	u32 reg = 0;
+
+	/* Set/Clear DSI_EN bit */
+	reg = DSI_R32(ctrl, DSI_CTRL);
+	if (on)
+		reg |= BIT(0);
+	else
+		reg &= ~BIT(0);
+
+	DSI_W32(ctrl, DSI_CTRL, reg);
+
+	pr_debug("[DSI_%d] Controller engine = %d\n", ctrl->index, on);
+}
+
+/**
+ * cmd_engine_en() - enable DSI controller command engine
+ * @ctrl:          Pointer to the controller host hardware.
+ * @on:            Turn on/off the DSI command engine.
+ */
+void dsi_ctrl_hw_14_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
+{
+	u32 reg = 0;
+
+	/* Set/Clear CMD_MODE_EN bit */
+	reg = DSI_R32(ctrl, DSI_CTRL);
+	if (on)
+		reg |= BIT(2);
+	else
+		reg &= ~BIT(2);
+
+	DSI_W32(ctrl, DSI_CTRL, reg);
+
+	pr_debug("[DSI_%d] command engine = %d\n", ctrl->index, on);
+}
+
+/**
+ * setup_lane_map() - setup mapping between logical and physical lanes
+ * @ctrl:          Pointer to the controller host hardware.
+ * @lane_map:      Structure defining the mapping between DSI logical
+ *                 lanes and physical lanes.
+ */
+void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
+			       struct dsi_lane_mapping *lane_map)
+{
+	u32 reg_value = 0;
+	u32 lane_number = ((lane_map->physical_lane0 * 1000)+
+			   (lane_map->physical_lane1 * 100) +
+			   (lane_map->physical_lane2 * 10) +
+			   (lane_map->physical_lane3));
+
+	if (lane_number == 123)
+		reg_value = 0;
+	else if (lane_number == 3012)
+		reg_value = 1;
+	else if (lane_number == 2301)
+		reg_value = 2;
+	else if (lane_number == 1230)
+		reg_value = 3;
+	else if (lane_number == 321)
+		reg_value = 4;
+	else if (lane_number == 1032)
+		reg_value = 5;
+	else if (lane_number == 2103)
+		reg_value = 6;
+	else if (lane_number == 3210)
+		reg_value = 7;
+
+	DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, reg_value);
+
+	pr_debug("[DSI_%d] Lane swap setup complete\n", ctrl->index);
+}
+
+/**
+ * kickoff_command() - transmits commands stored in memory
+ * @ctrl:          Pointer to the controller host hardware.
+ * @cmd:           Command information.
+ * @flags:         Modifiers for command transmission.
+ *
+ * The controller hardware is programmed with address and size of the
+ * command buffer. The transmission is kicked off if
+ * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
+ * set, caller should make a separate call to trigger_command_dma() to
+ * transmit the command.
+ */
+void dsi_ctrl_hw_14_kickoff_command(struct dsi_ctrl_hw *ctrl,
+				    struct dsi_ctrl_cmd_dma_info *cmd,
+				    u32 flags)
+{
+	u32 reg = 0;
+
+	/*Set BROADCAST_EN and EMBEDDED_MODE */
+	reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
+	if (cmd->en_broadcast)
+		reg |= BIT(31);
+	else
+		reg &= ~BIT(31);
+
+	if (cmd->is_master)
+		reg |= BIT(30);
+	else
+		reg &= ~BIT(30);
+
+	if (cmd->use_lpm)
+		reg |= BIT(26);
+	else
+		reg &= ~BIT(26);
+
+	reg |= BIT(28);
+	DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
+
+	DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
+	DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF));
+
+	/* wait for writes to complete before kick off */
+	wmb();
+
+	if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
+		DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
+}
+
+/**
+ * kickoff_fifo_command() - transmits a command using FIFO in dsi
+ *                          hardware.
+ * @ctrl:          Pointer to the controller host hardware.
+ * @cmd:           Command information.
+ * @flags:         Modifiers for command transmission.
+ *
+ * The controller hardware FIFO is programmed with command header and
+ * payload. The transmission is kicked off if
+ * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
+ * set, caller should make a separate call to trigger_command_dma() to
+ * transmit the command.
+ */
+void dsi_ctrl_hw_14_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
+					 struct dsi_ctrl_cmd_dma_fifo_info *cmd,
+					 u32 flags)
+{
+	u32 reg = 0, i = 0;
+	u32 *ptr = cmd->command;
+	/*
+	 * Set CMD_DMA_TPG_EN, TPG_DMA_FIFO_MODE and
+	 * CMD_DMA_PATTERN_SEL = custom pattern stored in TPG DMA FIFO
+	 */
+	reg = (BIT(1) | BIT(2) | (0x3 << 16));
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
+
+	/*
+	 * Program the FIFO with command buffer. Hardware requires an extra
+	 * DWORD (set to zero) if the length of command buffer is odd DWORDS.
+	 */
+	for (i = 0; i < cmd->size; i += 4) {
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, *ptr);
+		ptr++;
+	}
+
+	if ((cmd->size / 4) & 0x1)
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, 0);
+
+	/*Set BROADCAST_EN and EMBEDDED_MODE */
+	reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
+	if (cmd->en_broadcast)
+		reg |= BIT(31);
+	else
+		reg &= ~BIT(31);
+
+	if (cmd->is_master)
+		reg |= BIT(30);
+	else
+		reg &= ~BIT(30);
+
+	if (cmd->use_lpm)
+		reg |= BIT(26);
+	else
+		reg &= ~BIT(26);
+
+	reg |= BIT(28);
+
+	DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
+
+	DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->size & 0xFFFFFFFF));
+	/* Finish writes before command trigger */
+	wmb();
+
+	if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
+		DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
+
+	pr_debug("[DSI_%d]size=%d, trigger = %d\n",
+		 ctrl->index, cmd->size,
+		 (flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER) ? false : true);
+}
+
+void dsi_ctrl_hw_14_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl)
+{
+	/* disable cmd dma tpg */
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, 0x0);
+
+	DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x1);
+	udelay(1);
+	DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x0);
+}
+
+/**
+ * trigger_command_dma() - trigger transmission of command buffer.
+ * @ctrl:          Pointer to the controller host hardware.
+ *
+ * This trigger can be only used if there was a prior call to
+ * kickoff_command() of kickoff_fifo_command() with
+ * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag.
+ */
+void dsi_ctrl_hw_14_trigger_command_dma(struct dsi_ctrl_hw *ctrl)
+{
+	DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
+	pr_debug("[DSI_%d] CMD DMA triggered\n", ctrl->index);
+}
+
+/**
+ * get_cmd_read_data() - get data read from the peripheral
+ * @ctrl:           Pointer to the controller host hardware.
+ * @rd_buf:         Buffer where data will be read into.
+ * @total_read_len: Number of bytes to read.
+ *
+ * return: number of bytes read.
+ */
+u32 dsi_ctrl_hw_14_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
+				     u8 *rd_buf,
+				     u32 read_offset,
+				     u32 total_read_len)
+{
+	u32 *lp, *temp, data;
+	int i, j = 0, cnt;
+	u32 read_cnt;
+	u32 rx_byte = 0;
+	u32 repeated_bytes = 0;
+	u8 reg[16];
+	u32 pkt_size = 0;
+	int buf_offset = read_offset;
+
+	lp = (u32 *)rd_buf;
+	temp = (u32 *)reg;
+	cnt = (rx_byte + 3) >> 2;
+
+	if (cnt > 4)
+		cnt = 4;
+
+	if (rx_byte == 4)
+		read_cnt = 4;
+	else
+		read_cnt = pkt_size + 6;
+
+	if (read_cnt > 16) {
+		int bytes_shifted;
+
+		bytes_shifted = read_cnt - 16;
+		repeated_bytes = buf_offset - bytes_shifted;
+	}
+
+	for (i = cnt - 1; i >= 0; i--) {
+		data = DSI_R32(ctrl, DSI_RDBK_DATA0 + i*4);
+		*temp++ = ntohl(data);
+	}
+
+	for (i = repeated_bytes; i < 16; i++)
+		rd_buf[j++] = reg[i];
+
+	pr_debug("[DSI_%d] Read %d bytes\n", ctrl->index, j);
+	return j;
+}
+/**
+ * ulps_request() - request ulps entry for specified lanes
+ * @ctrl:          Pointer to the controller host hardware.
+ * @lanes:         ORed list of lanes (enum dsi_data_lanes) which need
+ *                 to enter ULPS.
+ *
+ * Caller should check if lanes are in ULPS mode by calling
+ * get_lanes_in_ulps() operation.
+ */
+void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
+{
+	u32 reg = 0;
+
+	if (lanes & DSI_CLOCK_LANE)
+		reg = BIT(4);
+	if (lanes & DSI_DATA_LANE_0)
+		reg |= BIT(0);
+	if (lanes & DSI_DATA_LANE_1)
+		reg |= BIT(1);
+	if (lanes & DSI_DATA_LANE_2)
+		reg |= BIT(2);
+	if (lanes & DSI_DATA_LANE_3)
+		reg |= BIT(3);
+
+	DSI_W32(ctrl, DSI_LANE_CTRL, reg);
+
+	pr_debug("[DSI_%d] ULPS requested for lanes 0x%x\n", ctrl->index,
+		 lanes);
+}
+
+/**
+ * ulps_exit() - exit ULPS on specified lanes
+ * @ctrl:          Pointer to the controller host hardware.
+ * @lanes:         ORed list of lanes (enum dsi_data_lanes) which need
+ *                 to exit ULPS.
+ *
+ * Caller should check if lanes are in active mode by calling
+ * get_lanes_in_ulps() operation.
+ */
+void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
+{
+	u32 reg = 0;
+
+	reg = DSI_R32(ctrl, DSI_LANE_CTRL);
+	if (lanes & DSI_CLOCK_LANE)
+		reg |= BIT(12);
+	if (lanes & DSI_DATA_LANE_0)
+		reg |= BIT(8);
+	if (lanes & DSI_DATA_LANE_1)
+		reg |= BIT(9);
+	if (lanes & DSI_DATA_LANE_2)
+		reg |= BIT(10);
+	if (lanes & DSI_DATA_LANE_3)
+		reg |= BIT(11);
+
+	DSI_W32(ctrl, DSI_LANE_CTRL, reg);
+
+	pr_debug("[DSI_%d] ULPS exit request for lanes=0x%x\n",
+		 ctrl->index, lanes);
+}
+
+/**
+ * clear_ulps_request() - clear ulps request once all lanes are active
+ * @ctrl:          Pointer to controller host hardware.
+ * @lanes:         ORed list of lanes (enum dsi_data_lanes).
+ *
+ * ULPS request should be cleared after the lanes have exited ULPS.
+ */
+void dsi_ctrl_hw_14_clear_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
+{
+	u32 reg = 0;
+
+	reg = DSI_R32(ctrl, DSI_LANE_CTRL);
+	reg &= ~BIT(4); /* clock lane */
+	if (lanes & DSI_DATA_LANE_0)
+		reg &= ~BIT(0);
+	if (lanes & DSI_DATA_LANE_1)
+		reg &= ~BIT(1);
+	if (lanes & DSI_DATA_LANE_2)
+		reg &= ~BIT(2);
+	if (lanes & DSI_DATA_LANE_3)
+		reg &= ~BIT(3);
+
+	DSI_W32(ctrl, DSI_LANE_CTRL, reg);
+	/*
+	 * HPG recommends separate writes for clearing ULPS_REQUEST and
+	 * ULPS_EXIT.
+	 */
+	DSI_W32(ctrl, DSI_LANE_CTRL, 0x0);
+
+	pr_debug("[DSI_%d] ULPS request cleared\n", ctrl->index);
+}
+
+/**
+ * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
+ * @ctrl:          Pointer to the controller host hardware.
+ *
+ * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
+ * state. If 0 is returned, all the lanes are active.
+ *
+ * Return: List of lanes in ULPS state.
+ */
+u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
+{
+	u32 reg = 0;
+	u32 lanes = 0;
+
+	reg = DSI_R32(ctrl, DSI_LANE_STATUS);
+	if (!(reg & BIT(8)))
+		lanes |= DSI_DATA_LANE_0;
+	if (!(reg & BIT(9)))
+		lanes |= DSI_DATA_LANE_1;
+	if (!(reg & BIT(10)))
+		lanes |= DSI_DATA_LANE_2;
+	if (!(reg & BIT(11)))
+		lanes |= DSI_DATA_LANE_3;
+	if (!(reg & BIT(12)))
+		lanes |= DSI_CLOCK_LANE;
+
+	pr_debug("[DSI_%d] lanes in ulps = 0x%x\n", ctrl->index, lanes);
+	return lanes;
+}
+
+/**
+ * clamp_enable() - enable DSI clamps to keep PHY driving a stable link
+ * @ctrl:          Pointer to the controller host hardware.
+ * @lanes:         ORed list of lanes which need to be clamped.
+ * @enable_ulps:   TODO:??
+ */
+void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
+				 u32 lanes,
+				 bool enable_ulps)
+{
+	u32 clamp_reg = 0;
+	u32 bit_shift = 0;
+	u32 reg = 0;
+
+	if (ctrl->index == 1)
+		bit_shift = 16;
+
+	if (lanes & DSI_CLOCK_LANE) {
+		clamp_reg |= BIT(9);
+		if (enable_ulps)
+			clamp_reg |= BIT(8);
+	}
+
+	if (lanes & DSI_DATA_LANE_0) {
+		clamp_reg |= BIT(7);
+		if (enable_ulps)
+			clamp_reg |= BIT(6);
+	}
+
+	if (lanes & DSI_DATA_LANE_1) {
+		clamp_reg |= BIT(5);
+		if (enable_ulps)
+			clamp_reg |= BIT(4);
+	}
+
+	if (lanes & DSI_DATA_LANE_2) {
+		clamp_reg |= BIT(3);
+		if (enable_ulps)
+			clamp_reg |= BIT(2);
+	}
+
+	if (lanes & DSI_DATA_LANE_3) {
+		clamp_reg |= BIT(1);
+		if (enable_ulps)
+			clamp_reg |= BIT(0);
+	}
+
+	clamp_reg |= BIT(15); /* Enable clamp */
+
+	reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
+	reg |= (clamp_reg << bit_shift);
+	DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
+
+
+	reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
+	reg |= BIT(30);
+	DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
+
+	pr_debug("[DSI_%d] Clamps enabled for lanes=0x%x\n", ctrl->index,
+		 lanes);
+}
+
+/**
+ * clamp_disable() - disable DSI clamps
+ * @ctrl:          Pointer to the controller host hardware.
+ * @lanes:         ORed list of lanes which need to have clamps released.
+ * @disable_ulps:   TODO:??
+ */
+void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
+				  u32 lanes,
+				  bool disable_ulps)
+{
+	u32 clamp_reg = 0;
+	u32 bit_shift = 0;
+	u32 reg = 0;
+
+	if (ctrl->index == 1)
+		bit_shift = 16;
+
+	if (lanes & DSI_CLOCK_LANE) {
+		clamp_reg |= BIT(9);
+		if (disable_ulps)
+			clamp_reg |= BIT(8);
+	}
+
+	if (lanes & DSI_DATA_LANE_0) {
+		clamp_reg |= BIT(7);
+		if (disable_ulps)
+			clamp_reg |= BIT(6);
+	}
+
+	if (lanes & DSI_DATA_LANE_1) {
+		clamp_reg |= BIT(5);
+		if (disable_ulps)
+			clamp_reg |= BIT(4);
+	}
+
+	if (lanes & DSI_DATA_LANE_2) {
+		clamp_reg |= BIT(3);
+		if (disable_ulps)
+			clamp_reg |= BIT(2);
+	}
+
+	if (lanes & DSI_DATA_LANE_3) {
+		clamp_reg |= BIT(1);
+		if (disable_ulps)
+			clamp_reg |= BIT(0);
+	}
+
+	clamp_reg |= BIT(15); /* Enable clamp */
+	clamp_reg <<= bit_shift;
+
+	/* Disable PHY reset skip */
+	reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
+	reg &= ~BIT(30);
+	DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
+
+	reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
+	reg &= ~(clamp_reg);
+	DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
+
+	pr_debug("[DSI_%d] Disable clamps for lanes=%d\n", ctrl->index, lanes);
+}
+
+/**
+ * get_interrupt_status() - returns the interrupt status
+ * @ctrl:          Pointer to the controller host hardware.
+ *
+ * Returns the ORed list of interrupts(enum dsi_status_int_type) that
+ * are active. This list does not include any error interrupts. Caller
+ * should call get_error_status for error interrupts.
+ *
+ * Return: List of active interrupts.
+ */
+u32 dsi_ctrl_hw_14_get_interrupt_status(struct dsi_ctrl_hw *ctrl)
+{
+	u32 reg = 0;
+	u32 ints = 0;
+
+	reg = DSI_R32(ctrl, DSI_INT_CTRL);
+
+	if (reg & BIT(0))
+		ints |= DSI_CMD_MODE_DMA_DONE;
+	if (reg & BIT(8))
+		ints |= DSI_CMD_FRAME_DONE;
+	if (reg & BIT(10))
+		ints |= DSI_CMD_STREAM0_FRAME_DONE;
+	if (reg & BIT(12))
+		ints |= DSI_CMD_STREAM1_FRAME_DONE;
+	if (reg & BIT(14))
+		ints |= DSI_CMD_STREAM2_FRAME_DONE;
+	if (reg & BIT(16))
+		ints |= DSI_VIDEO_MODE_FRAME_DONE;
+	if (reg & BIT(20))
+		ints |= DSI_BTA_DONE;
+	if (reg & BIT(28))
+		ints |= DSI_DYN_REFRESH_DONE;
+	if (reg & BIT(30))
+		ints |= DSI_DESKEW_DONE;
+
+	pr_debug("[DSI_%d] Interrupt status = 0x%x, INT_CTRL=0x%x\n",
+		 ctrl->index, ints, reg);
+	return ints;
+}
+
+/**
+ * clear_interrupt_status() - clears the specified interrupts
+ * @ctrl:          Pointer to the controller host hardware.
+ * @ints:          List of interrupts to be cleared.
+ */
+void dsi_ctrl_hw_14_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints)
+{
+	u32 reg = 0;
+
+	if (ints & DSI_CMD_MODE_DMA_DONE)
+		reg |= BIT(0);
+	if (ints & DSI_CMD_FRAME_DONE)
+		reg |= BIT(8);
+	if (ints & DSI_CMD_STREAM0_FRAME_DONE)
+		reg |= BIT(10);
+	if (ints & DSI_CMD_STREAM1_FRAME_DONE)
+		reg |= BIT(12);
+	if (ints & DSI_CMD_STREAM2_FRAME_DONE)
+		reg |= BIT(14);
+	if (ints & DSI_VIDEO_MODE_FRAME_DONE)
+		reg |= BIT(16);
+	if (ints & DSI_BTA_DONE)
+		reg |= BIT(20);
+	if (ints & DSI_DYN_REFRESH_DONE)
+		reg |= BIT(28);
+	if (ints & DSI_DESKEW_DONE)
+		reg |= BIT(30);
+
+	DSI_W32(ctrl, DSI_INT_CTRL, reg);
+
+	pr_debug("[DSI_%d] Clear interrupts, ints = 0x%x, INT_CTRL=0x%x\n",
+		 ctrl->index, ints, reg);
+}
+
+/**
+ * enable_status_interrupts() - enable the specified interrupts
+ * @ctrl:          Pointer to the controller host hardware.
+ * @ints:          List of interrupts to be enabled.
+ *
+ * Enables the specified interrupts. This list will override the
+ * previous interrupts enabled through this function. Caller has to
+ * maintain the state of the interrupts enabled. To disable all
+ * interrupts, set ints to 0.
+ */
+void dsi_ctrl_hw_14_enable_status_interrupts(struct dsi_ctrl_hw *ctrl, u32 ints)
+{
+	u32 reg = 0;
+
+	/* Do not change value of DSI_ERROR_MASK bit */
+	reg |= (DSI_R32(ctrl, DSI_INT_CTRL) & BIT(25));
+	if (ints & DSI_CMD_MODE_DMA_DONE)
+		reg |= BIT(1);
+	if (ints & DSI_CMD_FRAME_DONE)
+		reg |= BIT(9);
+	if (ints & DSI_CMD_STREAM0_FRAME_DONE)
+		reg |= BIT(11);
+	if (ints & DSI_CMD_STREAM1_FRAME_DONE)
+		reg |= BIT(13);
+	if (ints & DSI_CMD_STREAM2_FRAME_DONE)
+		reg |= BIT(15);
+	if (ints & DSI_VIDEO_MODE_FRAME_DONE)
+		reg |= BIT(17);
+	if (ints & DSI_BTA_DONE)
+		reg |= BIT(21);
+	if (ints & DSI_DYN_REFRESH_DONE)
+		reg |= BIT(29);
+	if (ints & DSI_DESKEW_DONE)
+		reg |= BIT(31);
+
+	DSI_W32(ctrl, DSI_INT_CTRL, reg);
+
+	pr_debug("[DSI_%d] Enable interrupts 0x%x, INT_CTRL=0x%x\n",
+		 ctrl->index, ints, reg);
+}
+
+/**
+ * get_error_status() - returns the error status
+ * @ctrl:          Pointer to the controller host hardware.
+ *
+ * Returns the ORed list of errors(enum dsi_error_int_type) that are
+ * active. This list does not include any status interrupts. Caller
+ * should call get_interrupt_status for status interrupts.
+ *
+ * Return: List of active error interrupts.
+ */
+u64 dsi_ctrl_hw_14_get_error_status(struct dsi_ctrl_hw *ctrl)
+{
+	u32 dln0_phy_err;
+	u32 fifo_status;
+	u32 ack_error;
+	u32 timeout_errors;
+	u32 clk_error;
+	u32 dsi_status;
+	u64 errors = 0;
+
+	dln0_phy_err = DSI_R32(ctrl, DSI_DLN0_PHY_ERR);
+	if (dln0_phy_err & BIT(0))
+		errors |= DSI_DLN0_ESC_ENTRY_ERR;
+	if (dln0_phy_err & BIT(4))
+		errors |= DSI_DLN0_ESC_SYNC_ERR;
+	if (dln0_phy_err & BIT(8))
+		errors |= DSI_DLN0_LP_CONTROL_ERR;
+	if (dln0_phy_err & BIT(12))
+		errors |= DSI_DLN0_LP0_CONTENTION;
+	if (dln0_phy_err & BIT(16))
+		errors |= DSI_DLN0_LP1_CONTENTION;
+
+	fifo_status = DSI_R32(ctrl, DSI_FIFO_STATUS);
+	if (fifo_status & BIT(7))
+		errors |= DSI_CMD_MDP_FIFO_UNDERFLOW;
+	if (fifo_status & BIT(10))
+		errors |= DSI_CMD_DMA_FIFO_UNDERFLOW;
+	if (fifo_status & BIT(18))
+		errors |= DSI_DLN0_HS_FIFO_OVERFLOW;
+	if (fifo_status & BIT(19))
+		errors |= DSI_DLN0_HS_FIFO_UNDERFLOW;
+	if (fifo_status & BIT(22))
+		errors |= DSI_DLN1_HS_FIFO_OVERFLOW;
+	if (fifo_status & BIT(23))
+		errors |= DSI_DLN1_HS_FIFO_UNDERFLOW;
+	if (fifo_status & BIT(26))
+		errors |= DSI_DLN2_HS_FIFO_OVERFLOW;
+	if (fifo_status & BIT(27))
+		errors |= DSI_DLN2_HS_FIFO_UNDERFLOW;
+	if (fifo_status & BIT(30))
+		errors |= DSI_DLN3_HS_FIFO_OVERFLOW;
+	if (fifo_status & BIT(31))
+		errors |= DSI_DLN3_HS_FIFO_UNDERFLOW;
+
+	ack_error = DSI_R32(ctrl, DSI_ACK_ERR_STATUS);
+	if (ack_error & BIT(16))
+		errors |= DSI_RDBK_SINGLE_ECC_ERR;
+	if (ack_error & BIT(17))
+		errors |= DSI_RDBK_MULTI_ECC_ERR;
+	if (ack_error & BIT(20))
+		errors |= DSI_RDBK_CRC_ERR;
+	if (ack_error & BIT(23))
+		errors |= DSI_RDBK_INCOMPLETE_PKT;
+	if (ack_error & BIT(24))
+		errors |= DSI_PERIPH_ERROR_PKT;
+
+	timeout_errors = DSI_R32(ctrl, DSI_TIMEOUT_STATUS);
+	if (timeout_errors & BIT(0))
+		errors |= DSI_HS_TX_TIMEOUT;
+	if (timeout_errors & BIT(4))
+		errors |= DSI_LP_RX_TIMEOUT;
+	if (timeout_errors & BIT(8))
+		errors |= DSI_BTA_TIMEOUT;
+
+	clk_error = DSI_R32(ctrl, DSI_CLK_STATUS);
+	if (clk_error & BIT(16))
+		errors |= DSI_PLL_UNLOCK;
+
+	dsi_status = DSI_R32(ctrl, DSI_STATUS);
+	if (dsi_status & BIT(31))
+		errors |= DSI_INTERLEAVE_OP_CONTENTION;
+
+	pr_debug("[DSI_%d] Error status = 0x%llx, phy=0x%x, fifo=0x%x",
+		 ctrl->index, errors, dln0_phy_err, fifo_status);
+	pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
+		 ctrl->index, ack_error, timeout_errors, clk_error, dsi_status);
+	return errors;
+}
+
+/**
+ * clear_error_status() - clears the specified errors
+ * @ctrl:          Pointer to the controller host hardware.
+ * @errors:          List of errors to be cleared.
+ */
+void dsi_ctrl_hw_14_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors)
+{
+	u32 dln0_phy_err = 0;
+	u32 fifo_status = 0;
+	u32 ack_error = 0;
+	u32 timeout_error = 0;
+	u32 clk_error = 0;
+	u32 dsi_status = 0;
+	u32 int_ctrl = 0;
+
+	if (errors & DSI_RDBK_SINGLE_ECC_ERR)
+		ack_error |= BIT(16);
+	if (errors & DSI_RDBK_MULTI_ECC_ERR)
+		ack_error |= BIT(17);
+	if (errors & DSI_RDBK_CRC_ERR)
+		ack_error |= BIT(20);
+	if (errors & DSI_RDBK_INCOMPLETE_PKT)
+		ack_error |= BIT(23);
+	if (errors & DSI_PERIPH_ERROR_PKT)
+		ack_error |= BIT(24);
+
+	if (errors & DSI_LP_RX_TIMEOUT)
+		timeout_error |= BIT(4);
+	if (errors & DSI_HS_TX_TIMEOUT)
+		timeout_error |= BIT(0);
+	if (errors & DSI_BTA_TIMEOUT)
+		timeout_error |= BIT(8);
+
+	if (errors & DSI_PLL_UNLOCK)
+		clk_error |= BIT(16);
+
+	if (errors & DSI_DLN0_LP0_CONTENTION)
+		dln0_phy_err |= BIT(12);
+	if (errors & DSI_DLN0_LP1_CONTENTION)
+		dln0_phy_err |= BIT(16);
+	if (errors & DSI_DLN0_ESC_ENTRY_ERR)
+		dln0_phy_err |= BIT(0);
+	if (errors & DSI_DLN0_ESC_SYNC_ERR)
+		dln0_phy_err |= BIT(4);
+	if (errors & DSI_DLN0_LP_CONTROL_ERR)
+		dln0_phy_err |= BIT(8);
+
+	if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW)
+		fifo_status |= BIT(10);
+	if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW)
+		fifo_status |= BIT(7);
+	if (errors & DSI_DLN0_HS_FIFO_OVERFLOW)
+		fifo_status |= BIT(18);
+	if (errors & DSI_DLN1_HS_FIFO_OVERFLOW)
+		fifo_status |= BIT(22);
+	if (errors & DSI_DLN2_HS_FIFO_OVERFLOW)
+		fifo_status |= BIT(26);
+	if (errors & DSI_DLN3_HS_FIFO_OVERFLOW)
+		fifo_status |= BIT(30);
+	if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW)
+		fifo_status |= BIT(19);
+	if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW)
+		fifo_status |= BIT(23);
+	if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW)
+		fifo_status |= BIT(27);
+	if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW)
+		fifo_status |= BIT(31);
+
+	if (errors & DSI_INTERLEAVE_OP_CONTENTION)
+		dsi_status |= BIT(31);
+
+	DSI_W32(ctrl, DSI_DLN0_PHY_ERR, dln0_phy_err);
+	DSI_W32(ctrl, DSI_FIFO_STATUS, fifo_status);
+	DSI_W32(ctrl, DSI_ACK_ERR_STATUS, ack_error);
+	DSI_W32(ctrl, DSI_TIMEOUT_STATUS, timeout_error);
+	DSI_W32(ctrl, DSI_CLK_STATUS, clk_error);
+	DSI_W32(ctrl, DSI_STATUS, dsi_status);
+
+	int_ctrl = DSI_R32(ctrl, DSI_INT_CTRL);
+	int_ctrl |= BIT(24);
+	DSI_W32(ctrl, DSI_INT_CTRL, int_ctrl);
+	pr_debug("[DSI_%d] clear errors = 0x%llx, phy=0x%x, fifo=0x%x",
+		 ctrl->index, errors, dln0_phy_err, fifo_status);
+	pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
+		 ctrl->index, ack_error, timeout_error, clk_error, dsi_status);
+}
+
+/**
+ * enable_error_interrupts() - enable the specified interrupts
+ * @ctrl:          Pointer to the controller host hardware.
+ * @errors:        List of errors to be enabled.
+ *
+ * Enables the specified interrupts. This list will override the
+ * previous interrupts enabled through this function. Caller has to
+ * maintain the state of the interrupts enabled. To disable all
+ * interrupts, set errors to 0.
+ */
+void dsi_ctrl_hw_14_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
+					    u64 errors)
+{
+	u32 int_ctrl = 0;
+	u32 int_mask0 = 0x7FFF3BFF;
+
+	int_ctrl = DSI_R32(ctrl, DSI_INT_CTRL);
+	if (errors)
+		int_ctrl |= BIT(25);
+	else
+		int_ctrl &= ~BIT(25);
+
+	if (errors & DSI_RDBK_SINGLE_ECC_ERR)
+		int_mask0 &= ~BIT(0);
+	if (errors & DSI_RDBK_MULTI_ECC_ERR)
+		int_mask0 &= ~BIT(1);
+	if (errors & DSI_RDBK_CRC_ERR)
+		int_mask0 &= ~BIT(2);
+	if (errors & DSI_RDBK_INCOMPLETE_PKT)
+		int_mask0 &= ~BIT(3);
+	if (errors & DSI_PERIPH_ERROR_PKT)
+		int_mask0 &= ~BIT(4);
+
+	if (errors & DSI_LP_RX_TIMEOUT)
+		int_mask0 &= ~BIT(5);
+	if (errors & DSI_HS_TX_TIMEOUT)
+		int_mask0 &= ~BIT(6);
+	if (errors & DSI_BTA_TIMEOUT)
+		int_mask0 &= ~BIT(7);
+
+	if (errors & DSI_PLL_UNLOCK)
+		int_mask0 &= ~BIT(28);
+
+	if (errors & DSI_DLN0_LP0_CONTENTION)
+		int_mask0 &= ~BIT(24);
+	if (errors & DSI_DLN0_LP1_CONTENTION)
+		int_mask0 &= ~BIT(25);
+	if (errors & DSI_DLN0_ESC_ENTRY_ERR)
+		int_mask0 &= ~BIT(21);
+	if (errors & DSI_DLN0_ESC_SYNC_ERR)
+		int_mask0 &= ~BIT(22);
+	if (errors & DSI_DLN0_LP_CONTROL_ERR)
+		int_mask0 &= ~BIT(23);
+
+	if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(9);
+	if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(11);
+	if (errors & DSI_DLN0_HS_FIFO_OVERFLOW)
+		int_mask0 &= ~BIT(16);
+	if (errors & DSI_DLN1_HS_FIFO_OVERFLOW)
+		int_mask0 &= ~BIT(17);
+	if (errors & DSI_DLN2_HS_FIFO_OVERFLOW)
+		int_mask0 &= ~BIT(18);
+	if (errors & DSI_DLN3_HS_FIFO_OVERFLOW)
+		int_mask0 &= ~BIT(19);
+	if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(26);
+	if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(27);
+	if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(29);
+	if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW)
+		int_mask0 &= ~BIT(30);
+
+	if (errors & DSI_INTERLEAVE_OP_CONTENTION)
+		int_mask0 &= ~BIT(8);
+
+	DSI_W32(ctrl, DSI_INT_CTRL, int_ctrl);
+	DSI_W32(ctrl, DSI_ERR_INT_MASK0, int_mask0);
+
+	pr_debug("[DSI_%d] enable errors = 0x%llx, int_mask0=0x%x\n",
+		 ctrl->index, errors, int_mask0);
+}
+
+/**
+ * video_test_pattern_setup() - setup test pattern engine for video mode
+ * @ctrl:          Pointer to the controller host hardware.
+ * @type:          Type of test pattern.
+ * @init_val:      Initial value to use for generating test pattern.
+ */
+void dsi_ctrl_hw_14_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
+					     enum dsi_test_pattern type,
+					     u32 init_val)
+{
+	u32 reg = 0;
+
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, init_val);
+
+	switch (type) {
+	case DSI_TEST_PATTERN_FIXED:
+		reg |= (0x2 << 4);
+		break;
+	case DSI_TEST_PATTERN_INC:
+		reg |= (0x1 << 4);
+		break;
+	case DSI_TEST_PATTERN_POLY:
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_POLY, 0xF0F0F);
+		break;
+	default:
+		break;
+	}
+
+	DSI_W32(ctrl, DSI_TPG_MAIN_CONTROL, 0x100);
+	DSI_W32(ctrl, DSI_TPG_VIDEO_CONFIG, 0x5);
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
+
+	pr_debug("[DSI_%d] Video test pattern setup done\n", ctrl->index);
+}
+
+/**
+ * cmd_test_pattern_setup() - setup test patttern engine for cmd mode
+ * @ctrl:          Pointer to the controller host hardware.
+ * @type:          Type of test pattern.
+ * @init_val:      Initial value to use for generating test pattern.
+ * @stream_id:     Stream Id on which packets are generated.
+ */
+void dsi_ctrl_hw_14_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
+					   enum dsi_test_pattern type,
+					   u32 init_val,
+					   u32 stream_id)
+{
+	u32 reg = 0;
+	u32 init_offset;
+	u32 poly_offset;
+	u32 pattern_sel_shift;
+
+	switch (stream_id) {
+	case 0:
+		init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0;
+		poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM0_POLY;
+		pattern_sel_shift = 8;
+		break;
+	case 1:
+		init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL1;
+		poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM1_POLY;
+		pattern_sel_shift = 12;
+		break;
+	case 2:
+		init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL2;
+		poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY;
+		pattern_sel_shift = 20;
+		break;
+	default:
+		return;
+	}
+
+	DSI_W32(ctrl, init_offset, init_val);
+
+	switch (type) {
+	case DSI_TEST_PATTERN_FIXED:
+		reg |= (0x2 << pattern_sel_shift);
+		break;
+	case DSI_TEST_PATTERN_INC:
+		reg |= (0x1 << pattern_sel_shift);
+		break;
+	case DSI_TEST_PATTERN_POLY:
+		DSI_W32(ctrl, poly_offset, 0xF0F0F);
+		break;
+	default:
+		break;
+	}
+
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
+	pr_debug("[DSI_%d] Cmd test pattern setup done\n", ctrl->index);
+}
+
+/**
+ * test_pattern_enable() - enable test pattern engine
+ * @ctrl:          Pointer to the controller host hardware.
+ * @enable:        Enable/Disable test pattern engine.
+ */
+void dsi_ctrl_hw_14_test_pattern_enable(struct dsi_ctrl_hw *ctrl,
+					bool enable)
+{
+	u32 reg = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_CTRL);
+
+	if (enable)
+		reg |= BIT(0);
+	else
+		reg &= ~BIT(0);
+
+	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
+
+	pr_debug("[DSI_%d] Test pattern enable=%d\n", ctrl->index, enable);
+}
+
+/**
+ * trigger_cmd_test_pattern() - trigger a command mode frame update with
+ *                              test pattern
+ * @ctrl:          Pointer to the controller host hardware.
+ * @stream_id:     Stream on which frame update is sent.
+ */
+void dsi_ctrl_hw_14_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
+					     u32 stream_id)
+{
+	switch (stream_id) {
+	case 0:
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1);
+		break;
+	case 1:
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM1_TRIGGER, 0x1);
+		break;
+	case 2:
+		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM2_TRIGGER, 0x1);
+		break;
+	default:
+		break;
+	}
+
+	pr_debug("[DSI_%d] Cmd Test pattern trigger\n", ctrl->index);
+}
+
+#define DUMP_REG_VALUE(off) "\t%-30s: 0x%08x\n", #off, DSI_R32(ctrl, off)
+ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
+					  char *buf,
+					  u32 size)
+{
+	u32 len = 0;
+
+	len += snprintf((buf + len), (size - len), "CONFIGURATION REGS:\n");
+
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_HW_VERSION));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_FIFO_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_SYNC_DATATYPE));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_PIXEL_DATATYPE));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_BLANKING_DATATYPE));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_DATA_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_H));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_V));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_TOTAL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_HSYNC));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC_VPOS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_DMA_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DMA_CMD_OFFSET));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DMA_CMD_LENGTH));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DMA_FIFO_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DMA_NULL_PACKET_DATA));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_TOTAL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_TOTAL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_ACK_ERR_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATA0));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATA1));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATA2));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATA3));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATATYPE0));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATATYPE1));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TRIG_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_EXT_MUX));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_EXT_MUX_TE_PULSE_DETECT_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CMD_MODE_DMA_SW_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CMD_MODE_MDP_SW_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CMD_MODE_BTA_SW_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RESET_SW_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_LANE_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_LANE_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_LANE_SWAP_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DLN0_PHY_ERR));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_LP_TIMER_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_HS_TIMER_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TIMEOUT_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CLKOUT_TIMING_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_EOT_PACKET));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_EOT_PACKET_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_GENERIC_ESC_TX_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_ERR_INT_MASK0));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_INT_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_SOFT_RESET));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CLK_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_CLK_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_PHY_SW_RESET));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_AXI2AHB_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL2));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_TOTAL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VBIF_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_AES_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_RDBK_DATA_CTRL));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_STATUS));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_WRITE_TRIGGER));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DSI_TIMING_FLUSH));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_DSI_TIMING_DB_MODE));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_RESET));
+	len += snprintf((buf + len), (size - len),
+			DUMP_REG_VALUE(DSI_VERSION));
+
+	pr_err("LLENGTH = %d\n", len);
+	return len;
+}
+
+
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg_1_4.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg_1_4.h
new file mode 100644
index 0000000000000000000000000000000000000000..028ad46664a7b9d1f745a9280f00832d453e55ef
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg_1_4.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CTRL_REG_H_
+#define _DSI_CTRL_REG_H_
+
+#define DSI_HW_VERSION                             (0x0000)
+#define DSI_CTRL                                   (0x0004)
+#define DSI_STATUS                                 (0x0008)
+#define DSI_FIFO_STATUS                            (0x000C)
+#define DSI_VIDEO_MODE_CTRL                        (0x0010)
+#define DSI_VIDEO_MODE_SYNC_DATATYPE               (0x0014)
+#define DSI_VIDEO_MODE_PIXEL_DATATYPE              (0x0018)
+#define DSI_VIDEO_MODE_BLANKING_DATATYPE           (0x001C)
+#define DSI_VIDEO_MODE_DATA_CTRL                   (0x0020)
+#define DSI_VIDEO_MODE_ACTIVE_H                    (0x0024)
+#define DSI_VIDEO_MODE_ACTIVE_V                    (0x0028)
+#define DSI_VIDEO_MODE_TOTAL                       (0x002C)
+#define DSI_VIDEO_MODE_HSYNC                       (0x0030)
+#define DSI_VIDEO_MODE_VSYNC                       (0x0034)
+#define DSI_VIDEO_MODE_VSYNC_VPOS                  (0x0038)
+#define DSI_COMMAND_MODE_DMA_CTRL                  (0x003C)
+#define DSI_COMMAND_MODE_MDP_CTRL                  (0x0040)
+#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL          (0x0044)
+#define DSI_DMA_CMD_OFFSET                         (0x0048)
+#define DSI_DMA_CMD_LENGTH                         (0x004C)
+#define DSI_DMA_FIFO_CTRL                          (0x0050)
+#define DSI_DMA_NULL_PACKET_DATA                   (0x0054)
+#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL          (0x0058)
+#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL         (0x005C)
+#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL          (0x0060)
+#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL         (0x0064)
+#define DSI_ACK_ERR_STATUS                         (0x0068)
+#define DSI_RDBK_DATA0                             (0x006C)
+#define DSI_RDBK_DATA1                             (0x0070)
+#define DSI_RDBK_DATA2                             (0x0074)
+#define DSI_RDBK_DATA3                             (0x0078)
+#define DSI_RDBK_DATATYPE0                         (0x007C)
+#define DSI_RDBK_DATATYPE1                         (0x0080)
+#define DSI_TRIG_CTRL                              (0x0084)
+#define DSI_EXT_MUX                                (0x0088)
+#define DSI_EXT_MUX_TE_PULSE_DETECT_CTRL           (0x008C)
+#define DSI_CMD_MODE_DMA_SW_TRIGGER                (0x0090)
+#define DSI_CMD_MODE_MDP_SW_TRIGGER                (0x0094)
+#define DSI_CMD_MODE_BTA_SW_TRIGGER                (0x0098)
+#define DSI_RESET_SW_TRIGGER                       (0x009C)
+#define DSI_MISR_CMD_CTRL                          (0x00A0)
+#define DSI_MISR_VIDEO_CTRL                        (0x00A4)
+#define DSI_LANE_STATUS                            (0x00A8)
+#define DSI_LANE_CTRL                              (0x00AC)
+#define DSI_LANE_SWAP_CTRL                         (0x00B0)
+#define DSI_DLN0_PHY_ERR                           (0x00B4)
+#define DSI_LP_TIMER_CTRL                          (0x00B8)
+#define DSI_HS_TIMER_CTRL                          (0x00BC)
+#define DSI_TIMEOUT_STATUS                         (0x00C0)
+#define DSI_CLKOUT_TIMING_CTRL                     (0x00C4)
+#define DSI_EOT_PACKET                             (0x00C8)
+#define DSI_EOT_PACKET_CTRL                        (0x00CC)
+#define DSI_GENERIC_ESC_TX_TRIGGER                 (0x00D0)
+#define DSI_CAM_BIST_CTRL                          (0x00D4)
+#define DSI_CAM_BIST_FRAME_SIZE                    (0x00D8)
+#define DSI_CAM_BIST_BLOCK_SIZE                    (0x00DC)
+#define DSI_CAM_BIST_FRAME_CONFIG                  (0x00E0)
+#define DSI_CAM_BIST_LSFR_CTRL                     (0x00E4)
+#define DSI_CAM_BIST_LSFR_INIT                     (0x00E8)
+#define DSI_CAM_BIST_START                         (0x00EC)
+#define DSI_CAM_BIST_STATUS                        (0x00F0)
+#define DSI_ERR_INT_MASK0                          (0x010C)
+#define DSI_INT_CTRL                               (0x0110)
+#define DSI_IOBIST_CTRL                            (0x0114)
+#define DSI_SOFT_RESET                             (0x0118)
+#define DSI_CLK_CTRL                               (0x011C)
+#define DSI_CLK_STATUS                             (0x0120)
+#define DSI_PHY_SW_RESET                           (0x012C)
+#define DSI_AXI2AHB_CTRL                           (0x0130)
+#define DSI_MISR_CMD_MDP0_32BIT                    (0x0134)
+#define DSI_MISR_CMD_MDP1_32BIT                    (0x0138)
+#define DSI_MISR_CMD_DMA_32BIT                     (0x013C)
+#define DSI_MISR_VIDEO_32BIT                       (0x0140)
+#define DSI_LANE_MISR_CTRL                         (0x0144)
+#define DSI_LANE0_MISR                             (0x0148)
+#define DSI_LANE1_MISR                             (0x014C)
+#define DSI_LANE2_MISR                             (0x0150)
+#define DSI_LANE3_MISR                             (0x0154)
+#define DSI_TEST_PATTERN_GEN_CTRL                  (0x015C)
+#define DSI_TEST_PATTERN_GEN_VIDEO_POLY            (0x0160)
+#define DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL        (0x0164)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM0_POLY  (0x0168)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0     (0x016C)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM1_POLY  (0x0170)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL1     (0x0174)
+#define DSI_TEST_PATTERN_GEN_CMD_DMA_POLY          (0x0178)
+#define DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL      (0x017C)
+#define DSI_TEST_PATTERN_GEN_VIDEO_ENABLE          (0x0180)
+#define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER   (0x0184)
+#define DSI_TEST_PATTERN_GEN_CMD_STREAM1_TRIGGER   (0x0188)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL2     (0x018C)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY  (0x0190)
+#define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY  (0x0190)
+#define DSI_COMMAND_MODE_MDP_IDLE_CTRL             (0x0194)
+#define DSI_TEST_PATTERN_GEN_CMD_STREAM2_TRIGGER   (0x0198)
+#define DSI_TPG_MAIN_CONTROL                       (0x019C)
+#define DSI_TPG_MAIN_CONTROL2                      (0x01A0)
+#define DSI_TPG_VIDEO_CONFIG                       (0x01A4)
+#define DSI_TPG_COMPONENT_LIMITS                   (0x01A8)
+#define DSI_TPG_RECTANGLE                          (0x01AC)
+#define DSI_TPG_BLACK_WHITE_PATTERN_FRAMES         (0x01B0)
+#define DSI_TPG_RGB_MAPPING                        (0x01B4)
+#define DSI_COMMAND_MODE_MDP_CTRL2                 (0x01B8)
+#define DSI_COMMAND_MODE_MDP_STREAM2_CTRL          (0x01BC)
+#define DSI_COMMAND_MODE_MDP_STREAM2_TOTAL         (0x01C0)
+#define DSI_MISR_CMD_MDP2_8BIT                     (0x01C4)
+#define DSI_MISR_CMD_MDP2_32BIT                    (0x01C8)
+#define DSI_VBIF_CTRL                              (0x01CC)
+#define DSI_AES_CTRL                               (0x01D0)
+#define DSI_RDBK_DATA_CTRL                         (0x01D4)
+#define DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2     (0x01D8)
+#define DSI_TPG_DMA_FIFO_STATUS                    (0x01DC)
+#define DSI_TPG_DMA_FIFO_WRITE_TRIGGER             (0x01E0)
+#define DSI_DSI_TIMING_FLUSH                       (0x01E4)
+#define DSI_DSI_TIMING_DB_MODE                     (0x01E8)
+#define DSI_TPG_DMA_FIFO_RESET                     (0x01EC)
+#define DSI_SCRATCH_REGISTER_0                     (0x01F0)
+#define DSI_VERSION                                (0x01F4)
+#define DSI_SCRATCH_REGISTER_1                     (0x01F8)
+#define DSI_SCRATCH_REGISTER_2                     (0x01FC)
+#define DSI_DYNAMIC_REFRESH_CTRL                   (0x0200)
+#define DSI_DYNAMIC_REFRESH_PIPE_DELAY             (0x0204)
+#define DSI_DYNAMIC_REFRESH_PIPE_DELAY2            (0x0208)
+#define DSI_DYNAMIC_REFRESH_PLL_DELAY              (0x020C)
+#define DSI_DYNAMIC_REFRESH_STATUS                 (0x0210)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL0              (0x0214)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL1              (0x0218)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL2              (0x021C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL3              (0x0220)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL4              (0x0224)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL5              (0x0228)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL6              (0x022C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL7              (0x0230)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL8              (0x0234)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL9              (0x0238)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL10             (0x023C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL11             (0x0240)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL12             (0x0244)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL13             (0x0248)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL14             (0x024C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL15             (0x0250)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL16             (0x0254)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL17             (0x0258)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL18             (0x025C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL19             (0x0260)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL20             (0x0264)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL21             (0x0268)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL22             (0x026C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL23             (0x0270)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL24             (0x0274)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL25             (0x0278)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL26             (0x027C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL27             (0x0280)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL28             (0x0284)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL29             (0x0288)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL30             (0x028C)
+#define DSI_DYNAMIC_REFRESH_PLL_CTRL31             (0x0290)
+#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR         (0x0294)
+#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2        (0x0298)
+#define DSI_VIDEO_COMPRESSION_MODE_CTRL            (0x02A0)
+#define DSI_VIDEO_COMPRESSION_MODE_CTRL2           (0x02A4)
+#define DSI_COMMAND_COMPRESSION_MODE_CTRL          (0x02A8)
+#define DSI_COMMAND_COMPRESSION_MODE_CTRL2         (0x02AC)
+#define DSI_COMMAND_COMPRESSION_MODE_CTRL3         (0x02B0)
+#define DSI_COMMAND_MODE_NULL_INSERTION_CTRL       (0x02B4)
+#define DSI_READ_BACK_DISABLE_STATUS               (0x02B8)
+#define DSI_DESKEW_CTRL                            (0x02BC)
+#define DSI_DESKEW_DELAY_CTRL                      (0x02C0)
+#define DSI_DESKEW_SW_TRIGGER                      (0x02C4)
+#define DSI_SECURE_DISPLAY_STATUS                  (0x02CC)
+#define DSI_SECURE_DISPLAY_BLOCK_COMMAND_COLOR     (0x02D0)
+#define DSI_SECURE_DISPLAY_BLOCK_VIDEO_COLOR       (0x02D4)
+
+
+#endif /* _DSI_CTRL_REG_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
new file mode 100644
index 0000000000000000000000000000000000000000..2caa32ea8f0c15d8c80a3232d6a0b80f6be6d35a
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_DEFS_H_
+#define _DSI_DEFS_H_
+
+#include <linux/types.h>
+
+#define DSI_H_TOTAL(t) (((t)->h_active) + ((t)->h_back_porch) + \
+			((t)->h_sync_width) + ((t)->h_front_porch))
+
+#define DSI_V_TOTAL(t) (((t)->v_active) + ((t)->v_back_porch) + \
+			((t)->v_sync_width) + ((t)->v_front_porch))
+
+/**
+ * enum dsi_pixel_format - DSI pixel formats
+ * @DSI_PIXEL_FORMAT_RGB565:
+ * @DSI_PIXEL_FORMAT_RGB666:
+ * @DSI_PIXEL_FORMAT_RGB666_LOOSE:
+ * @DSI_PIXEL_FORMAT_RGB888:
+ * @DSI_PIXEL_FORMAT_RGB111:
+ * @DSI_PIXEL_FORMAT_RGB332:
+ * @DSI_PIXEL_FORMAT_RGB444:
+ * @DSI_PIXEL_FORMAT_MAX:
+ */
+enum dsi_pixel_format {
+	DSI_PIXEL_FORMAT_RGB565 = 0,
+	DSI_PIXEL_FORMAT_RGB666,
+	DSI_PIXEL_FORMAT_RGB666_LOOSE,
+	DSI_PIXEL_FORMAT_RGB888,
+	DSI_PIXEL_FORMAT_RGB111,
+	DSI_PIXEL_FORMAT_RGB332,
+	DSI_PIXEL_FORMAT_RGB444,
+	DSI_PIXEL_FORMAT_MAX
+};
+
+/**
+ * enum dsi_op_mode - dsi operation mode
+ * @DSI_OP_VIDEO_MODE: DSI video mode operation
+ * @DSI_OP_CMD_MODE:   DSI Command mode operation
+ * @DSI_OP_MODE_MAX:
+ */
+enum dsi_op_mode {
+	DSI_OP_VIDEO_MODE = 0,
+	DSI_OP_CMD_MODE,
+	DSI_OP_MODE_MAX
+};
+
+/**
+ * enum dsi_mode_flags - flags to signal other drm components via private flags
+ * @DSI_MODE_FLAG_SEAMLESS:	Seamless transition requested by user
+ * @DSI_MODE_FLAG_DFPS:		Seamless transition is DynamicFPS
+ * @DSI_MODE_FLAG_VBLANK_PRE_MODESET:	Transition needs VBLANK before Modeset
+ */
+enum dsi_mode_flags {
+	DSI_MODE_FLAG_SEAMLESS			= BIT(0),
+	DSI_MODE_FLAG_DFPS			= BIT(1),
+	DSI_MODE_FLAG_VBLANK_PRE_MODESET	= BIT(2)
+};
+
+/**
+ * enum dsi_data_lanes - dsi physical lanes
+ * @DSI_DATA_LANE_0: Physical lane 0
+ * @DSI_DATA_LANE_1: Physical lane 1
+ * @DSI_DATA_LANE_2: Physical lane 2
+ * @DSI_DATA_LANE_3: Physical lane 3
+ * @DSI_CLOCK_LANE:  Physical clock lane
+ */
+enum dsi_data_lanes {
+	DSI_DATA_LANE_0 = BIT(0),
+	DSI_DATA_LANE_1 = BIT(1),
+	DSI_DATA_LANE_2 = BIT(2),
+	DSI_DATA_LANE_3 = BIT(3),
+	DSI_CLOCK_LANE  = BIT(4)
+};
+
+/**
+ * enum dsi_logical_lane - dsi logical lanes
+ * @DSI_LOGICAL_LANE_0:     Logical lane 0
+ * @DSI_LOGICAL_LANE_1:     Logical lane 1
+ * @DSI_LOGICAL_LANE_2:     Logical lane 2
+ * @DSI_LOGICAL_LANE_3:     Logical lane 3
+ * @DSI_LOGICAL_CLOCK_LANE: Clock lane
+ * @DSI_LANE_MAX:           Maximum lanes supported
+ */
+enum dsi_logical_lane {
+	DSI_LOGICAL_LANE_0 = 0,
+	DSI_LOGICAL_LANE_1,
+	DSI_LOGICAL_LANE_2,
+	DSI_LOGICAL_LANE_3,
+	DSI_LOGICAL_CLOCK_LANE,
+	DSI_LANE_MAX
+};
+
+/**
+ * enum dsi_trigger_type - dsi trigger type
+ * @DSI_TRIGGER_NONE:     No trigger.
+ * @DSI_TRIGGER_TE:       TE trigger.
+ * @DSI_TRIGGER_SEOF:     Start or End of frame.
+ * @DSI_TRIGGER_SW:       Software trigger.
+ * @DSI_TRIGGER_SW_SEOF:  Software trigger and start/end of frame.
+ * @DSI_TRIGGER_SW_TE:    Software and TE triggers.
+ * @DSI_TRIGGER_MAX:      Max trigger values.
+ */
+enum dsi_trigger_type {
+	DSI_TRIGGER_NONE = 0,
+	DSI_TRIGGER_TE,
+	DSI_TRIGGER_SEOF,
+	DSI_TRIGGER_SW,
+	DSI_TRIGGER_SW_SEOF,
+	DSI_TRIGGER_SW_TE,
+	DSI_TRIGGER_MAX
+};
+
+/**
+ * enum dsi_color_swap_mode - color swap mode
+ * @DSI_COLOR_SWAP_RGB:
+ * @DSI_COLOR_SWAP_RBG:
+ * @DSI_COLOR_SWAP_BGR:
+ * @DSI_COLOR_SWAP_BRG:
+ * @DSI_COLOR_SWAP_GRB:
+ * @DSI_COLOR_SWAP_GBR:
+ */
+enum dsi_color_swap_mode {
+	DSI_COLOR_SWAP_RGB = 0,
+	DSI_COLOR_SWAP_RBG,
+	DSI_COLOR_SWAP_BGR,
+	DSI_COLOR_SWAP_BRG,
+	DSI_COLOR_SWAP_GRB,
+	DSI_COLOR_SWAP_GBR
+};
+
+/**
+ * enum dsi_dfps_type - Dynamic FPS support type
+ * @DSI_DFPS_NONE:           Dynamic FPS is not supported.
+ * @DSI_DFPS_SUSPEND_RESUME:
+ * @DSI_DFPS_IMMEDIATE_CLK:
+ * @DSI_DFPS_IMMEDIATE_HFP:
+ * @DSI_DFPS_IMMEDIATE_VFP:
+ * @DSI_DPFS_MAX:
+ */
+enum dsi_dfps_type {
+	DSI_DFPS_NONE = 0,
+	DSI_DFPS_SUSPEND_RESUME,
+	DSI_DFPS_IMMEDIATE_CLK,
+	DSI_DFPS_IMMEDIATE_HFP,
+	DSI_DFPS_IMMEDIATE_VFP,
+	DSI_DFPS_MAX
+};
+
+/**
+ * enum dsi_phy_type - DSI phy types
+ * @DSI_PHY_TYPE_DPHY:
+ * @DSI_PHY_TYPE_CPHY:
+ */
+enum dsi_phy_type {
+	DSI_PHY_TYPE_DPHY,
+	DSI_PHY_TYPE_CPHY
+};
+
+/**
+ * enum dsi_te_mode - dsi te source
+ * @DSI_TE_ON_DATA_LINK:    TE read from DSI link
+ * @DSI_TE_ON_EXT_PIN:      TE signal on an external GPIO
+ */
+enum dsi_te_mode {
+	DSI_TE_ON_DATA_LINK = 0,
+	DSI_TE_ON_EXT_PIN,
+};
+
+/**
+ * enum dsi_video_traffic_mode - video mode pixel transmission type
+ * @DSI_VIDEO_TRAFFIC_SYNC_PULSES:       Non-burst mode with sync pulses.
+ * @DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS: Non-burst mode with sync start events.
+ * @DSI_VIDEO_TRAFFIC_BURST_MODE:        Burst mode using sync start events.
+ */
+enum dsi_video_traffic_mode {
+	DSI_VIDEO_TRAFFIC_SYNC_PULSES = 0,
+	DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS,
+	DSI_VIDEO_TRAFFIC_BURST_MODE,
+};
+
+/**
+ * struct dsi_mode_info - video mode information dsi frame
+ * @h_active:         Active width of one frame in pixels.
+ * @h_back_porch:     Horizontal back porch in pixels.
+ * @h_sync_width:     HSYNC width in pixels.
+ * @h_front_porch:    Horizontal fron porch in pixels.
+ * @h_skew:
+ * @h_sync_polarity:  Polarity of HSYNC (false is active low).
+ * @v_active:         Active height of one frame in lines.
+ * @v_back_porch:     Vertical back porch in lines.
+ * @v_sync_width:     VSYNC width in lines.
+ * @v_front_porch:    Vertical front porch in lines.
+ * @v_sync_polarity:  Polarity of VSYNC (false is active low).
+ * @refresh_rate:     Refresh rate in Hz.
+ */
+struct dsi_mode_info {
+	u32 h_active;
+	u32 h_back_porch;
+	u32 h_sync_width;
+	u32 h_front_porch;
+	u32 h_skew;
+	bool h_sync_polarity;
+
+	u32 v_active;
+	u32 v_back_porch;
+	u32 v_sync_width;
+	u32 v_front_porch;
+	bool v_sync_polarity;
+
+	u32 refresh_rate;
+};
+
+/**
+ * struct dsi_lane_mapping - Mapping between DSI logical and physical lanes
+ * @physical_lane0:   Logical lane to which physical lane 0 is mapped.
+ * @physical_lane1:   Logical lane to which physical lane 1 is mapped.
+ * @physical_lane2:   Logical lane to which physical lane 2 is mapped.
+ * @physical_lane3:   Logical lane to which physical lane 3 is mapped.
+ */
+struct dsi_lane_mapping {
+	enum dsi_logical_lane physical_lane0;
+	enum dsi_logical_lane physical_lane1;
+	enum dsi_logical_lane physical_lane2;
+	enum dsi_logical_lane physical_lane3;
+};
+
+/**
+ * struct dsi_host_common_cfg - Host configuration common to video and cmd mode
+ * @dst_format:          Destination pixel format.
+ * @data_lanes:          Physical data lanes to be enabled.
+ * @en_crc_check:        Enable CRC checks.
+ * @en_ecc_check:        Enable ECC checks.
+ * @te_mode:             Source for TE signalling.
+ * @mdp_cmd_trigger:     MDP frame update trigger for command mode.
+ * @dma_cmd_trigger:     Command DMA trigger.
+ * @cmd_trigger_stream:  Command mode stream to trigger.
+ * @bit_swap_read:       Is red color bit swapped.
+ * @bit_swap_green:      Is green color bit swapped.
+ * @bit_swap_blue:       Is blue color bit swapped.
+ * @t_clk_post:          Number of byte clock cycles that the transmitter shall
+ *                       continue sending after last data lane has transitioned
+ *                       to LP mode.
+ * @t_clk_pre:           Number of byte clock cycles that the high spped clock
+ *                       shall be driven prior to data lane transitions from LP
+ *                       to HS mode.
+ * @ignore_rx_eot:       Ignore Rx EOT packets if set to true.
+ * @append_tx_eot:       Append EOT packets for forward transmissions if set to
+ *                       true.
+ */
+struct dsi_host_common_cfg {
+	enum dsi_pixel_format dst_format;
+	enum dsi_data_lanes data_lanes;
+	bool en_crc_check;
+	bool en_ecc_check;
+	enum dsi_te_mode te_mode;
+	enum dsi_trigger_type mdp_cmd_trigger;
+	enum dsi_trigger_type dma_cmd_trigger;
+	u32 cmd_trigger_stream;
+	enum dsi_color_swap_mode swap_mode;
+	bool bit_swap_red;
+	bool bit_swap_green;
+	bool bit_swap_blue;
+	u32 t_clk_post;
+	u32 t_clk_pre;
+	bool ignore_rx_eot;
+	bool append_tx_eot;
+};
+
+/**
+ * struct dsi_video_engine_cfg - DSI video engine configuration
+ * @host_cfg:                  Pointer to host common configuration.
+ * @last_line_interleave_en:   Allow command mode op interleaved on last line of
+ *                             video stream.
+ * @pulse_mode_hsa_he:         Send HSA and HE following VS/VE packet if set to
+ *                             true.
+ * @hfp_lp11_en:               Enter low power stop mode (LP-11) during HFP.
+ * @hbp_lp11_en:               Enter low power stop mode (LP-11) during HBP.
+ * @hsa_lp11_en:               Enter low power stop mode (LP-11) during HSA.
+ * @eof_bllp_lp11_en:          Enter low power stop mode (LP-11) during BLLP of
+ *                             last line of a frame.
+ * @bllp_lp11_en:              Enter low power stop mode (LP-11) during BLLP.
+ * @traffic_mode:              Traffic mode for video stream.
+ * @vc_id:                     Virtual channel identifier.
+ */
+struct dsi_video_engine_cfg {
+	bool last_line_interleave_en;
+	bool pulse_mode_hsa_he;
+	bool hfp_lp11_en;
+	bool hbp_lp11_en;
+	bool hsa_lp11_en;
+	bool eof_bllp_lp11_en;
+	bool bllp_lp11_en;
+	enum dsi_video_traffic_mode traffic_mode;
+	u32 vc_id;
+};
+
+/**
+ * struct dsi_cmd_engine_cfg - DSI command engine configuration
+ * @host_cfg:                  Pointer to host common configuration.
+ * @host_cfg:                      Common host configuration
+ * @max_cmd_packets_interleave     Maximum number of command mode RGB packets to
+ *                                 send with in one horizontal blanking period
+ *                                 of the video mode frame.
+ * @wr_mem_start:                  DCS command for write_memory_start.
+ * @wr_mem_continue:               DCS command for write_memory_continue.
+ * @insert_dcs_command:            Insert DCS command as first byte of payload
+ *                                 of the pixel data.
+ * @mdp_transfer_time_us   Specifies the mdp transfer time for command mode
+ *                         panels in microseconds
+ */
+struct dsi_cmd_engine_cfg {
+	u32 max_cmd_packets_interleave;
+	u32 wr_mem_start;
+	u32 wr_mem_continue;
+	bool insert_dcs_command;
+	u32 mdp_transfer_time_us;
+};
+
+/**
+ * struct dsi_host_config - DSI host configuration parameters.
+ * @panel_mode:            Operation mode for panel (video or cmd mode).
+ * @common_config:         Host configuration common to both Video and Cmd mode.
+ * @video_engine:          Video engine configuration if panel is in video mode.
+ * @cmd_engine:            Cmd engine configuration if panel is in cmd mode.
+ * @esc_clk_rate_khz:      Esc clock frequency in Hz.
+ * @bit_clk_rate_hz:       Bit clock frequency in Hz.
+ * @video_timing:          Video timing information of a frame.
+ * @lane_map:              Mapping between logical and physical lanes.
+ * @phy_type:              PHY type to be used.
+ */
+struct dsi_host_config {
+	enum dsi_op_mode panel_mode;
+	struct dsi_host_common_cfg common_config;
+	union {
+		struct dsi_video_engine_cfg video_engine;
+		struct dsi_cmd_engine_cfg cmd_engine;
+	} u;
+	u64 esc_clk_rate_hz;
+	u64 bit_clk_rate_hz;
+	struct dsi_mode_info video_timing;
+	struct dsi_lane_mapping lane_map;
+};
+
+/**
+ * struct dsi_display_mode - specifies mode for dsi display
+ * @timing:         Timing parameters for the panel.
+ * @pixel_clk_khz:  Pixel clock in Khz.
+ * @panel_mode:     Panel operation mode.
+ * @flags:          Additional flags.
+ */
+struct dsi_display_mode {
+	struct dsi_mode_info timing;
+	u32 pixel_clk_khz;
+	enum dsi_op_mode panel_mode;
+
+	u32 flags;
+};
+
+#endif /* _DSI_DEFS_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a166a4bae93f4bebc174d2c592e63ad292ba4d8
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -0,0 +1,2588 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"msm-dsi-display:[%s] " fmt, __func__
+
+#include <linux/list.h>
+#include <linux/of.h>
+
+#include "msm_drv.h"
+#include "dsi_display.h"
+#include "dsi_panel.h"
+#include "dsi_ctrl.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_drm.h"
+
+#define to_dsi_display(x) container_of(x, struct dsi_display, host)
+
+static DEFINE_MUTEX(dsi_display_list_lock);
+static LIST_HEAD(dsi_display_list);
+
+static const struct of_device_id dsi_display_dt_match[] = {
+	{.compatible = "qcom,dsi-display"},
+	{}
+};
+
+static struct dsi_display *main_display;
+
+int dsi_display_set_backlight(void *display, u32 bl_lvl)
+{
+	struct dsi_display *dsi_display = display;
+	struct dsi_panel *panel;
+	int rc = 0;
+
+	if (dsi_display == NULL)
+		return -EINVAL;
+
+	panel = dsi_display->panel;
+
+	rc = dsi_panel_set_backlight(panel, bl_lvl);
+	if (rc)
+		pr_err("unable to set backlight\n");
+
+	return rc;
+}
+
+static ssize_t debugfs_dump_info_read(struct file *file,
+				      char __user *buff,
+				      size_t count,
+				      loff_t *ppos)
+{
+	struct dsi_display *display = file->private_data;
+	char *buf;
+	u32 len = 0;
+	int i;
+
+	if (!display)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0;
+
+	buf = kzalloc(SZ_4K, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
+	len += snprintf(buf + len, (SZ_4K - len),
+			"\tResolution = %dx%d\n",
+			display->config.video_timing.h_active,
+			display->config.video_timing.v_active);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		len += snprintf(buf + len, (SZ_4K - len),
+				"\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
+				i, display->ctrl[i].ctrl->name,
+				display->ctrl[i].phy->name);
+	}
+
+	len += snprintf(buf + len, (SZ_4K - len),
+			"\tPanel = %s\n", display->panel->name);
+
+	len += snprintf(buf + len, (SZ_4K - len),
+			"\tClock master = %s\n",
+			display->ctrl[display->clk_master_idx].ctrl->name);
+
+	if (copy_to_user(buff, buf, len)) {
+		kfree(buf);
+		return -EFAULT;
+	}
+
+	*ppos += len;
+
+	kfree(buf);
+	return len;
+}
+
+
+static const struct file_operations dump_info_fops = {
+	.open = simple_open,
+	.read = debugfs_dump_info_read,
+};
+
+static int dsi_display_debugfs_init(struct dsi_display *display)
+{
+	int rc = 0;
+	struct dentry *dir, *dump_file;
+
+	dir = debugfs_create_dir(display->name, NULL);
+	if (IS_ERR_OR_NULL(dir)) {
+		rc = PTR_ERR(dir);
+		pr_err("[%s] debugfs create dir failed, rc = %d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	dump_file = debugfs_create_file("dump_info",
+					0444,
+					dir,
+					display,
+					&dump_info_fops);
+	if (IS_ERR_OR_NULL(dump_file)) {
+		rc = PTR_ERR(dump_file);
+		pr_err("[%s] debugfs create file failed, rc=%d\n",
+		       display->name, rc);
+		goto error_remove_dir;
+	}
+
+	display->root = dir;
+	return rc;
+error_remove_dir:
+	debugfs_remove(dir);
+error:
+	return rc;
+}
+
+static int dsi_display_debugfs_deinit(struct dsi_display *display)
+{
+	debugfs_remove_recursive(display->root);
+
+	return 0;
+}
+
+static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
+					struct dsi_display_mode *mode)
+{
+	if (display->ctrl_count > 1) {
+		mode->timing.h_active /= display->ctrl_count;
+		mode->timing.h_front_porch /= display->ctrl_count;
+		mode->timing.h_sync_width /= display->ctrl_count;
+		mode->timing.h_back_porch /= display->ctrl_count;
+		mode->timing.h_skew /= display->ctrl_count;
+		mode->pixel_clk_khz /= display->ctrl_count;
+	}
+}
+
+static int dsi_display_ctrl_power_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_VREG_ON);
+		if (rc) {
+			pr_err("[%s] Failed to set power state, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+
+	return rc;
+error:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+		(void)dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_OFF);
+	}
+	return rc;
+}
+
+static int dsi_display_ctrl_power_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_OFF);
+		if (rc) {
+			pr_err("[%s] Failed to power off, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_phy_power_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_phy_set_power_state(ctrl->phy, true);
+		if (rc) {
+			pr_err("[%s] Failed to set power state, rc=%d\n",
+			       ctrl->phy->name, rc);
+			goto error;
+		}
+	}
+
+	return rc;
+error:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->phy)
+			continue;
+		(void)dsi_phy_set_power_state(ctrl->phy, false);
+	}
+	return rc;
+}
+
+static int dsi_display_phy_power_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->phy)
+			continue;
+
+		rc = dsi_phy_set_power_state(ctrl->phy, false);
+		if (rc) {
+			pr_err("[%s] Failed to power off, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_core_clk_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, the clock for master controller should
+	 * be enabled before the other controller. Master controller in the
+	 * clock context refers to the controller that sources the clock.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON);
+	if (rc) {
+		pr_err("[%s] failed to turn on clocks, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	/* Turn on rest of the controllers */
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_CORE_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn on clock, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_VREG_ON);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_link_clk_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, the clock for master controller should
+	 * be enabled before the other controller. Master controller in the
+	 * clock context refers to the controller that sources the clock.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
+				       &display->clock_info.src_clks);
+	if (rc) {
+		pr_err("[%s] failed to set source clocks for master, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON);
+	if (rc) {
+		pr_err("[%s] failed to turn on clocks, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	/* Turn on rest of the controllers */
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
+					       &display->clock_info.src_clks);
+		if (rc) {
+			pr_err("[%s] failed to set source clocks, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_LINK_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn on clock, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_power_state(m_ctrl->ctrl,
+				       DSI_CTRL_POWER_CORE_CLK_ON);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_core_clk_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, clock for slave DSI controllers should
+	 * be disabled first before disabling clock for master controller. Slave
+	 * controllers in the clock context refer to controller which source
+	 * clock from another controller.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_VREG_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn off clock, rc=%d\n",
+			       display->name, rc);
+		}
+	}
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_VREG_ON);
+	if (rc)
+		pr_err("[%s] failed to turn off clocks, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_ctrl_link_clk_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, clock for slave DSI controllers should
+	 * be disabled first before disabling clock for master controller. Slave
+	 * controllers in the clock context refer to controller which source
+	 * clock from another controller.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_CORE_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn off clock, rc=%d\n",
+			       display->name, rc);
+		}
+	}
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON);
+	if (rc)
+		pr_err("[%s] failed to turn off clocks, rc=%d\n",
+		       display->name, rc);
+	return rc;
+}
+
+static int dsi_display_ctrl_init(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0 ; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_host_init(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to init host_%d, rc=%d\n",
+			       display->name, i, rc);
+			goto error_host_deinit;
+		}
+	}
+
+	return 0;
+error_host_deinit:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		(void)dsi_ctrl_host_deinit(ctrl->ctrl);
+	}
+	return rc;
+}
+
+static int dsi_display_ctrl_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0 ; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_host_deinit(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to deinit host_%d, rc=%d\n",
+			       display->name, i, rc);
+		}
+	}
+
+	return rc;
+}
+
+static int dsi_display_cmd_engine_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	if (display->cmd_engine_refcount > 0) {
+		display->cmd_engine_refcount++;
+		return 0;
+	}
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	display->cmd_engine_refcount++;
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_cmd_engine_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	if (display->cmd_engine_refcount == 0) {
+		pr_err("[%s] Invalid refcount\n", display->name);
+		return 0;
+	} else if (display->cmd_engine_refcount > 1) {
+		display->cmd_engine_refcount--;
+		return 0;
+	}
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	display->cmd_engine_refcount = 0;
+	return rc;
+}
+
+static int dsi_display_ctrl_host_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable host engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
+						    DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable sl host engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_host_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
+						    DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to disable host engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc) {
+		pr_err("[%s] failed to disable host engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_vid_engine_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->video_master_idx];
+
+	rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable vid engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable vid engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_vid_engine_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->video_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to disable vid engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc)
+		pr_err("[%s] failed to disable mvid engine, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_phy_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+	enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+	if (display->ctrl_count > 1)
+		m_src = DSI_PLL_SOURCE_NATIVE;
+
+	rc = dsi_phy_enable(m_ctrl->phy,
+			    &display->config,
+			    m_src,
+			    true);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_phy_enable(ctrl->phy,
+				    &display->config,
+				    DSI_PLL_SOURCE_NON_NATIVE,
+				    true);
+		if (rc) {
+			pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+
+error_disable_master:
+	(void)dsi_phy_disable(m_ctrl->phy);
+error:
+	return rc;
+}
+
+static int dsi_display_phy_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_phy_disable(ctrl->phy);
+		if (rc)
+			pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_phy_disable(m_ctrl->phy);
+	if (rc)
+		pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_wake_up(struct dsi_display *display)
+{
+	return 0;
+}
+
+static int dsi_display_broadcast_cmd(struct dsi_display *display,
+				     const struct mipi_dsi_msg *msg)
+{
+	int rc = 0;
+	u32 flags, m_flags;
+	struct dsi_display_ctrl *ctrl, *m_ctrl;
+	int i;
+
+	m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
+		   DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FIFO_STORE);
+	flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
+		 DSI_CTRL_CMD_FIFO_STORE);
+
+	/*
+	 * 1. Setup commands in FIFO
+	 * 2. Trigger commands
+	 */
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, m_flags);
+	if (rc) {
+		pr_err("[%s] cmd transfer failed on master,rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (ctrl == m_ctrl)
+			continue;
+
+		rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, flags);
+		if (rc) {
+			pr_err("[%s] cmd transfer failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+		rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl,
+			DSI_CTRL_CMD_BROADCAST);
+		if (rc) {
+			pr_err("[%s] cmd trigger failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+	rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl,
+				(DSI_CTRL_CMD_BROADCAST_MASTER |
+				 DSI_CTRL_CMD_BROADCAST));
+	if (rc) {
+		pr_err("[%s] cmd trigger failed for master, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_phy_sw_reset(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
+	if (rc) {
+		pr_err("[%s] failed to reset phy, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to reset phy, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_host_attach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static int dsi_host_detach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
+				 const struct mipi_dsi_msg *msg)
+{
+	struct dsi_display *display = to_dsi_display(host);
+
+	int rc = 0;
+
+	if (!host || !msg) {
+		pr_err("Invalid params\n");
+		return 0;
+	}
+
+	rc = dsi_display_wake_up(display);
+	if (rc) {
+		pr_err("[%s] failed to wake up display, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_cmd_engine_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	if (display->ctrl_count > 1) {
+		rc = dsi_display_broadcast_cmd(display, msg);
+		if (rc) {
+			pr_err("[%s] cmd broadcast failed, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_cmd_engine;
+		}
+	} else {
+		rc = dsi_ctrl_cmd_transfer(display->ctrl[0].ctrl, msg,
+					  DSI_CTRL_CMD_FIFO_STORE);
+		if (rc) {
+			pr_err("[%s] cmd transfer failed, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_cmd_engine;
+		}
+	}
+error_disable_cmd_engine:
+	(void)dsi_display_cmd_engine_disable(display);
+error:
+	return rc;
+}
+
+
+static struct mipi_dsi_host_ops dsi_host_ops = {
+	.attach = dsi_host_attach,
+	.detach = dsi_host_detach,
+	.transfer = dsi_host_transfer,
+};
+
+static int dsi_display_mipi_host_init(struct dsi_display *display)
+{
+	int rc = 0;
+	struct mipi_dsi_host *host = &display->host;
+
+	host->dev = &display->pdev->dev;
+	host->ops = &dsi_host_ops;
+
+	rc = mipi_dsi_host_register(host);
+	if (rc) {
+		pr_err("[%s] failed to register mipi dsi host, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+static int dsi_display_mipi_host_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	struct mipi_dsi_host *host = &display->host;
+
+	mipi_dsi_host_unregister(host);
+
+	host->dev = NULL;
+	host->ops = NULL;
+
+	return rc;
+}
+
+static int dsi_display_clocks_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	struct dsi_clk_link_set *src = &display->clock_info.src_clks;
+	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
+	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
+
+	if (src->byte_clk) {
+		devm_clk_put(&display->pdev->dev, src->byte_clk);
+		src->byte_clk = NULL;
+	}
+
+	if (src->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, src->pixel_clk);
+		src->pixel_clk = NULL;
+	}
+
+	if (mux->byte_clk) {
+		devm_clk_put(&display->pdev->dev, mux->byte_clk);
+		mux->byte_clk = NULL;
+	}
+
+	if (mux->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, mux->pixel_clk);
+		mux->pixel_clk = NULL;
+	}
+
+	if (shadow->byte_clk) {
+		devm_clk_put(&display->pdev->dev, shadow->byte_clk);
+		shadow->byte_clk = NULL;
+	}
+
+	if (shadow->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
+		shadow->pixel_clk = NULL;
+	}
+
+	return rc;
+}
+
+static int dsi_display_clocks_init(struct dsi_display *display)
+{
+	int rc = 0;
+	struct dsi_clk_link_set *src = &display->clock_info.src_clks;
+	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
+	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
+
+	src->byte_clk = devm_clk_get(&display->pdev->dev, "src_byte_clk");
+	if (IS_ERR_OR_NULL(src->byte_clk)) {
+		rc = PTR_ERR(src->byte_clk);
+		src->byte_clk = NULL;
+		pr_err("failed to get src_byte_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	src->pixel_clk = devm_clk_get(&display->pdev->dev, "src_pixel_clk");
+	if (IS_ERR_OR_NULL(src->pixel_clk)) {
+		rc = PTR_ERR(src->pixel_clk);
+		src->pixel_clk = NULL;
+		pr_err("failed to get src_pixel_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	mux->byte_clk = devm_clk_get(&display->pdev->dev, "mux_byte_clk");
+	if (IS_ERR_OR_NULL(mux->byte_clk)) {
+		rc = PTR_ERR(mux->byte_clk);
+		pr_err("failed to get mux_byte_clk, rc=%d\n", rc);
+		mux->byte_clk = NULL;
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	mux->pixel_clk = devm_clk_get(&display->pdev->dev, "mux_pixel_clk");
+	if (IS_ERR_OR_NULL(mux->pixel_clk)) {
+		rc = PTR_ERR(mux->pixel_clk);
+		mux->pixel_clk = NULL;
+		pr_err("failed to get mux_pixel_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	shadow->byte_clk = devm_clk_get(&display->pdev->dev, "shadow_byte_clk");
+	if (IS_ERR_OR_NULL(shadow->byte_clk)) {
+		rc = PTR_ERR(shadow->byte_clk);
+		shadow->byte_clk = NULL;
+		pr_err("failed to get shadow_byte_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	shadow->pixel_clk = devm_clk_get(&display->pdev->dev,
+					 "shadow_pixel_clk");
+	if (IS_ERR_OR_NULL(shadow->pixel_clk)) {
+		rc = PTR_ERR(shadow->pixel_clk);
+		shadow->pixel_clk = NULL;
+		pr_err("failed to get shadow_pixel_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+done:
+	return 0;
+error:
+	(void)dsi_display_clocks_deinit(display);
+	return rc;
+}
+
+static int dsi_display_parse_lane_map(struct dsi_display *display)
+{
+	int rc = 0;
+
+	display->lane_map.physical_lane0 = DSI_LOGICAL_LANE_0;
+	display->lane_map.physical_lane1 = DSI_LOGICAL_LANE_1;
+	display->lane_map.physical_lane2 = DSI_LOGICAL_LANE_2;
+	display->lane_map.physical_lane3 = DSI_LOGICAL_LANE_3;
+	return rc;
+}
+
+static int dsi_display_parse_dt(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	u32 phy_count = 0;
+	struct device_node *of_node;
+
+	/* Parse controllers */
+	for (i = 0; i < MAX_DSI_CTRLS_PER_DISPLAY; i++) {
+		of_node = of_parse_phandle(display->pdev->dev.of_node,
+					   "qcom,dsi-ctrl", i);
+		if (!of_node) {
+			if (!i) {
+				pr_err("No controllers present\n");
+				return -ENODEV;
+			}
+			break;
+		}
+
+		display->ctrl[i].ctrl_of_node = of_node;
+		display->ctrl_count++;
+	}
+
+	/* Parse Phys */
+	for (i = 0; i < MAX_DSI_CTRLS_PER_DISPLAY; i++) {
+		of_node = of_parse_phandle(display->pdev->dev.of_node,
+					   "qcom,dsi-phy", i);
+		if (!of_node) {
+			if (!i) {
+				pr_err("No PHY devices present\n");
+				rc = -ENODEV;
+				goto error;
+			}
+			break;
+		}
+
+		display->ctrl[i].phy_of_node = of_node;
+		phy_count++;
+	}
+
+	if (phy_count != display->ctrl_count) {
+		pr_err("Number of controllers does not match PHYs\n");
+		rc = -ENODEV;
+		goto error;
+	}
+
+	of_node = of_parse_phandle(display->pdev->dev.of_node,
+				   "qcom,dsi-panel", 0);
+	if (!of_node) {
+		pr_err("No Panel device present\n");
+		rc = -ENODEV;
+		goto error;
+	} else {
+		display->panel_of = of_node;
+	}
+
+	rc = dsi_display_parse_lane_map(display);
+	if (rc) {
+		pr_err("Lane map not found, rc=%d\n", rc);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_res_init(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
+		if (IS_ERR_OR_NULL(ctrl->ctrl)) {
+			rc = PTR_ERR(ctrl->ctrl);
+			pr_err("failed to get dsi controller, rc=%d\n", rc);
+			ctrl->ctrl = NULL;
+			goto error_ctrl_put;
+		}
+
+		ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
+		if (IS_ERR_OR_NULL(ctrl->phy)) {
+			rc = PTR_ERR(ctrl->phy);
+			pr_err("failed to get phy controller, rc=%d\n", rc);
+			dsi_ctrl_put(ctrl->ctrl);
+			ctrl->phy = NULL;
+			goto error_ctrl_put;
+		}
+	}
+
+	display->panel = dsi_panel_get(&display->pdev->dev, display->panel_of);
+	if (IS_ERR_OR_NULL(display->panel)) {
+		rc = PTR_ERR(display->panel);
+		pr_err("failed to get panel, rc=%d\n", rc);
+		display->panel = NULL;
+		goto error_ctrl_put;
+	}
+
+	rc = dsi_display_clocks_init(display);
+	if (rc) {
+		pr_err("Failed to parse clock data, rc=%d\n", rc);
+		goto error_ctrl_put;
+	}
+
+	return 0;
+error_ctrl_put:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		dsi_ctrl_put(ctrl->ctrl);
+		dsi_phy_put(ctrl->phy);
+	}
+	return rc;
+}
+
+static int dsi_display_res_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	rc = dsi_display_clocks_deinit(display);
+	if (rc)
+		pr_err("clocks deinit failed, rc=%d\n", rc);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		dsi_phy_put(ctrl->phy);
+		dsi_ctrl_put(ctrl->ctrl);
+	}
+
+	return rc;
+}
+
+static int dsi_display_validate_mode_set(struct dsi_display *display,
+					 struct dsi_display_mode *mode,
+					 u32 flags)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/*
+	 * To set a mode:
+	 * 1. Controllers should be turned off.
+	 * 2. Link clocks should be off.
+	 * 3. Phy should be disabled.
+	 */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
+		    (ctrl->phy_enabled)) {
+			rc = -EINVAL;
+			goto error;
+		}
+	}
+
+error:
+	return rc;
+}
+
+static bool dsi_display_is_seamless_dfps_possible(
+		const struct dsi_display *display,
+		const struct dsi_display_mode *tgt,
+		const enum dsi_dfps_type dfps_type)
+{
+	struct dsi_display_mode *cur;
+
+	if (!display || !tgt) {
+		pr_err("Invalid params\n");
+		return false;
+	}
+
+	cur = &display->panel->mode;
+
+	if (cur->timing.h_active != tgt->timing.h_active) {
+		pr_debug("timing.h_active differs %d %d\n",
+				cur->timing.h_active, tgt->timing.h_active);
+		return false;
+	}
+
+	if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
+		pr_debug("timing.h_back_porch differs %d %d\n",
+				cur->timing.h_back_porch,
+				tgt->timing.h_back_porch);
+		return false;
+	}
+
+	if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
+		pr_debug("timing.h_sync_width differs %d %d\n",
+				cur->timing.h_sync_width,
+				tgt->timing.h_sync_width);
+		return false;
+	}
+
+	if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
+		pr_debug("timing.h_front_porch differs %d %d\n",
+				cur->timing.h_front_porch,
+				tgt->timing.h_front_porch);
+		if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
+			return false;
+	}
+
+	if (cur->timing.h_skew != tgt->timing.h_skew) {
+		pr_debug("timing.h_skew differs %d %d\n",
+				cur->timing.h_skew,
+				tgt->timing.h_skew);
+		return false;
+	}
+
+	/* skip polarity comparison */
+
+	if (cur->timing.v_active != tgt->timing.v_active) {
+		pr_debug("timing.v_active differs %d %d\n",
+				cur->timing.v_active,
+				tgt->timing.v_active);
+		return false;
+	}
+
+	if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
+		pr_debug("timing.v_back_porch differs %d %d\n",
+				cur->timing.v_back_porch,
+				tgt->timing.v_back_porch);
+		return false;
+	}
+
+	if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
+		pr_debug("timing.v_sync_width differs %d %d\n",
+				cur->timing.v_sync_width,
+				tgt->timing.v_sync_width);
+		return false;
+	}
+
+	if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
+		pr_debug("timing.v_front_porch differs %d %d\n",
+				cur->timing.v_front_porch,
+				tgt->timing.v_front_porch);
+		if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
+			return false;
+	}
+
+	/* skip polarity comparison */
+
+	if (cur->timing.refresh_rate == tgt->timing.refresh_rate) {
+		pr_debug("timing.refresh_rate identical %d %d\n",
+				cur->timing.refresh_rate,
+				tgt->timing.refresh_rate);
+		return false;
+	}
+
+	if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
+		pr_debug("pixel_clk_khz differs %d %d\n",
+				cur->pixel_clk_khz, tgt->pixel_clk_khz);
+
+	if (cur->panel_mode != tgt->panel_mode) {
+		pr_debug("panel_mode differs %d %d\n",
+				cur->panel_mode, tgt->panel_mode);
+		return false;
+	}
+
+	if (cur->flags != tgt->flags)
+		pr_debug("flags differs %d %d\n", cur->flags, tgt->flags);
+
+	return true;
+}
+
+static int dsi_display_dfps_update(struct dsi_display *display,
+				   struct dsi_display_mode *dsi_mode)
+{
+	struct dsi_mode_info *timing;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+	struct dsi_display_mode *panel_mode;
+	struct dsi_dfps_capabilities dfps_caps;
+	int rc = 0;
+	int i;
+
+	if (!display || !dsi_mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+	timing = &dsi_mode->timing;
+
+	dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
+	if (!dfps_caps.dfps_support) {
+		pr_err("dfps not supported\n");
+		return -ENOTSUPP;
+	}
+
+	if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
+		pr_err("dfps clock method not supported\n");
+		return -ENOTSUPP;
+	}
+
+	/* For split DSI, update the clock master first */
+
+	pr_debug("configuring seamless dynamic fps\n\n");
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+	rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
+	if (rc) {
+		pr_err("[%s] failed to dfps update host_%d, rc=%d\n",
+				display->name, i, rc);
+		goto error;
+	}
+
+	/* Update the rest of the controllers */
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
+		if (rc) {
+			pr_err("[%s] failed to dfps update host_%d, rc=%d\n",
+					display->name, i, rc);
+			goto error;
+		}
+	}
+
+	panel_mode = &display->panel->mode;
+	memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
+
+error:
+	return rc;
+}
+
+static int dsi_display_dfps_calc_front_porch(
+		u64 clk_hz,
+		u32 new_fps,
+		u32 a_total,
+		u32 b_total,
+		u32 b_fp,
+		u32 *b_fp_out)
+{
+	s32 b_fp_new;
+
+	if (!b_fp_out) {
+		pr_err("Invalid params");
+		return -EINVAL;
+	}
+
+	if (!a_total || !new_fps) {
+		pr_err("Invalid pixel total or new fps in mode request\n");
+		return -EINVAL;
+	}
+
+	/**
+	 * Keep clock, other porches constant, use new fps, calc front porch
+	 * clk = (hor * ver * fps)
+	 * hfront = clk / (vtotal * fps)) - hactive - hback - hsync
+	 */
+	b_fp_new = (clk_hz / (a_total * new_fps)) - (b_total - b_fp);
+
+	pr_debug("clk %llu fps %u a %u b %u b_fp %u new_fp %d\n",
+			clk_hz, new_fps, a_total, b_total, b_fp, b_fp_new);
+
+	if (b_fp_new < 0) {
+		pr_err("Invalid new_hfp calcluated%d\n", b_fp_new);
+		return -EINVAL;
+	}
+
+	/**
+	 * TODO: To differentiate from clock method when communicating to the
+	 * other components, perhaps we should set clk here to original value
+	 */
+	*b_fp_out = b_fp_new;
+
+	return 0;
+}
+
+static int dsi_display_get_dfps_timing(struct dsi_display *display,
+				       struct dsi_display_mode *adj_mode)
+{
+	struct dsi_dfps_capabilities dfps_caps;
+	struct dsi_display_mode per_ctrl_mode;
+	struct dsi_mode_info *timing;
+	struct dsi_ctrl *m_ctrl;
+	u64 clk_hz;
+
+	int rc = 0;
+
+	if (!display || !adj_mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+	m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
+
+	dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
+	if (!dfps_caps.dfps_support) {
+		pr_err("dfps not supported by panel\n");
+		return -EINVAL;
+	}
+
+	per_ctrl_mode = *adj_mode;
+	adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
+
+	if (!dsi_display_is_seamless_dfps_possible(display,
+			&per_ctrl_mode, dfps_caps.type)) {
+		pr_err("seamless dynamic fps not supported for mode\n");
+		return -EINVAL;
+	}
+
+	/* TODO: Remove this direct reference to the dsi_ctrl */
+	clk_hz = m_ctrl->clk_info.link_clks.pixel_clk_rate;
+	timing = &per_ctrl_mode.timing;
+
+	switch (dfps_caps.type) {
+	case DSI_DFPS_IMMEDIATE_VFP:
+		rc = dsi_display_dfps_calc_front_porch(
+				clk_hz,
+				timing->refresh_rate,
+				DSI_H_TOTAL(timing),
+				DSI_V_TOTAL(timing),
+				timing->v_front_porch,
+				&adj_mode->timing.v_front_porch);
+		break;
+
+	case DSI_DFPS_IMMEDIATE_HFP:
+		rc = dsi_display_dfps_calc_front_porch(
+				clk_hz,
+				timing->refresh_rate,
+				DSI_V_TOTAL(timing),
+				DSI_H_TOTAL(timing),
+				timing->h_front_porch,
+				&adj_mode->timing.h_front_porch);
+		if (!rc)
+			adj_mode->timing.h_front_porch *= display->ctrl_count;
+		break;
+
+	default:
+		pr_err("Unsupported DFPS mode %d\n", dfps_caps.type);
+		rc = -ENOTSUPP;
+	}
+
+	return rc;
+}
+
+static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
+		struct dsi_display_mode *adj_mode)
+{
+	int rc = 0;
+
+	if (!display || !adj_mode) {
+		pr_err("Invalid params\n");
+		return false;
+	}
+
+	/* Currently the only seamless transition is dynamic fps */
+	rc = dsi_display_get_dfps_timing(display, adj_mode);
+	if (rc) {
+		pr_debug("Dynamic FPS not supported for seamless\n");
+	} else {
+		pr_debug("Mode switch is seamless Dynamic FPS\n");
+		adj_mode->flags |= DSI_MODE_FLAG_DFPS |
+				DSI_MODE_FLAG_VBLANK_PRE_MODESET;
+	}
+
+	return rc;
+}
+
+static int dsi_display_set_mode_sub(struct dsi_display *display,
+				    struct dsi_display_mode *mode,
+				    u32 flags)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	rc = dsi_panel_get_host_cfg_for_mode(display->panel,
+					     mode,
+					     &display->config);
+	if (rc) {
+		pr_err("[%s] failed to get host config for mode, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	memcpy(&display->config.lane_map, &display->lane_map,
+	       sizeof(display->lane_map));
+
+	if (mode->flags & DSI_MODE_FLAG_DFPS) {
+		rc = dsi_display_dfps_update(display, mode);
+		if (rc) {
+			pr_err("[%s]DSI dfps update failed, rc=%d\n",
+					display->name, rc);
+			goto error;
+		}
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
+				mode->flags);
+		if (rc) {
+			pr_err("[%s] failed to update ctrl config, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+	}
+error:
+	return rc;
+}
+
+/**
+ * _dsi_display_dev_init - initializes the display device
+ * Initialization will acquire references to the resources required for the
+ * display hardware to function.
+ * @display:         Handle to the display
+ * Returns:          Zero on success
+ */
+static int _dsi_display_dev_init(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("invalid display\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_parse_dt(display);
+	if (rc) {
+		pr_err("[%s] failed to parse dt, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_res_init(display);
+	if (rc) {
+		pr_err("[%s] failed to initialize resources, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+/**
+ * _dsi_display_dev_deinit - deinitializes the display device
+ * All the resources acquired during device init will be released.
+ * @display:        Handle to the display
+ * Returns:         Zero on success
+ */
+static int _dsi_display_dev_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("invalid display\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_res_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinitialize resource, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+
+	return rc;
+}
+
+/**
+ * dsi_display_bind - bind dsi device with controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ * Returns:     Zero on success
+ */
+static int dsi_display_bind(struct device *dev,
+		struct device *master,
+		void *data)
+{
+	struct dsi_display_ctrl *display_ctrl;
+	struct drm_device *drm;
+	struct dsi_display *display;
+	struct platform_device *pdev = to_platform_device(dev);
+	int i, rc = 0;
+
+	if (!dev || !pdev || !master) {
+		pr_err("invalid param(s), dev %pK, pdev %pK, master %pK\n",
+				dev, pdev, master);
+		return -EINVAL;
+	}
+
+	drm = dev_get_drvdata(master);
+	display = platform_get_drvdata(pdev);
+	if (!drm || !display) {
+		pr_err("invalid param(s), drm %pK, display %pK\n",
+				drm, display);
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_debugfs_init(display);
+	if (rc) {
+		pr_err("[%s] debugfs init failed, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		display_ctrl = &display->ctrl[i];
+
+		rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
+		if (rc) {
+			pr_err("[%s] failed to initialize ctrl[%d], rc=%d\n",
+			       display->name, i, rc);
+			goto error_ctrl_deinit;
+		}
+
+		rc = dsi_phy_drv_init(display_ctrl->phy);
+		if (rc) {
+			pr_err("[%s] Failed to initialize phy[%d], rc=%d\n",
+				display->name, i, rc);
+			(void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+			goto error_ctrl_deinit;
+		}
+	}
+
+	rc = dsi_display_mipi_host_init(display);
+	if (rc) {
+		pr_err("[%s] failed to initialize mipi host, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_deinit;
+	}
+
+	rc = dsi_panel_drv_init(display->panel, &display->host);
+	if (rc) {
+		if (rc != -EPROBE_DEFER)
+			pr_err("[%s] failed to initialize panel driver, rc=%d\n",
+			       display->name, rc);
+		goto error_host_deinit;
+	}
+
+	rc = dsi_panel_get_mode_count(display->panel, &display->num_of_modes);
+	if (rc) {
+		pr_err("[%s] failed to get mode count, rc=%d\n",
+		       display->name, rc);
+		goto error_panel_deinit;
+	}
+
+	display->drm_dev = drm;
+	goto error;
+
+error_panel_deinit:
+	(void)dsi_panel_drv_deinit(display->panel);
+error_host_deinit:
+	(void)dsi_display_mipi_host_deinit(display);
+error_ctrl_deinit:
+	for (i = i - 1; i >= 0; i--) {
+		display_ctrl = &display->ctrl[i];
+		(void)dsi_phy_drv_deinit(display_ctrl->phy);
+		(void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+	}
+	(void)dsi_display_debugfs_deinit(display);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+/**
+ * dsi_display_unbind - unbind dsi from controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ */
+static void dsi_display_unbind(struct device *dev,
+		struct device *master, void *data)
+{
+	struct dsi_display_ctrl *display_ctrl;
+	struct dsi_display *display;
+	struct platform_device *pdev = to_platform_device(dev);
+	int i, rc = 0;
+
+	if (!dev || !pdev) {
+		pr_err("invalid param(s)\n");
+		return;
+	}
+
+	display = platform_get_drvdata(pdev);
+	if (!display) {
+		pr_err("invalid display\n");
+		return;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_drv_deinit(display->panel);
+	if (rc)
+		pr_err("[%s] failed to deinit panel driver, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_mipi_host_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinit mipi hosts, rc=%d\n",
+		       display->name,
+		       rc);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		display_ctrl = &display->ctrl[i];
+
+		rc = dsi_phy_drv_deinit(display_ctrl->phy);
+		if (rc)
+			pr_err("[%s] failed to deinit phy%d driver, rc=%d\n",
+			       display->name, i, rc);
+
+		rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+		if (rc)
+			pr_err("[%s] failed to deinit ctrl%d driver, rc=%d\n",
+			       display->name, i, rc);
+	}
+	(void)dsi_display_debugfs_deinit(display);
+
+	mutex_unlock(&display->display_lock);
+}
+
+static const struct component_ops dsi_display_comp_ops = {
+	.bind = dsi_display_bind,
+	.unbind = dsi_display_unbind,
+};
+
+static struct platform_driver dsi_display_driver = {
+	.probe = dsi_display_dev_probe,
+	.remove = dsi_display_dev_remove,
+	.driver = {
+		.name = "msm-dsi-display",
+		.of_match_table = dsi_display_dt_match,
+	},
+};
+
+int dsi_display_dev_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
+	if (!display)
+		return -ENOMEM;
+
+	display->name = of_get_property(pdev->dev.of_node, "label", NULL);
+
+	display->is_active = of_property_read_bool(pdev->dev.of_node,
+						"qcom,dsi-display-active");
+
+	display->display_type = of_get_property(pdev->dev.of_node,
+						"qcom,display-type", NULL);
+	if (!display->display_type)
+		display->display_type = "unknown";
+
+	mutex_init(&display->display_lock);
+
+	display->pdev = pdev;
+	platform_set_drvdata(pdev, display);
+	mutex_lock(&dsi_display_list_lock);
+	list_add(&display->list, &dsi_display_list);
+	mutex_unlock(&dsi_display_list_lock);
+
+	if (display->is_active) {
+		main_display = display;
+		rc = _dsi_display_dev_init(display);
+		if (rc) {
+			pr_err("device init failed, rc=%d\n", rc);
+			return rc;
+		}
+
+		rc = component_add(&pdev->dev, &dsi_display_comp_ops);
+		if (rc)
+			pr_err("component add failed, rc=%d\n", rc);
+	}
+	return rc;
+}
+
+int dsi_display_dev_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+	struct dsi_display *pos, *tmp;
+
+	if (!pdev) {
+		pr_err("Invalid device\n");
+		return -EINVAL;
+	}
+
+	display = platform_get_drvdata(pdev);
+
+	(void)_dsi_display_dev_deinit(display);
+
+	mutex_lock(&dsi_display_list_lock);
+	list_for_each_entry_safe(pos, tmp, &dsi_display_list, list) {
+		if (pos == display) {
+			list_del(&display->list);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_display_list_lock);
+
+	platform_set_drvdata(pdev, NULL);
+	devm_kfree(&pdev->dev, display);
+	return rc;
+}
+
+int dsi_display_get_num_of_displays(void)
+{
+	int count = 0;
+	struct dsi_display *display;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(display, &dsi_display_list, list) {
+		count++;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return count;
+}
+
+int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
+{
+	struct dsi_display *pos;
+	int i = 0;
+
+	if (!display_array || !max_display_count) {
+		if (!display_array)
+			pr_err("invalid params\n");
+		return 0;
+	}
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (i >= max_display_count) {
+			pr_err("capping display count to %d\n", i);
+			break;
+		}
+		if (pos->is_active)
+			display_array[i++] = pos;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return i;
+}
+
+struct dsi_display *dsi_display_get_display_by_name(const char *name)
+{
+	struct dsi_display *display = NULL, *pos;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (!strcmp(name, pos->name))
+			display = pos;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+
+	return display;
+}
+
+void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
+{
+	mutex_lock(&display->display_lock);
+	display->is_active = is_active;
+	mutex_unlock(&display->display_lock);
+}
+
+int dsi_display_drm_bridge_init(struct dsi_display *display,
+		struct drm_encoder *enc)
+{
+	int rc = 0;
+	struct dsi_bridge *bridge;
+	struct msm_drm_private *priv = NULL;
+
+	if (!display || !display->drm_dev || !enc) {
+		pr_err("invalid param(s)\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+	priv = display->drm_dev->dev_private;
+
+	if (!priv) {
+		pr_err("Private data is not present\n");
+		rc = -EINVAL;
+		goto error;
+	}
+
+	if (display->bridge) {
+		pr_err("display is already initialize\n");
+		goto error;
+	}
+
+	bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
+	if (IS_ERR_OR_NULL(bridge)) {
+		rc = PTR_ERR(bridge);
+		pr_err("[%s] brige init failed, %d\n", display->name, rc);
+		goto error;
+	}
+
+	display->bridge = bridge;
+	priv->bridges[priv->num_bridges++] = &bridge->base;
+
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_drm_bridge_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	dsi_drm_bridge_cleanup(display->bridge);
+	display->bridge = NULL;
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_get_info(struct msm_display_info *info, void *disp)
+{
+	struct dsi_display *display;
+	struct dsi_panel_phy_props phy_props;
+	int i, rc;
+
+	if (!info || !disp) {
+		pr_err("invalid params\n");
+		return -EINVAL;
+	}
+	display = disp;
+
+	mutex_lock(&display->display_lock);
+	rc = dsi_panel_get_phy_props(display->panel, &phy_props);
+	if (rc) {
+		pr_err("[%s] failed to get panel phy props, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	info->intf_type = DRM_MODE_CONNECTOR_DSI;
+
+	info->num_of_h_tiles = display->ctrl_count;
+	for (i = 0; i < info->num_of_h_tiles; i++)
+		info->h_tile_instance[i] = display->ctrl[i].ctrl->index;
+
+	info->is_connected = true;
+	info->width_mm = phy_props.panel_width_mm;
+	info->height_mm = phy_props.panel_height_mm;
+	info->max_width = 1920;
+	info->max_height = 1080;
+	info->compression = MSM_DISPLAY_COMPRESS_NONE;
+
+	switch (display->panel->mode.panel_mode) {
+	case DSI_OP_VIDEO_MODE:
+		info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
+		break;
+	case DSI_OP_CMD_MODE:
+		info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
+		break;
+	default:
+		pr_err("unknwown dsi panel mode %d\n",
+				display->panel->mode.panel_mode);
+		break;
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_get_modes(struct dsi_display *display,
+			  struct dsi_display_mode *modes,
+			  u32 *count)
+{
+	int rc = 0;
+	int i;
+	struct dsi_dfps_capabilities dfps_caps;
+	int num_dfps_rates;
+
+	if (!display || !count) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
+	if (rc) {
+		pr_err("[%s] failed to get dfps caps from panel\n",
+				display->name);
+		goto error;
+	}
+
+	num_dfps_rates = !dfps_caps.dfps_support ? 1 :
+			dfps_caps.max_refresh_rate -
+			dfps_caps.min_refresh_rate + 1;
+
+	if (!modes) {
+		/* Inflate num_of_modes by fps in dfps */
+		*count = display->num_of_modes * num_dfps_rates;
+		goto error;
+	}
+
+	for (i = 0; i < *count; i++) {
+		/* Insert the dfps "sub-modes" between main panel modes */
+		int panel_mode_idx = i / num_dfps_rates;
+
+		rc = dsi_panel_get_mode(display->panel, panel_mode_idx, modes);
+		if (rc) {
+			pr_err("[%s] failed to get mode from panel\n",
+			       display->name);
+			goto error;
+		}
+
+		if (dfps_caps.dfps_support) {
+			modes->timing.refresh_rate = dfps_caps.min_refresh_rate
+					+ (i % num_dfps_rates);
+			modes->pixel_clk_khz = (DSI_H_TOTAL(&modes->timing) *
+					DSI_V_TOTAL(&modes->timing) *
+					modes->timing.refresh_rate) / 1000;
+		}
+
+		if (display->ctrl_count > 1) { /* TODO: remove if */
+			modes->timing.h_active *= display->ctrl_count;
+			modes->timing.h_front_porch *= display->ctrl_count;
+			modes->timing.h_sync_width *= display->ctrl_count;
+			modes->timing.h_back_porch *= display->ctrl_count;
+			modes->timing.h_skew *= display->ctrl_count;
+			modes->pixel_clk_khz *= display->ctrl_count;
+		}
+
+		modes++;
+	}
+
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_validate_mode(struct dsi_display *display,
+			      struct dsi_display_mode *mode,
+			      u32 flags)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+	struct dsi_display_mode adj_mode;
+
+	if (!display || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	adj_mode = *mode;
+	adjust_timing_by_ctrl_count(display, &adj_mode);
+
+	rc = dsi_panel_validate_mode(display->panel, &adj_mode);
+	if (rc) {
+		pr_err("[%s] panel mode validation failed, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
+		if (rc) {
+			pr_err("[%s] ctrl mode validation failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+		rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
+		if (rc) {
+			pr_err("[%s] phy mode validation failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+	if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
+			(mode->flags & DSI_MODE_FLAG_SEAMLESS)) {
+		rc = dsi_display_validate_mode_seamless(display, mode);
+		if (rc) {
+			pr_err("[%s] seamless not possible rc=%d\n",
+				display->name, rc);
+			goto error;
+		}
+	}
+
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_set_mode(struct dsi_display *display,
+			 struct dsi_display_mode *mode,
+			 u32 flags)
+{
+	int rc = 0;
+	struct dsi_display_mode adj_mode;
+
+	if (!display || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	adj_mode = *mode;
+	adjust_timing_by_ctrl_count(display, &adj_mode);
+
+	rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
+	if (rc) {
+		pr_err("[%s] mode cannot be set\n", display->name);
+		goto error;
+	}
+
+	rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
+	if (rc) {
+		pr_err("[%s] failed to set mode\n", display->name);
+		goto error;
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
+		if (rc) {
+			pr_err("[%s] failed to set tpg state for host_%d\n",
+			       display->name, i);
+			goto error;
+		}
+	}
+
+	display->is_tpg_enabled = enable;
+error:
+	return rc;
+}
+
+int dsi_display_prepare(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_pre_prepare(display->panel);
+	if (rc) {
+		pr_err("[%s] panel pre-prepare failed, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_ctrl_power_on(display);
+	if (rc) {
+		pr_err("[%s] failed to power on dsi controllers, rc=%d\n",
+		       display->name, rc);
+		goto error_panel_post_unprep;
+	}
+
+	rc = dsi_display_phy_power_on(display);
+	if (rc) {
+		pr_err("[%s] failed to power on dsi phy, rc = %d\n",
+		       display->name, rc);
+		goto error_ctrl_pwr_off;
+	}
+
+	rc = dsi_display_ctrl_core_clk_on(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI core clocks, rc=%d\n",
+		       display->name, rc);
+		goto error_phy_pwr_off;
+	}
+
+	rc = dsi_display_phy_sw_reset(display);
+	if (rc) {
+		pr_err("[%s] failed to reset phy, rc=%d\n", display->name, rc);
+		goto error_ctrl_clk_off;
+	}
+
+	rc = dsi_display_phy_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_clk_off;
+	}
+
+	rc = dsi_display_ctrl_init(display);
+	if (rc) {
+		pr_err("[%s] failed to setup DSI controller, rc=%d\n",
+		       display->name, rc);
+		goto error_phy_disable;
+	}
+
+	rc = dsi_display_ctrl_link_clk_on(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI link clocks, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_deinit;
+	}
+
+	rc = dsi_display_ctrl_host_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI host, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_link_off;
+	}
+
+	rc = dsi_panel_prepare(display->panel);
+	if (rc) {
+		pr_err("[%s] panel prepare failed, rc=%d\n", display->name, rc);
+		goto error_host_engine_off;
+	}
+
+	goto error;
+
+error_host_engine_off:
+	(void)dsi_display_ctrl_host_disable(display);
+error_ctrl_link_off:
+	(void)dsi_display_ctrl_link_clk_off(display);
+error_ctrl_deinit:
+	(void)dsi_display_ctrl_deinit(display);
+error_phy_disable:
+	(void)dsi_display_phy_disable(display);
+error_ctrl_clk_off:
+	(void)dsi_display_ctrl_core_clk_off(display);
+error_phy_pwr_off:
+	(void)dsi_display_phy_power_off(display);
+error_ctrl_pwr_off:
+	(void)dsi_display_ctrl_power_off(display);
+error_panel_post_unprep:
+	(void)dsi_panel_post_unprepare(display->panel);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_enable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_enable(display->panel);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI panel, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
+		rc = dsi_display_vid_engine_enable(display);
+		if (rc) {
+			pr_err("[%s]failed to enable DSI video engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_panel;
+		}
+	} else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
+		rc = dsi_display_cmd_engine_enable(display);
+		if (rc) {
+			pr_err("[%s]failed to enable DSI cmd engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_panel;
+		}
+	} else {
+		pr_err("[%s] Invalid configuration\n", display->name);
+		rc = -EINVAL;
+		goto error_disable_panel;
+	}
+
+	goto error;
+
+error_disable_panel:
+	(void)dsi_panel_disable(display->panel);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_post_enable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_post_enable(display->panel);
+	if (rc)
+		pr_err("[%s] panel post-enable failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_pre_disable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_pre_disable(display->panel);
+	if (rc)
+		pr_err("[%s] panel pre-disable failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_disable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_wake_up(display);
+	if (rc)
+		pr_err("[%s] display wake up failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_disable(display->panel);
+	if (rc)
+		pr_err("[%s] failed to disable DSI panel, rc=%d\n",
+		       display->name, rc);
+
+	if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
+		rc = dsi_display_vid_engine_disable(display);
+		if (rc)
+			pr_err("[%s]failed to disable DSI vid engine, rc=%d\n",
+			       display->name, rc);
+	} else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
+		rc = dsi_display_cmd_engine_disable(display);
+		if (rc)
+			pr_err("[%s]failed to disable DSI cmd engine, rc=%d\n",
+			       display->name, rc);
+	} else {
+		pr_err("[%s] Invalid configuration\n", display->name);
+		rc = -EINVAL;
+	}
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_unprepare(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_wake_up(display);
+	if (rc)
+		pr_err("[%s] display wake up failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_unprepare(display->panel);
+	if (rc)
+		pr_err("[%s] panel unprepare failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_host_disable(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI host, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_link_clk_off(display);
+	if (rc)
+		pr_err("[%s] failed to disable Link clocks, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinit controller, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_phy_disable(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_core_clk_off(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI clocks, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_phy_power_off(display);
+	if (rc)
+		pr_err("[%s] failed to power off PHY, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_power_off(display);
+	if (rc)
+		pr_err("[%s] failed to power DSI vregs, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_post_unprepare(display->panel);
+	if (rc)
+		pr_err("[%s] panel post-unprepare failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+static int __init dsi_display_register(void)
+{
+	dsi_phy_drv_register();
+	dsi_ctrl_drv_register();
+	return platform_driver_register(&dsi_display_driver);
+}
+
+static void __exit dsi_display_unregister(void)
+{
+	platform_driver_unregister(&dsi_display_driver);
+	dsi_ctrl_drv_unregister();
+	dsi_phy_drv_unregister();
+}
+
+module_init(dsi_display_register);
+module_exit(dsi_display_unregister);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
new file mode 100644
index 0000000000000000000000000000000000000000..b77bf268dbd18a3ed680efc388b78fa25d70944d
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_DISPLAY_H_
+#define _DSI_DISPLAY_H_
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/debugfs.h>
+#include <linux/of_device.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+
+#include "msm_drv.h"
+#include "dsi_defs.h"
+#include "dsi_ctrl.h"
+#include "dsi_phy.h"
+#include "dsi_panel.h"
+
+#define MAX_DSI_CTRLS_PER_DISPLAY             2
+
+/*
+ * DSI Validate Mode modifiers
+ * @DSI_VALIDATE_FLAG_ALLOW_ADJUST:	Allow mode validation to also do fixup
+ */
+#define DSI_VALIDATE_FLAG_ALLOW_ADJUST	0x1
+
+/**
+ * enum dsi_display_type - enumerates DSI display types
+ * @DSI_DISPLAY_SINGLE:       A panel connected on a single DSI interface.
+ * @DSI_DISPLAY_EXT_BRIDGE:   A bridge is connected between panel and DSI host.
+ *			      It utilizes a single DSI interface.
+ * @DSI_DISPLAY_SPLIT:        A panel that utilizes more than one DSI
+ *			      interfaces.
+ * @DSI_DISPLAY_SPLIT_EXT_BRIDGE: A bridge is present between panel and DSI
+ *				  host. It utilizes more than one DSI interface.
+ */
+enum dsi_display_type {
+	DSI_DISPLAY_SINGLE = 0,
+	DSI_DISPLAY_EXT_BRIDGE,
+	DSI_DISPLAY_SPLIT,
+	DSI_DISPLAY_SPLIT_EXT_BRIDGE,
+	DSI_DISPLAY_MAX,
+};
+
+/**
+ * struct dsi_display_ctrl - dsi ctrl/phy information for the display
+ * @ctrl:           Handle to the DSI controller device.
+ * @ctrl_of_node:   pHandle to the DSI controller device.
+ * @dsi_ctrl_idx:   DSI controller instance id.
+ * @power_state:    Current power state of the DSI controller.
+ * @phy:                  Handle to the DSI PHY device.
+ * @phy_of_node:          pHandle to the DSI PHY device.
+ * @phy_enabled:          PHY power status.
+ */
+struct dsi_display_ctrl {
+	/* controller info */
+	struct dsi_ctrl *ctrl;
+	struct device_node *ctrl_of_node;
+	u32 dsi_ctrl_idx;
+
+	enum dsi_power_state power_state;
+
+	/* phy info */
+	struct msm_dsi_phy *phy;
+	struct device_node *phy_of_node;
+
+	bool phy_enabled;
+};
+
+/**
+ * struct dsi_display_clk_info - dsi display clock source information
+ * @src_clks:          Source clocks for DSI display.
+ * @mux_clks:          Mux clocks used for DFPS.
+ * @shadow_clks:       Used for DFPS.
+ */
+struct dsi_display_clk_info {
+	struct dsi_clk_link_set src_clks;
+	struct dsi_clk_link_set mux_clks;
+	struct dsi_clk_link_set shadow_clks;
+};
+
+/**
+ * struct dsi_display - dsi display information
+ * @pdev:             Pointer to platform device.
+ * @drm_dev:          DRM device associated with the display.
+ * @name:             Name of the display.
+ * @display_type:     Display type as defined in device tree.
+ * @list:             List pointer.
+ * @is_active:        Is display active.
+ * @display_lock:     Mutex for dsi_display interface.
+ * @ctrl_count:       Number of DSI interfaces required by panel.
+ * @ctrl:             Controller information for DSI display.
+ * @panel:            Handle to DSI panel.
+ * @panel_of:         pHandle to DSI panel.
+ * @type:             DSI display type.
+ * @clk_master_idx:   The master controller for controlling clocks. This is an
+ *		      index into the ctrl[MAX_DSI_CTRLS_PER_DISPLAY] array.
+ * @cmd_master_idx:   The master controller for sending DSI commands to panel.
+ * @video_master_idx: The master controller for enabling video engine.
+ * @clock_info:       Clock sourcing for DSI display.
+ * @lane_map:         Lane mapping between DSI host and Panel.
+ * @num_of_modes:     Number of modes supported by display.
+ * @is_tpg_enabled:   TPG state.
+ * @host:             DRM MIPI DSI Host.
+ * @connector:        Pointer to DRM connector object.
+ * @bridge:           Pointer to DRM bridge object.
+ * @cmd_engine_refcount:  Reference count enforcing single instance of cmd eng
+ * @root:                 Debugfs root directory
+ */
+struct dsi_display {
+	struct platform_device *pdev;
+	struct drm_device *drm_dev;
+
+	const char *name;
+	const char *display_type;
+	struct list_head list;
+	bool is_active;
+	struct mutex display_lock;
+
+	u32 ctrl_count;
+	struct dsi_display_ctrl ctrl[MAX_DSI_CTRLS_PER_DISPLAY];
+
+	/* panel info */
+	struct dsi_panel *panel;
+	struct device_node *panel_of;
+
+	enum dsi_display_type type;
+	u32 clk_master_idx;
+	u32 cmd_master_idx;
+	u32 video_master_idx;
+
+	struct dsi_display_clk_info clock_info;
+	struct dsi_host_config config;
+	struct dsi_lane_mapping lane_map;
+	u32 num_of_modes;
+	bool is_tpg_enabled;
+
+	struct mipi_dsi_host host;
+	struct dsi_bridge    *bridge;
+	u32 cmd_engine_refcount;
+
+	/* DEBUG FS */
+	struct dentry *root;
+};
+
+int dsi_display_dev_probe(struct platform_device *pdev);
+int dsi_display_dev_remove(struct platform_device *pdev);
+
+/**
+ * dsi_display_get_num_of_displays() - returns number of display devices
+ *				       supported.
+ *
+ * Return: number of displays.
+ */
+int dsi_display_get_num_of_displays(void);
+
+/**
+ * dsi_display_get_active_displays - returns pointers for active display devices
+ * @display_array: Pointer to display array to be filled
+ * @max_display_count: Size of display_array
+ * @Returns: Number of display entries filled
+ */
+int dsi_display_get_active_displays(void **display_array,
+		u32 max_display_count);
+
+/**
+ * dsi_display_get_display_by_name()- finds display by name
+ * @index:      name of the display.
+ *
+ * Return: handle to the display or error code.
+ */
+struct dsi_display *dsi_display_get_display_by_name(const char *name);
+
+/**
+ * dsi_display_set_active_state() - sets the state of the display
+ * @display:        Handle to display.
+ * @is_active:      state
+ */
+void dsi_display_set_active_state(struct dsi_display *display, bool is_active);
+
+/**
+ * dsi_display_drm_bridge_init() - initializes DRM bridge object for DSI
+ * @display:            Handle to the display.
+ * @encoder:            Pointer to the encoder object which is connected to the
+ *			display.
+ *
+ * Return: error code.
+ */
+int dsi_display_drm_bridge_init(struct dsi_display *display,
+		struct drm_encoder *enc);
+
+/**
+ * dsi_display_drm_bridge_deinit() - destroys DRM bridge for the display
+ * @display:        Handle to the display.
+ *
+ * Return: error code.
+ */
+int dsi_display_drm_bridge_deinit(struct dsi_display *display);
+
+/**
+ * dsi_display_get_info() - returns the display properties
+ * @info:             Pointer to the structure where info is stored.
+ * @disp:             Handle to the display.
+ *
+ * Return: error code.
+ */
+int dsi_display_get_info(struct msm_display_info *info, void *disp);
+
+/**
+ * dsi_display_get_modes() - get modes supported by display
+ * @display:            Handle to display.
+ * @modes;              Pointer to array of modes. Memory allocated should be
+ *			big enough to store (count * struct dsi_display_mode)
+ *			elements. If modes pointer is NULL, number of modes will
+ *			be stored in the memory pointed to by count.
+ * @count:              If modes is NULL, number of modes will be stored. If
+ *			not, mode information will be copied (number of modes
+ *			copied will be equal to *count).
+ *
+ * Return: error code.
+ */
+int dsi_display_get_modes(struct dsi_display *display,
+			  struct dsi_display_mode *modes,
+			  u32 *count);
+
+/**
+ * dsi_display_validate_mode() - validates if mode is supported by display
+ * @display:             Handle to display.
+ * @mode:                Mode to be validated.
+ * @flags:               Modifier flags.
+ *
+ * Return: 0 if supported or error code.
+ */
+int dsi_display_validate_mode(struct dsi_display *display,
+			      struct dsi_display_mode *mode,
+			      u32 flags);
+
+/**
+ * dsi_display_set_mode() - Set mode on the display.
+ * @display:           Handle to display.
+ * @mode:              mode to be set.
+ * @flags:             Modifier flags.
+ *
+ * Return: error code.
+ */
+int dsi_display_set_mode(struct dsi_display *display,
+			 struct dsi_display_mode *mode,
+			 u32 flags);
+
+/**
+ * dsi_display_prepare() - prepare display
+ * @display:          Handle to display.
+ *
+ * Prepare will perform power up sequences for the host and panel hardware.
+ * Power and clock resources might be turned on (depending on the panel mode).
+ * The video engine is not enabled.
+ *
+ * Return: error code.
+ */
+int dsi_display_prepare(struct dsi_display *display);
+
+/**
+ * dsi_display_enable() - enable display
+ * @display:            Handle to display.
+ *
+ * Enable will turn on the host engine and the panel. At the end of the enable
+ * function, Host and panel hardware are ready to accept pixel data from
+ * upstream.
+ *
+ * Return: error code.
+ */
+int dsi_display_enable(struct dsi_display *display);
+
+/**
+ * dsi_display_post_enable() - perform post enable operations.
+ * @display:         Handle to display.
+ *
+ * Some panels might require some commands to be sent after pixel data
+ * transmission has started. Such commands are sent as part of the post_enable
+ * function.
+ *
+ * Return: error code.
+ */
+int dsi_display_post_enable(struct dsi_display *display);
+
+/**
+ * dsi_display_pre_disable() - perform pre disable operations.
+ * @display:          Handle to display.
+ *
+ * If a panel requires commands to be sent before pixel data transmission is
+ * stopped, those can be sent as part of pre_disable.
+ *
+ * Return: error code.
+ */
+int dsi_display_pre_disable(struct dsi_display *display);
+
+/**
+ * dsi_display_disable() - disable panel and host hardware.
+ * @display:             Handle to display.
+ *
+ * Disable host and panel hardware and pixel data transmission can not continue.
+ *
+ * Return: error code.
+ */
+int dsi_display_disable(struct dsi_display *display);
+
+/**
+ * dsi_display_unprepare() - power off display hardware.
+ * @display:            Handle to display.
+ *
+ * Host and panel hardware is turned off. Panel will be in reset state at the
+ * end of the function.
+ *
+ * Return: error code.
+ */
+int dsi_display_unprepare(struct dsi_display *display);
+
+int dsi_display_set_tpg_state(struct dsi_display *display, bool enable);
+
+int dsi_display_clock_gate(struct dsi_display *display, bool enable);
+int dsi_dispaly_static_frame(struct dsi_display *display, bool enable);
+
+int dsi_display_set_backlight(void *display, u32 bl_lvl);
+#endif /* _DSI_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..93fb041399e26a82061fbba7f7873a5aafb93116
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "dsi_display_test.h"
+
+static void dsi_display_test_dump_modes(struct dsi_display_mode *mode, u32
+					count)
+{
+}
+
+static void dsi_display_test_work(struct work_struct *work)
+{
+	struct dsi_display_test *test;
+	struct dsi_display *display;
+	struct dsi_display_mode *modes;
+	u32 count = 0;
+	u32 size = 0;
+	int rc = 0;
+
+	test = container_of(work, struct dsi_display_test, test_work);
+
+	display = test->display;
+	rc = dsi_display_get_modes(display, NULL, &count);
+	if (rc) {
+		pr_err("failed to get modes count, rc=%d\n", rc);
+		goto test_fail;
+	}
+
+	size = count * sizeof(*modes);
+	modes = kzalloc(size, GFP_KERNEL);
+	if (!modes) {
+		rc = -ENOMEM;
+		goto test_fail;
+	}
+
+	rc = dsi_display_get_modes(display, modes, &count);
+	if (rc) {
+		pr_err("failed to get modes, rc=%d\n", rc);
+		goto test_fail_free_modes;
+	}
+
+	dsi_display_test_dump_modes(modes, count);
+
+	rc = dsi_display_set_mode(display, &modes[0], 0x0);
+	if (rc) {
+		pr_err("failed to set mode, rc=%d\n", rc);
+		goto test_fail_free_modes;
+	}
+
+	rc = dsi_display_prepare(display);
+	if (rc) {
+		pr_err("failed to prepare display, rc=%d\n", rc);
+		goto test_fail_free_modes;
+	}
+
+	rc = dsi_display_enable(display);
+	if (rc) {
+		pr_err("failed to enable display, rc=%d\n", rc);
+		goto test_fail_unprep_disp;
+	}
+	return;
+
+test_fail_unprep_disp:
+	if (rc) {
+		pr_err("failed to unprep display, rc=%d\n", rc);
+		goto test_fail_free_modes;
+	}
+
+test_fail_free_modes:
+	kfree(modes);
+test_fail:
+	return;
+}
+
+int dsi_display_test_init(struct dsi_display *display)
+{
+	static int done;
+	int rc = 0;
+	struct dsi_display_test *test;
+
+	if (done)
+		return rc;
+
+	done = 1;
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	test = kzalloc(sizeof(*test), GFP_KERNEL);
+	if (!test)
+		return -ENOMEM;
+
+	test->display = display;
+	INIT_WORK(&test->test_work, dsi_display_test_work);
+
+	dsi_display_test_work(&test->test_work);
+	return rc;
+}
+
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h
new file mode 100644
index 0000000000000000000000000000000000000000..e36569854ab1af6400d958cf75dbee6c6eb35708
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_DISPLAY_TEST_H_
+#define _DSI_DISPLAY_TEST_H_
+
+#include "dsi_display.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_ctrl.h"
+
+struct dsi_display_test {
+	struct dsi_display *display;
+
+	struct work_struct test_work;
+};
+
+int dsi_display_test_init(struct dsi_display *display);
+
+
+#endif /* _DSI_DISPLAY_TEST_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1adecf81cc0ff42b7a77c7721ec23c62ba8bc6c
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+#define pr_fmt(fmt)	"dsi-drm:[%s] " fmt, __func__
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+
+#include "msm_kms.h"
+#include "sde_connector.h"
+#include "dsi_drm.h"
+
+#define to_dsi_bridge(x)     container_of((x), struct dsi_bridge, base)
+#define to_dsi_state(x)      container_of((x), struct dsi_connector_state, base)
+
+static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
+				struct dsi_display_mode *dsi_mode)
+{
+	memset(dsi_mode, 0, sizeof(*dsi_mode));
+
+	dsi_mode->timing.h_active = drm_mode->hdisplay;
+	dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
+	dsi_mode->timing.h_sync_width = drm_mode->htotal -
+			(drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
+	dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
+					 drm_mode->hdisplay;
+	dsi_mode->timing.h_skew = drm_mode->hskew;
+
+	dsi_mode->timing.v_active = drm_mode->vdisplay;
+	dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
+	dsi_mode->timing.v_sync_width = drm_mode->vtotal -
+		(drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
+
+	dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
+					 drm_mode->vdisplay;
+
+	dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
+
+	dsi_mode->pixel_clk_khz = drm_mode->clock;
+	dsi_mode->panel_mode = 0; /* TODO: Panel Mode */
+
+	if (msm_is_mode_seamless(drm_mode))
+		dsi_mode->flags |= DSI_MODE_FLAG_SEAMLESS;
+	if (msm_is_mode_dynamic_fps(drm_mode))
+		dsi_mode->flags |= DSI_MODE_FLAG_DFPS;
+	if (msm_needs_vblank_pre_modeset(drm_mode))
+		dsi_mode->flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
+}
+
+static void convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
+				struct drm_display_mode *drm_mode)
+{
+	memset(drm_mode, 0, sizeof(*drm_mode));
+
+	drm_mode->hdisplay = dsi_mode->timing.h_active;
+	drm_mode->hsync_start = drm_mode->hdisplay +
+				dsi_mode->timing.h_front_porch;
+	drm_mode->hsync_end = drm_mode->hsync_start +
+			      dsi_mode->timing.h_sync_width;
+	drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
+	drm_mode->hskew = dsi_mode->timing.h_skew;
+
+	drm_mode->vdisplay = dsi_mode->timing.v_active;
+	drm_mode->vsync_start = drm_mode->vdisplay +
+				dsi_mode->timing.v_front_porch;
+	drm_mode->vsync_end = drm_mode->vsync_start +
+			      dsi_mode->timing.v_sync_width;
+	drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
+
+	drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
+	drm_mode->clock = dsi_mode->pixel_clk_khz;
+
+	if (dsi_mode->flags & DSI_MODE_FLAG_SEAMLESS)
+		drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
+	if (dsi_mode->flags & DSI_MODE_FLAG_DFPS)
+		drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
+	if (dsi_mode->flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
+		drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
+
+	drm_mode_set_name(drm_mode);
+}
+
+static int dsi_bridge_attach(struct drm_bridge *bridge)
+{
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	pr_debug("[%d] attached\n", c_bridge->id);
+
+	return 0;
+
+}
+
+static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
+{
+	int rc = 0;
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	/* By this point mode should have been validated through mode_fixup */
+	rc = dsi_display_set_mode(c_bridge->display,
+			&(c_bridge->dsi_mode), 0x0);
+	if (rc) {
+		pr_err("[%d] failed to perform a mode set, rc=%d\n",
+		       c_bridge->id, rc);
+		return;
+	}
+
+	if (c_bridge->dsi_mode.flags & DSI_MODE_FLAG_SEAMLESS) {
+		pr_debug("[%d] seamless pre-enable\n", c_bridge->id);
+		return;
+	}
+
+	rc = dsi_display_prepare(c_bridge->display);
+	if (rc) {
+		pr_err("[%d] DSI display prepare failed, rc=%d\n",
+		       c_bridge->id, rc);
+		return;
+	}
+
+	rc = dsi_display_enable(c_bridge->display);
+	if (rc) {
+		pr_err("[%d] DSI display enable failed, rc=%d\n",
+		       c_bridge->id, rc);
+		(void)dsi_display_unprepare(c_bridge->display);
+	}
+}
+
+static void dsi_bridge_enable(struct drm_bridge *bridge)
+{
+	int rc = 0;
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	if (c_bridge->dsi_mode.flags & DSI_MODE_FLAG_SEAMLESS) {
+		pr_debug("[%d] seamless enable\n", c_bridge->id);
+		return;
+	}
+
+	rc = dsi_display_post_enable(c_bridge->display);
+	if (rc)
+		pr_err("[%d] DSI display post enabled failed, rc=%d\n",
+		       c_bridge->id, rc);
+}
+
+static void dsi_bridge_disable(struct drm_bridge *bridge)
+{
+	int rc = 0;
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	rc = dsi_display_pre_disable(c_bridge->display);
+	if (rc) {
+		pr_err("[%d] DSI display pre disable failed, rc=%d\n",
+		       c_bridge->id, rc);
+	}
+}
+
+static void dsi_bridge_post_disable(struct drm_bridge *bridge)
+{
+	int rc = 0;
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	rc = dsi_display_disable(c_bridge->display);
+	if (rc) {
+		pr_err("[%d] DSI display disable failed, rc=%d\n",
+		       c_bridge->id, rc);
+		return;
+	}
+
+	rc = dsi_display_unprepare(c_bridge->display);
+	if (rc) {
+		pr_err("[%d] DSI display unprepare failed, rc=%d\n",
+		       c_bridge->id, rc);
+		return;
+	}
+}
+
+static void dsi_bridge_mode_set(struct drm_bridge *bridge,
+				struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+{
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+
+	if (!bridge || !mode || !adjusted_mode) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
+	convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
+
+	pr_debug("note: using panel cmd/vid mode instead of user val\n");
+	c_bridge->dsi_mode.panel_mode =
+		c_bridge->display->panel->mode.panel_mode;
+}
+
+static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
+				  const struct drm_display_mode *mode,
+				  struct drm_display_mode *adjusted_mode)
+{
+	int rc = 0;
+	bool ret = true;
+	struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
+	struct dsi_display_mode dsi_mode;
+
+	if (!bridge || !mode || !adjusted_mode) {
+		pr_err("Invalid params\n");
+		return false;
+	}
+
+	convert_to_dsi_mode(mode, &dsi_mode);
+
+	rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
+			DSI_VALIDATE_FLAG_ALLOW_ADJUST);
+	if (rc) {
+		pr_err("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
+		ret = false;
+	} else {
+		convert_to_drm_mode(&dsi_mode, adjusted_mode);
+	}
+
+	return ret;
+}
+
+static const struct drm_bridge_funcs dsi_bridge_ops = {
+	.attach       = dsi_bridge_attach,
+	.mode_fixup   = dsi_bridge_mode_fixup,
+	.pre_enable   = dsi_bridge_pre_enable,
+	.enable       = dsi_bridge_enable,
+	.disable      = dsi_bridge_disable,
+	.post_disable = dsi_bridge_post_disable,
+	.mode_set     = dsi_bridge_mode_set,
+};
+
+int dsi_conn_post_init(struct drm_connector *connector,
+		void *info,
+		void *display)
+{
+	struct dsi_display *dsi_display = display;
+	struct dsi_panel *panel;
+
+	if (!info || !dsi_display)
+		return -EINVAL;
+
+	sde_kms_info_add_keystr(info,
+		"display type", dsi_display->display_type);
+
+	switch (dsi_display->type) {
+	case DSI_DISPLAY_SINGLE:
+		sde_kms_info_add_keystr(info, "display config",
+					"single display");
+		break;
+	case DSI_DISPLAY_EXT_BRIDGE:
+		sde_kms_info_add_keystr(info, "display config", "ext bridge");
+		break;
+	case DSI_DISPLAY_SPLIT:
+		sde_kms_info_add_keystr(info, "display config",
+					"split display");
+		break;
+	case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
+		sde_kms_info_add_keystr(info, "display config",
+					"split ext bridge");
+		break;
+	default:
+		pr_debug("invalid display type:%d\n", dsi_display->type);
+		break;
+	}
+
+	if (!dsi_display->panel) {
+		pr_debug("invalid panel data\n");
+		goto end;
+	}
+
+	panel = dsi_display->panel;
+	sde_kms_info_add_keystr(info, "panel name", panel->name);
+
+	switch (panel->mode.panel_mode) {
+	case DSI_OP_VIDEO_MODE:
+		sde_kms_info_add_keystr(info, "panel mode", "video");
+		break;
+	case DSI_OP_CMD_MODE:
+		sde_kms_info_add_keystr(info, "panel mode", "command");
+		sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
+				panel->cmd_config.mdp_transfer_time_us);
+		break;
+	default:
+		pr_debug("invalid panel type:%d\n", panel->mode.panel_mode);
+		break;
+	}
+	sde_kms_info_add_keystr(info, "dfps support",
+			panel->dfps_caps.dfps_support ? "true" : "false");
+
+	switch (panel->phy_props.rotation) {
+	case DSI_PANEL_ROTATE_NONE:
+		sde_kms_info_add_keystr(info, "panel orientation", "none");
+		break;
+	case DSI_PANEL_ROTATE_H_FLIP:
+		sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
+		break;
+	case DSI_PANEL_ROTATE_V_FLIP:
+		sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
+		break;
+	default:
+		pr_debug("invalid panel rotation:%d\n",
+						panel->phy_props.rotation);
+		break;
+	}
+
+	switch (panel->bl_config.type) {
+	case DSI_BACKLIGHT_PWM:
+		sde_kms_info_add_keystr(info, "backlight type", "pwm");
+		break;
+	case DSI_BACKLIGHT_WLED:
+		sde_kms_info_add_keystr(info, "backlight type", "wled");
+		break;
+	case DSI_BACKLIGHT_DCS:
+		sde_kms_info_add_keystr(info, "backlight type", "dcs");
+		break;
+	default:
+		pr_debug("invalid panel backlight type:%d\n",
+						panel->bl_config.type);
+		break;
+	}
+
+end:
+	return 0;
+}
+
+enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
+		bool force,
+		void *display)
+{
+	enum drm_connector_status status = connector_status_unknown;
+	struct msm_display_info info;
+	int rc;
+
+	if (!conn || !display)
+		return status;
+
+	/* get display dsi_info */
+	memset(&info, 0x0, sizeof(info));
+	rc = dsi_display_get_info(&info, display);
+	if (rc) {
+		pr_err("failed to get display info, rc=%d\n", rc);
+		return connector_status_disconnected;
+	}
+
+	if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
+		status = (info.is_connected ? connector_status_connected :
+					      connector_status_disconnected);
+	else
+		status = connector_status_connected;
+
+	conn->display_info.width_mm = info.width_mm;
+	conn->display_info.height_mm = info.height_mm;
+
+	return status;
+}
+
+int dsi_connector_get_modes(struct drm_connector *connector,
+		void *display)
+{
+	u32 count = 0;
+	u32 size = 0;
+	struct dsi_display_mode *modes;
+	struct drm_display_mode drm_mode;
+	int rc, i;
+
+	if (sde_connector_get_panel(connector)) {
+		/*
+		 * TODO: If drm_panel is attached, query modes from the panel.
+		 * This is complicated in split dsi cases because panel is not
+		 * attached to both connectors.
+		 */
+		goto end;
+	}
+	rc = dsi_display_get_modes(display, NULL, &count);
+	if (rc) {
+		pr_err("failed to get num of modes, rc=%d\n", rc);
+		goto error;
+	}
+
+	size = count * sizeof(*modes);
+	modes = kzalloc(size,  GFP_KERNEL);
+	if (!modes) {
+		count = 0;
+		goto end;
+	}
+
+	rc = dsi_display_get_modes(display, modes, &count);
+	if (rc) {
+		pr_err("failed to get modes, rc=%d\n", rc);
+		count = 0;
+		goto error;
+	}
+
+	for (i = 0; i < count; i++) {
+		struct drm_display_mode *m;
+
+		memset(&drm_mode, 0x0, sizeof(drm_mode));
+		convert_to_drm_mode(&modes[i], &drm_mode);
+		m = drm_mode_duplicate(connector->dev, &drm_mode);
+		if (!m) {
+			pr_err("failed to add mode %ux%u\n",
+			       drm_mode.hdisplay,
+			       drm_mode.vdisplay);
+			count = -ENOMEM;
+			goto error;
+		}
+		m->width_mm = connector->display_info.width_mm;
+		m->height_mm = connector->display_info.height_mm;
+		drm_mode_probed_add(connector, m);
+	}
+error:
+	kfree(modes);
+end:
+	pr_debug("MODE COUNT =%d\n\n", count);
+	return count;
+}
+
+enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
+		struct drm_display_mode *mode,
+		void *display)
+{
+	struct dsi_display_mode dsi_mode;
+	int rc;
+
+	if (!connector || !mode) {
+		pr_err("Invalid params\n");
+		return MODE_ERROR;
+	}
+
+	convert_to_dsi_mode(mode, &dsi_mode);
+
+	rc = dsi_display_validate_mode(display, &dsi_mode,
+			DSI_VALIDATE_FLAG_ALLOW_ADJUST);
+	if (rc) {
+		pr_err("mode not supported, rc=%d\n", rc);
+		return MODE_BAD;
+	}
+
+	return MODE_OK;
+}
+
+struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
+				       struct drm_device *dev,
+				       struct drm_encoder *encoder)
+{
+	int rc = 0;
+	struct dsi_bridge *bridge;
+
+	bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		rc = -ENOMEM;
+		goto error;
+	}
+
+	bridge->display = display;
+	bridge->base.funcs = &dsi_bridge_ops;
+	bridge->base.encoder = encoder;
+
+	rc = drm_bridge_attach(dev, &bridge->base);
+	if (rc) {
+		pr_err("failed to attach bridge, rc=%d\n", rc);
+		goto error_free_bridge;
+	}
+
+	encoder->bridge = &bridge->base;
+	return bridge;
+error_free_bridge:
+	kfree(bridge);
+error:
+	return ERR_PTR(rc);
+}
+
+void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
+{
+	if (bridge && bridge->base.encoder)
+		bridge->base.encoder->bridge = NULL;
+
+	kfree(bridge);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
new file mode 100644
index 0000000000000000000000000000000000000000..934899bd206808ebb17c50f89ae60c238b439b3d
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_DRM_H_
+#define _DSI_DRM_H_
+
+#include <linux/types.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+
+#include "msm_drv.h"
+
+#include "dsi_display.h"
+
+struct dsi_bridge {
+	struct drm_bridge base;
+	u32 id;
+
+	struct dsi_display *display;
+	struct dsi_display_mode dsi_mode;
+};
+
+/**
+ * dsi_conn_post_init - callback to perform additional initialization steps
+ * @connector: Pointer to drm connector structure
+ * @info: Pointer to sde connector info structure
+ * @display: Pointer to private display handle
+ * Returns: Zero on success
+ */
+int dsi_conn_post_init(struct drm_connector *connector,
+		void *info,
+		void *display);
+
+/**
+ * dsi_conn_detect - callback to determine if connector is connected
+ * @connector: Pointer to drm connector structure
+ * @force: Force detect setting from drm framework
+ * @display: Pointer to private display handle
+ * Returns: Connector 'is connected' status
+ */
+enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
+		bool force,
+		void *display);
+
+/**
+ * dsi_connector_get_modes - callback to add drm modes via drm_mode_probed_add()
+ * @connector: Pointer to drm connector structure
+ * @display: Pointer to private display handle
+ * Returns: Number of modes added
+ */
+int dsi_connector_get_modes(struct drm_connector *connector,
+		void *display);
+
+/**
+ * dsi_conn_mode_valid - callback to determine if specified mode is valid
+ * @connector: Pointer to drm connector structure
+ * @mode: Pointer to drm mode structure
+ * @display: Pointer to private display handle
+ * Returns: Validity status for specified mode
+ */
+enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
+		struct drm_display_mode *mode,
+		void *display);
+
+struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
+		struct drm_device *dev,
+		struct drm_encoder *encoder);
+
+void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge);
+
+#endif /* _DSI_DRM_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..01535c02a7f83b68a755f0d7d4fd58bc5566e9b7
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_HW_H_
+#define _DSI_HW_H_
+#include <linux/io.h>
+
+#define DSI_R32(dsi_hw, off) readl_relaxed((dsi_hw)->base + (off))
+#define DSI_W32(dsi_hw, off, val) \
+	do {\
+		pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
+			(dsi_hw)->index, #off, val); \
+		writel_relaxed((val), (dsi_hw)->base + (off)); \
+	} while (0)
+
+#define DSI_MMSS_MISC_R32(dsi_hw, off) \
+	readl_relaxed((dsi_hw)->mmss_misc_base + (off))
+#define DSI_MMSS_MISC_W32(dsi_hw, off, val) \
+	do {\
+		pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
+			(dsi_hw)->index, #off, val); \
+		writel_relaxed((val), (dsi_hw)->mmss_misc_base + (off)); \
+	} while (0)
+
+#define DSI_R64(dsi_hw, off) readq_relaxed((dsi_hw)->base + (off))
+#define DSI_W64(dsi_hw, off, val) writeq_relaxed((val), (dsi_hw)->base + (off))
+
+#endif /* _DSI_HW_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
new file mode 100644
index 0000000000000000000000000000000000000000..a7a39e685d4d69d5f636f8251fc49e62fd9fdba3
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -0,0 +1,1998 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+
+#include "dsi_panel.h"
+#include "dsi_ctrl_hw.h"
+
+#define DSI_PANEL_DEFAULT_LABEL  "Default dsi panel"
+
+#define DEFAULT_MDP_TRANSFER_TIME 14000
+
+static int dsi_panel_vreg_get(struct dsi_panel *panel)
+{
+	int rc = 0;
+	int i;
+	struct regulator *vreg = NULL;
+
+	for (i = 0; i < panel->power_info.count; i++) {
+		vreg = devm_regulator_get(panel->parent,
+					  panel->power_info.vregs[i].vreg_name);
+		rc = PTR_RET(vreg);
+		if (rc) {
+			pr_err("failed to get %s regulator\n",
+			       panel->power_info.vregs[i].vreg_name);
+			goto error_put;
+		}
+		panel->power_info.vregs[i].vreg = vreg;
+	}
+
+	return rc;
+error_put:
+	for (i = i - 1; i >= 0; i--) {
+		devm_regulator_put(panel->power_info.vregs[i].vreg);
+		panel->power_info.vregs[i].vreg = NULL;
+	}
+	return rc;
+}
+
+static int dsi_panel_vreg_put(struct dsi_panel *panel)
+{
+	int rc = 0;
+	int i;
+
+	for (i = panel->power_info.count - 1; i >= 0; i--)
+		devm_regulator_put(panel->power_info.vregs[i].vreg);
+
+	return rc;
+}
+
+static int dsi_panel_gpio_request(struct dsi_panel *panel)
+{
+	int rc = 0;
+	struct dsi_panel_reset_config *r_config = &panel->reset_config;
+
+	if (gpio_is_valid(r_config->reset_gpio)) {
+		rc = gpio_request(r_config->reset_gpio, "reset_gpio");
+		if (rc) {
+			pr_err("request for reset_gpio failed, rc=%d\n", rc);
+			goto error;
+		}
+	}
+
+	if (gpio_is_valid(r_config->disp_en_gpio)) {
+		rc = gpio_request(r_config->disp_en_gpio, "disp_en_gpio");
+		if (rc) {
+			pr_err("request for disp_en_gpio failed, rc=%d\n", rc);
+			goto error_release_reset;
+		}
+	}
+
+	if (gpio_is_valid(panel->bl_config.en_gpio)) {
+		rc = gpio_request(panel->bl_config.en_gpio, "bklt_en_gpio");
+		if (rc) {
+			pr_err("request for bklt_en_gpio failed, rc=%d\n", rc);
+			goto error_release_disp_en;
+		}
+	}
+
+	goto error;
+error_release_disp_en:
+	if (gpio_is_valid(r_config->disp_en_gpio))
+		gpio_free(r_config->disp_en_gpio);
+error_release_reset:
+	if (gpio_is_valid(r_config->reset_gpio))
+		gpio_free(r_config->reset_gpio);
+error:
+	return rc;
+}
+
+static int dsi_panel_gpio_release(struct dsi_panel *panel)
+{
+	int rc = 0;
+	struct dsi_panel_reset_config *r_config = &panel->reset_config;
+
+	if (gpio_is_valid(r_config->reset_gpio))
+		gpio_free(r_config->reset_gpio);
+
+	if (gpio_is_valid(r_config->disp_en_gpio))
+		gpio_free(r_config->disp_en_gpio);
+
+	if (gpio_is_valid(panel->bl_config.en_gpio))
+		gpio_free(panel->bl_config.en_gpio);
+
+	return rc;
+}
+
+static int dsi_panel_reset(struct dsi_panel *panel)
+{
+	int rc = 0;
+	struct dsi_panel_reset_config *r_config = &panel->reset_config;
+	int i;
+
+	if (gpio_is_valid(panel->reset_config.disp_en_gpio)) {
+		rc = gpio_direction_output(panel->bl_config.en_gpio, 1);
+		if (rc) {
+			pr_err("unable to set dir for disp gpio rc=%d\n", rc);
+			goto exit;
+		}
+	}
+
+	if (r_config->count) {
+		rc = gpio_direction_output(r_config->reset_gpio,
+			r_config->sequence[0].level);
+		if (rc) {
+			pr_err("unable to set dir for rst gpio rc=%d\n", rc);
+			goto exit;
+		}
+	}
+
+	for (i = 0; i < r_config->count; i++) {
+		gpio_set_value(r_config->reset_gpio,
+			       r_config->sequence[i].level);
+
+
+		if (r_config->sequence[i].sleep_ms)
+			usleep_range(r_config->sequence[i].sleep_ms * 1000,
+				     r_config->sequence[i].sleep_ms * 1000);
+	}
+
+	if (gpio_is_valid(panel->bl_config.en_gpio)) {
+		rc = gpio_direction_output(panel->bl_config.en_gpio, 1);
+		if (rc)
+			pr_err("unable to set dir for bklt gpio rc=%d\n", rc);
+	}
+exit:
+	return rc;
+}
+
+static int dsi_panel_set_pinctrl_state(struct dsi_panel *panel, bool enable)
+{
+	int rc = 0;
+	struct pinctrl_state *state;
+
+	if (enable)
+		state = panel->pinctrl.active;
+	else
+		state = panel->pinctrl.suspend;
+
+	rc = pinctrl_select_state(panel->pinctrl.pinctrl, state);
+	if (rc)
+		pr_err("[%s] failed to set pin state, rc=%d\n", panel->name,
+		       rc);
+
+	return rc;
+}
+
+
+static int dsi_panel_power_on(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	rc = dsi_pwr_enable_regulator(&panel->power_info, true);
+	if (rc) {
+		pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc);
+		goto exit;
+	}
+
+	rc = dsi_panel_set_pinctrl_state(panel, true);
+	if (rc) {
+		pr_err("[%s] failed to set pinctrl, rc=%d\n", panel->name, rc);
+		goto error_disable_vregs;
+	}
+
+	rc = dsi_panel_reset(panel);
+	if (rc) {
+		pr_err("[%s] failed to reset panel, rc=%d\n", panel->name, rc);
+		goto error_disable_gpio;
+	}
+
+	goto exit;
+
+error_disable_gpio:
+	if (gpio_is_valid(panel->reset_config.disp_en_gpio))
+		gpio_set_value(panel->reset_config.disp_en_gpio, 0);
+
+	if (gpio_is_valid(panel->bl_config.en_gpio))
+		gpio_set_value(panel->bl_config.en_gpio, 0);
+
+	(void)dsi_panel_set_pinctrl_state(panel, false);
+
+error_disable_vregs:
+	(void)dsi_pwr_enable_regulator(&panel->power_info, false);
+
+exit:
+	return rc;
+}
+
+static int dsi_panel_power_off(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (gpio_is_valid(panel->reset_config.disp_en_gpio))
+		gpio_set_value(panel->reset_config.disp_en_gpio, 0);
+
+	if (gpio_is_valid(panel->reset_config.reset_gpio))
+		gpio_set_value(panel->reset_config.reset_gpio, 0);
+
+	rc = dsi_panel_set_pinctrl_state(panel, false);
+	if (rc) {
+		pr_err("[%s] failed set pinctrl state, rc=%d\n", panel->name,
+		       rc);
+	}
+
+	rc = dsi_pwr_enable_regulator(&panel->power_info, false);
+	if (rc)
+		pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc);
+
+	return rc;
+}
+static int dsi_panel_tx_cmd_set(struct dsi_panel *panel,
+				enum dsi_cmd_set_type type)
+{
+	int rc = 0, i = 0;
+	ssize_t len;
+	struct dsi_cmd_desc *cmds = panel->cmd_sets[type].cmds;
+	u32 count = panel->cmd_sets[type].count;
+	enum dsi_cmd_set_state state = panel->cmd_sets[type].state;
+	const struct mipi_dsi_host_ops *ops = panel->host->ops;
+
+	if (count == 0) {
+		pr_debug("[%s] No commands to be sent for state(%d)\n",
+			 panel->name, type);
+		goto error;
+	}
+
+	for (i = 0; i < count; i++) {
+		/* TODO:  handle last command */
+		if (state == DSI_CMD_SET_STATE_LP)
+			cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM;
+
+		len = ops->transfer(panel->host, &cmds->msg);
+		if (len < 0) {
+			rc = len;
+			pr_err("failed to set cmds(%d), rc=%d\n", type, rc);
+			goto error;
+		}
+		if (cmds->post_wait_ms)
+			msleep(cmds->post_wait_ms);
+		cmds++;
+	}
+error:
+	return rc;
+}
+
+static int dsi_panel_pinctrl_deinit(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	devm_pinctrl_put(panel->pinctrl.pinctrl);
+
+	return rc;
+}
+
+static int dsi_panel_pinctrl_init(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	/* TODO:  pinctrl is defined in dsi dt node */
+	panel->pinctrl.pinctrl = devm_pinctrl_get(panel->parent);
+	if (IS_ERR_OR_NULL(panel->pinctrl.pinctrl)) {
+		rc = PTR_ERR(panel->pinctrl.pinctrl);
+		pr_err("failed to get pinctrl, rc=%d\n", rc);
+		goto error;
+	}
+
+	panel->pinctrl.active = pinctrl_lookup_state(panel->pinctrl.pinctrl,
+						       "panel_active");
+	if (IS_ERR_OR_NULL(panel->pinctrl.active)) {
+		rc = PTR_ERR(panel->pinctrl.active);
+		pr_err("failed to get pinctrl active state, rc=%d\n", rc);
+		goto error;
+	}
+
+	panel->pinctrl.suspend =
+		pinctrl_lookup_state(panel->pinctrl.pinctrl, "panel_suspend");
+
+	if (IS_ERR_OR_NULL(panel->pinctrl.suspend)) {
+		rc = PTR_ERR(panel->pinctrl.suspend);
+		pr_err("failed to get pinctrl suspend state, rc=%d\n", rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+#ifdef CONFIG_LEDS_TRIGGERS
+static int dsi_panel_led_bl_register(struct dsi_panel *panel,
+				struct dsi_backlight_config *bl)
+{
+	int rc = 0;
+
+	led_trigger_register_simple("bkl-trigger", &bl->wled);
+
+	/* LED APIs don't tell us directly whether a classdev has yet
+	 * been registered to service this trigger. Until classdev is
+	 * registered, calling led_trigger has no effect, and doesn't
+	 * fail. Classdevs are associated with any registered triggers
+	 * when they do register, but that is too late for FBCon.
+	 * Check the cdev list directly and defer if appropriate.
+	 */
+	if (!bl->wled) {
+		pr_err("[%s] backlight registration failed\n", panel->name);
+		rc = -EINVAL;
+	} else {
+		read_lock(&bl->wled->leddev_list_lock);
+		if (list_empty(&bl->wled->led_cdevs))
+			rc = -EPROBE_DEFER;
+		read_unlock(&bl->wled->leddev_list_lock);
+
+		if (rc) {
+			pr_info("[%s] backlight %s not ready, defer probe\n",
+				panel->name, bl->wled->name);
+			led_trigger_unregister_simple(bl->wled);
+		}
+	}
+
+	return rc;
+}
+#else
+static int dsi_panel_led_bl_register(struct dsi_panel *panel,
+				struct dsi_backlight_config *bl)
+{
+	return 0;
+}
+#endif
+
+int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl)
+{
+	int rc = 0;
+	struct dsi_backlight_config *bl = &panel->bl_config;
+
+	switch (bl->type) {
+	case DSI_BACKLIGHT_WLED:
+		led_trigger_event(bl->wled, bl_lvl);
+		break;
+	default:
+		pr_err("Backlight type(%d) not supported\n", bl->type);
+		rc = -ENOTSUPP;
+	}
+
+	return rc;
+}
+
+static int dsi_panel_bl_register(struct dsi_panel *panel)
+{
+	int rc = 0;
+	struct dsi_backlight_config *bl = &panel->bl_config;
+
+	switch (bl->type) {
+	case DSI_BACKLIGHT_WLED:
+		rc = dsi_panel_led_bl_register(panel, bl);
+		break;
+	default:
+		pr_err("Backlight type(%d) not supported\n", bl->type);
+		rc = -ENOTSUPP;
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_bl_unregister(struct dsi_panel *panel)
+{
+	int rc = 0;
+	struct dsi_backlight_config *bl = &panel->bl_config;
+
+	switch (bl->type) {
+	case DSI_BACKLIGHT_WLED:
+		led_trigger_unregister_simple(bl->wled);
+		break;
+	default:
+		pr_err("Backlight type(%d) not supported\n", bl->type);
+		rc = -ENOTSUPP;
+		goto error;
+	}
+
+error:
+	return rc;
+}
+static int dsi_panel_parse_timing(struct dsi_mode_info *mode,
+				  struct device_node *of_node)
+{
+	int rc = 0;
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-framerate",
+				  &mode->refresh_rate);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-panel-framerate, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-width",
+				  &mode->h_active);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-panel-width, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-h-front-porch",
+				  &mode->h_front_porch);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-h-front-porch, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-h-back-porch",
+				  &mode->h_back_porch);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-h-back-porch, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-h-pulse-width",
+				  &mode->h_sync_width);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-h-pulse-width, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-h-sync-skew",
+				  &mode->h_skew);
+	if (rc)
+		pr_err("qcom,mdss-dsi-h-sync-skew is not defined, rc=%d\n", rc);
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-height",
+				  &mode->v_active);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-panel-height, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-v-back-porch",
+				  &mode->v_back_porch);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-v-back-porch, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-v-front-porch",
+				  &mode->v_front_porch);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-v-back-porch, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-v-pulse-width",
+				  &mode->v_sync_width);
+	if (rc) {
+		pr_err("failed to read qcom,mdss-dsi-v-pulse-width, rc=%d\n",
+		       rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_pixel_format(struct dsi_host_common_cfg *host,
+					struct device_node *of_node,
+					const char *name)
+{
+	int rc = 0;
+	u32 bpp = 0;
+	enum dsi_pixel_format fmt;
+	const char *packing;
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-bpp", &bpp);
+	if (rc) {
+		pr_err("[%s] failed to read qcom,mdss-dsi-bpp, rc=%d\n",
+		       name, rc);
+		return rc;
+	}
+
+	switch (bpp) {
+	case 3:
+		fmt = DSI_PIXEL_FORMAT_RGB111;
+		break;
+	case 8:
+		fmt = DSI_PIXEL_FORMAT_RGB332;
+		break;
+	case 12:
+		fmt = DSI_PIXEL_FORMAT_RGB444;
+		break;
+	case 16:
+		fmt = DSI_PIXEL_FORMAT_RGB565;
+		break;
+	case 18:
+		fmt = DSI_PIXEL_FORMAT_RGB666;
+		break;
+	case 24:
+	default:
+		fmt = DSI_PIXEL_FORMAT_RGB888;
+		break;
+	}
+
+	if (fmt == DSI_PIXEL_FORMAT_RGB666) {
+		packing = of_get_property(of_node,
+					  "qcom,mdss-dsi-pixel-packing",
+					  NULL);
+		if (packing && !strcmp(packing, "loose"))
+			fmt = DSI_PIXEL_FORMAT_RGB666_LOOSE;
+	}
+
+	host->dst_format = fmt;
+	return rc;
+}
+
+static int dsi_panel_parse_lane_states(struct dsi_host_common_cfg *host,
+				       struct device_node *of_node,
+				       const char *name)
+{
+	int rc = 0;
+	bool lane_enabled;
+
+	lane_enabled = of_property_read_bool(of_node,
+					    "qcom,mdss-dsi-lane-0-state");
+	host->data_lanes |= (lane_enabled ? DSI_DATA_LANE_0 : 0);
+
+	lane_enabled = of_property_read_bool(of_node,
+					     "qcom,mdss-dsi-lane-1-state");
+	host->data_lanes |= (lane_enabled ? DSI_DATA_LANE_1 : 0);
+
+	lane_enabled = of_property_read_bool(of_node,
+					    "qcom,mdss-dsi-lane-2-state");
+	host->data_lanes |= (lane_enabled ? DSI_DATA_LANE_2 : 0);
+
+	lane_enabled = of_property_read_bool(of_node,
+					     "qcom,mdss-dsi-lane-3-state");
+	host->data_lanes |= (lane_enabled ? DSI_DATA_LANE_3 : 0);
+
+	if (host->data_lanes == 0) {
+		pr_err("[%s] No data lanes are enabled, rc=%d\n", name, rc);
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+
+static int dsi_panel_parse_color_swap(struct dsi_host_common_cfg *host,
+				      struct device_node *of_node,
+				      const char *name)
+{
+	int rc = 0;
+	const char *swap_mode;
+
+	swap_mode = of_get_property(of_node, "qcom,mdss-dsi-color-order", NULL);
+	if (swap_mode) {
+		if (!strcmp(swap_mode, "rgb_swap_rgb")) {
+			host->swap_mode = DSI_COLOR_SWAP_RGB;
+		} else if (!strcmp(swap_mode, "rgb_swap_rbg")) {
+			host->swap_mode = DSI_COLOR_SWAP_RBG;
+		} else if (!strcmp(swap_mode, "rgb_swap_brg")) {
+			host->swap_mode = DSI_COLOR_SWAP_BRG;
+		} else if (!strcmp(swap_mode, "rgb_swap_grb")) {
+			host->swap_mode = DSI_COLOR_SWAP_GRB;
+		} else if (!strcmp(swap_mode, "rgb_swap_gbr")) {
+			host->swap_mode = DSI_COLOR_SWAP_GBR;
+		} else {
+			pr_err("[%s] Unrecognized color order-%s\n",
+			       name, swap_mode);
+			rc = -EINVAL;
+		}
+	} else {
+		pr_debug("[%s] Falling back to default color order\n", name);
+		host->swap_mode = DSI_COLOR_SWAP_RGB;
+	}
+
+	/* bit swap on color channel is not defined in dt */
+	host->bit_swap_red = false;
+	host->bit_swap_green = false;
+	host->bit_swap_blue = false;
+	return rc;
+}
+
+static int dsi_panel_parse_triggers(struct dsi_host_common_cfg *host,
+				    struct device_node *of_node,
+				    const char *name)
+{
+	const char *trig;
+	int rc = 0;
+
+	trig = of_get_property(of_node, "qcom,mdss-dsi-mdp-trigger", NULL);
+	if (trig) {
+		if (!strcmp(trig, "none")) {
+			host->mdp_cmd_trigger = DSI_TRIGGER_NONE;
+		} else if (!strcmp(trig, "trigger_te")) {
+			host->mdp_cmd_trigger = DSI_TRIGGER_TE;
+		} else if (!strcmp(trig, "trigger_sw")) {
+			host->mdp_cmd_trigger = DSI_TRIGGER_SW;
+		} else if (!strcmp(trig, "trigger_sw_te")) {
+			host->mdp_cmd_trigger = DSI_TRIGGER_SW_TE;
+		} else {
+			pr_err("[%s] Unrecognized mdp trigger type (%s)\n",
+			       name, trig);
+			rc = -EINVAL;
+		}
+
+	} else {
+		pr_debug("[%s] Falling back to default MDP trigger\n",
+			 name);
+		host->mdp_cmd_trigger = DSI_TRIGGER_SW;
+	}
+
+	trig = of_get_property(of_node, "qcom,mdss-dsi-dma-trigger", NULL);
+	if (trig) {
+		if (!strcmp(trig, "none")) {
+			host->dma_cmd_trigger = DSI_TRIGGER_NONE;
+		} else if (!strcmp(trig, "trigger_te")) {
+			host->dma_cmd_trigger = DSI_TRIGGER_TE;
+		} else if (!strcmp(trig, "trigger_sw")) {
+			host->dma_cmd_trigger = DSI_TRIGGER_SW;
+		} else if (!strcmp(trig, "trigger_sw_seof")) {
+			host->dma_cmd_trigger = DSI_TRIGGER_SW_SEOF;
+		} else if (!strcmp(trig, "trigger_sw_te")) {
+			host->dma_cmd_trigger = DSI_TRIGGER_SW_TE;
+		} else {
+			pr_err("[%s] Unrecognized mdp trigger type (%s)\n",
+			       name, trig);
+			rc = -EINVAL;
+		}
+
+	} else {
+		pr_debug("[%s] Falling back to default MDP trigger\n", name);
+		host->dma_cmd_trigger = DSI_TRIGGER_SW;
+	}
+
+
+	return rc;
+}
+
+static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host,
+					    struct device_node *of_node,
+					    const char *name)
+{
+	u32 val = 0;
+	int rc = 0;
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-t-clk-post", &val);
+	if (rc) {
+		pr_debug("[%s] Fallback to default t_clk_post value\n", name);
+		host->t_clk_post = 0x03;
+	} else {
+		host->t_clk_post = val;
+		pr_debug("[%s] t_clk_post = %d\n", name, val);
+	}
+
+	val = 0;
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-t-clk-pre", &val);
+	if (rc) {
+		pr_debug("[%s] Fallback to default t_clk_pre value\n", name);
+		host->t_clk_pre = 0x24;
+	} else {
+		host->t_clk_pre = val;
+		pr_debug("[%s] t_clk_pre = %d\n", name, val);
+	}
+
+	host->ignore_rx_eot = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-rx-eot-ignore");
+
+	host->append_tx_eot = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-tx-eot-append");
+
+	return 0;
+}
+
+static int dsi_panel_parse_host_config(struct dsi_panel *panel,
+				       struct device_node *of_node)
+{
+	int rc = 0;
+
+	rc = dsi_panel_parse_pixel_format(&panel->host_config, of_node,
+					  panel->name);
+	if (rc) {
+		pr_err("[%s] failed to get pixel format, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_lane_states(&panel->host_config, of_node,
+					 panel->name);
+	if (rc) {
+		pr_err("[%s] failed to parse lane states, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_color_swap(&panel->host_config, of_node,
+					panel->name);
+	if (rc) {
+		pr_err("[%s] failed to parse color swap config, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_triggers(&panel->host_config, of_node,
+				      panel->name);
+	if (rc) {
+		pr_err("[%s] failed to parse triggers, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_misc_host_config(&panel->host_config, of_node,
+					      panel->name);
+	if (rc) {
+		pr_err("[%s] failed to parse misc host config, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_dfps_caps(struct dsi_dfps_capabilities *dfps_caps,
+				     struct device_node *of_node,
+				     const char *name)
+{
+	int rc = 0;
+	bool supported = false;
+	const char *type;
+	u32 val = 0;
+
+	supported = of_property_read_bool(of_node,
+					"qcom,mdss-dsi-pan-enable-dynamic-fps");
+
+	if (!supported) {
+		pr_debug("[%s] DFPS is not supported\n", name);
+		dfps_caps->dfps_support = false;
+	} else {
+
+		type = of_get_property(of_node,
+				       "qcom,mdss-dsi-pan-fps-update",
+				       NULL);
+		if (!type) {
+			pr_err("[%s] dfps type not defined\n", name);
+			rc = -EINVAL;
+			goto error;
+		} else if (!strcmp(type, "dfps_suspend_resume_mode")) {
+			dfps_caps->type = DSI_DFPS_SUSPEND_RESUME;
+		} else if (!strcmp(type, "dfps_immediate_clk_mode")) {
+			dfps_caps->type = DSI_DFPS_IMMEDIATE_CLK;
+		} else if (!strcmp(type, "dfps_immediate_porch_mode_hfp")) {
+			dfps_caps->type = DSI_DFPS_IMMEDIATE_HFP;
+		} else if (!strcmp(type, "dfps_immediate_porch_mode_vfp")) {
+			dfps_caps->type = DSI_DFPS_IMMEDIATE_VFP;
+		} else {
+			pr_err("[%s] dfps type is not recognized\n", name);
+			rc = -EINVAL;
+			goto error;
+		}
+
+		rc = of_property_read_u32(of_node,
+					  "qcom,mdss-dsi-min-refresh-rate",
+					  &val);
+		if (rc) {
+			pr_err("[%s] Min refresh rate is not defined\n", name);
+			rc = -EINVAL;
+			goto error;
+		}
+		dfps_caps->min_refresh_rate = val;
+
+		rc = of_property_read_u32(of_node,
+					  "qcom,mdss-dsi-max-refresh-rate",
+					  &val);
+		if (rc) {
+			pr_debug("[%s] Using default refresh rate\n", name);
+			rc = of_property_read_u32(of_node,
+						"qcom,mdss-dsi-panel-framerate",
+						&val);
+			if (rc) {
+				pr_err("[%s] max refresh rate is not defined\n",
+				       name);
+				rc = -EINVAL;
+				goto error;
+			}
+		}
+		dfps_caps->max_refresh_rate = val;
+
+		if (dfps_caps->min_refresh_rate > dfps_caps->max_refresh_rate) {
+			pr_err("[%s] min rate > max rate\n", name);
+			rc = -EINVAL;
+		}
+
+		pr_debug("[%s] DFPS is supported %d-%d, mode %d\n", name,
+				dfps_caps->min_refresh_rate,
+				dfps_caps->max_refresh_rate,
+				dfps_caps->type);
+		dfps_caps->dfps_support = true;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_video_host_config(struct dsi_video_engine_cfg *cfg,
+					     struct device_node *of_node,
+					     const char *name)
+{
+	int rc = 0;
+	const char *traffic_mode;
+	u32 vc_id = 0;
+	u32 val = 0;
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-h-sync-pulse", &val);
+	if (rc) {
+		pr_debug("[%s] fallback to default h-sync-pulse\n", name);
+		cfg->pulse_mode_hsa_he = false;
+	} else if (val == 1) {
+		cfg->pulse_mode_hsa_he = true;
+	} else if (val == 0) {
+		cfg->pulse_mode_hsa_he = false;
+	} else {
+		pr_err("[%s] Unrecognized value for mdss-dsi-h-sync-pulse\n",
+		       name);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	cfg->hfp_lp11_en = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-hfp-power-mode");
+
+	cfg->hbp_lp11_en = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-hbp-power-mode");
+
+	cfg->hsa_lp11_en = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-hsa-power-mode");
+
+	cfg->last_line_interleave_en = of_property_read_bool(of_node,
+					"qcom,mdss-dsi-last-line-interleave");
+
+	cfg->eof_bllp_lp11_en = of_property_read_bool(of_node,
+					"qcom,mdss-dsi-bllp-eof-power-mode");
+
+	cfg->bllp_lp11_en = of_property_read_bool(of_node,
+					"qcom,mdss-dsi-bllp-power-mode");
+
+	traffic_mode = of_get_property(of_node,
+				       "qcom,mdss-dsi-traffic-mode",
+				       NULL);
+	if (!traffic_mode) {
+		pr_debug("[%s] Falling back to default traffic mode\n", name);
+		cfg->traffic_mode = DSI_VIDEO_TRAFFIC_SYNC_PULSES;
+	} else if (!strcmp(traffic_mode, "non_burst_sync_pulse")) {
+		cfg->traffic_mode = DSI_VIDEO_TRAFFIC_SYNC_PULSES;
+	} else if (!strcmp(traffic_mode, "non_burst_sync_event")) {
+		cfg->traffic_mode = DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
+	} else if (!strcmp(traffic_mode, "burst_mode")) {
+		cfg->traffic_mode = DSI_VIDEO_TRAFFIC_BURST_MODE;
+	} else {
+		pr_err("[%s] Unrecognized traffic mode-%s\n", name,
+		       traffic_mode);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-virtual-channel-id",
+				  &vc_id);
+	if (rc) {
+		pr_debug("[%s] Fallback to default vc id\n", name);
+		cfg->vc_id = 0;
+	} else {
+		cfg->vc_id = vc_id;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_cmd_host_config(struct dsi_cmd_engine_cfg *cfg,
+					   struct device_node *of_node,
+					   const char *name)
+{
+	u32 val = 0;
+	int rc = 0;
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-wr-mem-start", &val);
+	if (rc) {
+		pr_debug("[%s] Fallback to default wr-mem-start\n", name);
+		cfg->wr_mem_start = 0x2C;
+	} else {
+		cfg->wr_mem_start = val;
+	}
+
+	val = 0;
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-wr-mem-continue",
+				  &val);
+	if (rc) {
+		pr_debug("[%s] Fallback to default wr-mem-continue\n", name);
+		cfg->wr_mem_continue = 0x3C;
+	} else {
+		cfg->wr_mem_continue = val;
+	}
+
+	/* TODO:  fix following */
+	cfg->max_cmd_packets_interleave = 0;
+
+	val = 0;
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-te-dcs-command",
+				  &val);
+	if (rc) {
+		pr_debug("[%s] fallback to default te-dcs-cmd\n", name);
+		cfg->insert_dcs_command = true;
+	} else if (val == 1) {
+		cfg->insert_dcs_command = true;
+	} else if (val == 0) {
+		cfg->insert_dcs_command = false;
+	} else {
+		pr_err("[%s] Unrecognized value for mdss-dsi-te-dcs-command\n",
+		       name);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	if (of_property_read_u32(of_node, "qcom,mdss-mdp-transfer-time-us",
+				&val)) {
+		pr_debug("[%s] Fallback to default transfer-time-us\n", name);
+		cfg->mdp_transfer_time_us = DEFAULT_MDP_TRANSFER_TIME;
+	} else {
+		cfg->mdp_transfer_time_us = val;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_panel_mode(struct dsi_panel *panel,
+				      struct device_node *of_node)
+{
+	int rc = 0;
+	enum dsi_op_mode panel_mode;
+	const char *mode;
+
+	mode = of_get_property(of_node, "qcom,mdss-dsi-panel-type", NULL);
+	if (!mode) {
+		pr_debug("[%s] Fallback to default panel mode\n", panel->name);
+		panel_mode = DSI_OP_VIDEO_MODE;
+	} else if (!strcmp(mode, "dsi_video_mode")) {
+		panel_mode = DSI_OP_VIDEO_MODE;
+	} else if (!strcmp(mode, "dsi_cmd_mode")) {
+		panel_mode = DSI_OP_CMD_MODE;
+	} else {
+		pr_err("[%s] Unrecognized panel type-%s\n", panel->name, mode);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	if (panel_mode == DSI_OP_VIDEO_MODE) {
+		rc = dsi_panel_parse_video_host_config(&panel->video_config,
+						       of_node,
+						       panel->name);
+		if (rc) {
+			pr_err("[%s] Failed to parse video host cfg, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+
+	if (panel_mode == DSI_OP_CMD_MODE) {
+		rc = dsi_panel_parse_cmd_host_config(&panel->cmd_config,
+						     of_node,
+						     panel->name);
+		if (rc) {
+			pr_err("[%s] Failed to parse cmd host config, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+
+	panel->mode.panel_mode = panel_mode;
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_phy_props(struct dsi_panel_phy_props *props,
+				     struct device_node *of_node,
+				     const char *name)
+{
+	int rc = 0;
+	u32 val = 0;
+	const char *str;
+
+	rc = of_property_read_u32(of_node,
+				  "qcom,mdss-pan-physical-width-dimension",
+				  &val);
+	if (rc) {
+		pr_debug("[%s] Physical panel width is not defined\n", name);
+		props->panel_width_mm = 0;
+		rc = 0;
+	} else {
+		props->panel_width_mm = val;
+	}
+
+	rc = of_property_read_u32(of_node,
+				  "qcom,mdss-pan-physical-height-dimension",
+				  &val);
+	if (rc) {
+		pr_debug("[%s] Physical panel height is not defined\n", name);
+		props->panel_height_mm = 0;
+		rc = 0;
+	} else {
+		props->panel_height_mm = val;
+	}
+
+	str = of_get_property(of_node, "qcom,mdss-dsi-panel-orientation", NULL);
+	if (!str) {
+		props->rotation = DSI_PANEL_ROTATE_NONE;
+	} else if (!strcmp(str, "180")) {
+		props->rotation = DSI_PANEL_ROTATE_HV_FLIP;
+	} else if (!strcmp(str, "hflip")) {
+		props->rotation = DSI_PANEL_ROTATE_H_FLIP;
+	} else if (!strcmp(str, "vflip")) {
+		props->rotation = DSI_PANEL_ROTATE_V_FLIP;
+	} else {
+		pr_err("[%s] Unrecognized panel rotation-%s\n", name, str);
+		rc = -EINVAL;
+		goto error;
+	}
+error:
+	return rc;
+}
+const char *cmd_set_prop_map[DSI_CMD_SET_MAX] = {
+	"qcom,mdss-dsi-pre-on-command",
+	"qcom,mdss-dsi-on-command",
+	"qcom,mdss-dsi-post-panel-on-command",
+	"qcom,mdss-dsi-pre-off-command",
+	"qcom,mdss-dsi-off-command",
+	"qcom,mdss-dsi-post-off-command",
+	"qcom,mdss-dsi-pre-res-switch",
+	"qcom,mdss-dsi-res-switch",
+	"qcom,mdss-dsi-post-res-switch",
+	"qcom,cmd-to-video-mode-switch-commands",
+	"qcom,cmd-to-video-mode-post-switch-commands",
+	"qcom,video-to-cmd-mode-switch-commands",
+	"qcom,video-to-cmd-mode-post-switch-commands",
+	"qcom,mdss-dsi-panel-status-command",
+};
+
+const char *cmd_set_state_map[DSI_CMD_SET_MAX] = {
+	"qcom,mdss-dsi-pre-on-command-state",
+	"qcom,mdss-dsi-on-command-state",
+	"qcom,mdss-dsi-post-on-command-state",
+	"qcom,mdss-dsi-pre-off-command-state",
+	"qcom,mdss-dsi-off-command-state",
+	"qcom,mdss-dsi-post-off-command-state",
+	"qcom,mdss-dsi-pre-res-switch-state",
+	"qcom,mdss-dsi-res-switch-state",
+	"qcom,mdss-dsi-post-res-switch-state",
+	"qcom,cmd-to-video-mode-switch-commands-state",
+	"qcom,cmd-to-video-mode-post-switch-commands-state",
+	"qcom,video-to-cmd-mode-switch-commands-state",
+	"qcom,video-to-cmd-mode-post-switch-commands-state",
+	"qcom,mdss-dsi-panel-status-command-state",
+};
+
+static int dsi_panel_get_cmd_pkt_count(const char *data, u32 length, u32 *cnt)
+{
+	const u32 cmd_set_min_size = 7;
+	u32 count = 0;
+	u32 packet_length;
+	u32 tmp;
+
+	while (length >= cmd_set_min_size) {
+		packet_length = cmd_set_min_size;
+		tmp = ((data[5] << 8) | (data[6]));
+		packet_length += tmp;
+		if (packet_length > length) {
+			pr_err("FORMAT ERROR\n");
+			return -EINVAL;
+		}
+		length -= packet_length;
+		data += packet_length;
+		count++;
+	};
+
+	*cnt = count;
+	return 0;
+}
+
+static int dsi_panel_create_cmd_packets(const char *data,
+					u32 length,
+					u32 count,
+					struct dsi_cmd_desc *cmd)
+{
+	int rc = 0;
+	int i, j;
+	u8 *payload;
+
+	for (i = 0; i < count; i++) {
+		u32 size;
+
+		cmd[i].msg.type = data[0];
+		cmd[i].last_command = (data[1] == 1 ? true : false);
+		cmd[i].msg.channel = data[2];
+		cmd[i].msg.flags |= (data[3] == 1 ? MIPI_DSI_MSG_REQ_ACK : 0);
+		cmd[i].post_wait_ms = data[4];
+		cmd[i].msg.tx_len = ((data[5] << 8) | (data[6]));
+
+		size = cmd[i].msg.tx_len * sizeof(u8);
+
+		payload = kzalloc(size, GFP_KERNEL);
+		if (!payload) {
+			rc = -ENOMEM;
+			goto error_free_payloads;
+		}
+
+		for (j = 0; j < cmd[i].msg.tx_len; j++)
+			payload[j] = data[7 + j];
+
+		cmd[i].msg.tx_buf = payload;
+		data += (7 + cmd[i].msg.tx_len);
+	}
+
+	return rc;
+error_free_payloads:
+	for (i = i - 1; i >= 0; i--) {
+		cmd--;
+		kfree(cmd->msg.tx_buf);
+	}
+
+	return rc;
+}
+
+static void dsi_panel_destroy_cmd_packets(struct dsi_panel_cmd_set *set)
+{
+	u32 i = 0;
+	struct dsi_cmd_desc *cmd;
+
+	for (i = 0; i < set->count; i++) {
+		cmd = &set->cmds[i];
+		kfree(cmd->msg.tx_buf);
+	}
+
+	kfree(set->cmds);
+}
+
+static int dsi_panel_parse_cmd_sets_sub(struct dsi_panel_cmd_set *cmd,
+					enum dsi_cmd_set_type type,
+					struct device_node *of_node)
+{
+	int rc = 0;
+	u32 length = 0;
+	u32 size;
+	const char *data;
+	const char *state;
+	u32 packet_count = 0;
+
+	data = of_get_property(of_node, cmd_set_prop_map[type], &length);
+	if (!data) {
+		pr_err("%s commands not defined\n", cmd_set_prop_map[type]);
+		rc = -ENOTSUPP;
+		goto error;
+	}
+
+	rc = dsi_panel_get_cmd_pkt_count(data, length, &packet_count);
+	if (rc) {
+		pr_err("commands failed, rc=%d\n", rc);
+		goto error;
+	}
+	pr_debug("[%s] packet-count=%d, %d\n", cmd_set_prop_map[type],
+		 packet_count, length);
+
+	size = packet_count * sizeof(*cmd->cmds);
+	cmd->cmds = kzalloc(size, GFP_KERNEL);
+	if (!cmd->cmds) {
+		rc = -ENOMEM;
+		goto error;
+	}
+	cmd->count = packet_count;
+
+	rc = dsi_panel_create_cmd_packets(data, length, packet_count,
+					  cmd->cmds);
+	if (rc) {
+		pr_err("Failed to create cmd packets, rc=%d\n", rc);
+		goto error_free_mem;
+	}
+
+	state = of_get_property(of_node, cmd_set_state_map[type], NULL);
+	if (!state || !strcmp(state, "dsi_lp_mode")) {
+		cmd->state = DSI_CMD_SET_STATE_LP;
+	} else if (!strcmp(state, "dsi_hs_mode")) {
+		cmd->state = DSI_CMD_SET_STATE_HS;
+	} else {
+		pr_err("[%s] Command state unrecognized-%s\n",
+		       cmd_set_state_map[type], state);
+		goto error_free_mem;
+	}
+
+	return rc;
+error_free_mem:
+	kfree(cmd->cmds);
+	cmd->cmds = NULL;
+error:
+	return rc;
+
+}
+
+static int dsi_panel_parse_cmd_sets(struct dsi_panel *panel,
+				    struct device_node *of_node)
+{
+	int rc = 0;
+	struct dsi_panel_cmd_set *set;
+	u32 i;
+
+	for (i = DSI_CMD_SET_PRE_ON; i < DSI_CMD_SET_MAX; i++) {
+		set = &panel->cmd_sets[i];
+		set->type = i;
+		rc = dsi_panel_parse_cmd_sets_sub(set, i, of_node);
+		if (rc)
+			pr_err("[%s] failed to parse set %d\n", panel->name, i);
+	}
+
+	rc = 0;
+	return rc;
+}
+
+static int dsi_panel_parse_reset_sequence(struct dsi_panel *panel,
+				      struct device_node *of_node)
+{
+	int rc = 0;
+	int i;
+	u32 length = 0;
+	u32 count = 0;
+	u32 size = 0;
+	u32 *arr_32 = NULL;
+	const u32 *arr;
+	struct dsi_reset_seq *seq;
+
+	arr = of_get_property(of_node, "qcom,mdss-dsi-reset-sequence", &length);
+	if (!arr) {
+		pr_err("[%s] dsi-reset-sequence not found\n", panel->name);
+		rc = -EINVAL;
+		goto error;
+	}
+	if (length & 0x1) {
+		pr_err("[%s] syntax error for dsi-reset-sequence\n",
+		       panel->name);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	pr_err("RESET SEQ LENGTH = %d\n", length);
+	length = length / sizeof(u32);
+
+	size = length * sizeof(u32);
+
+	arr_32 = kzalloc(size, GFP_KERNEL);
+	if (!arr_32) {
+		rc = -ENOMEM;
+		goto error;
+	}
+
+	rc = of_property_read_u32_array(of_node, "qcom,mdss-dsi-reset-sequence",
+					arr_32, length);
+	if (rc) {
+		pr_err("[%s] cannot read dso-reset-seqience\n", panel->name);
+		goto error_free_arr_32;
+	}
+
+	count = length / 2;
+	size = count * sizeof(*seq);
+	seq = kzalloc(size, GFP_KERNEL);
+	if (!seq) {
+		rc = -ENOMEM;
+		goto error_free_arr_32;
+	}
+
+	panel->reset_config.sequence = seq;
+	panel->reset_config.count = count;
+
+	for (i = 0; i < length; i += 2) {
+		seq->level = arr_32[i];
+		seq->sleep_ms = arr_32[i + 1];
+		seq++;
+	}
+
+
+error_free_arr_32:
+	kfree(arr_32);
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_power_cfg(struct device *parent,
+				     struct dsi_panel *panel,
+				     struct device_node *of_node)
+{
+	int rc = 0;
+
+	rc = dsi_clk_pwr_of_get_vreg_data(of_node,
+					  &panel->power_info,
+					  "qcom,panel-supply-entries");
+	if (rc) {
+		pr_err("[%s] failed to parse vregs\n", panel->name);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_gpios(struct dsi_panel *panel,
+				 struct device_node *of_node)
+{
+	int rc = 0;
+
+	panel->reset_config.reset_gpio = of_get_named_gpio(of_node,
+					      "qcom,platform-reset-gpio",
+					      0);
+	if (!gpio_is_valid(panel->reset_config.reset_gpio)) {
+		pr_err("[%s] failed get reset gpio, rc=%d\n", panel->name, rc);
+		rc = -EINVAL;
+		goto error;
+	}
+
+	panel->reset_config.disp_en_gpio = of_get_named_gpio(of_node,
+						"qcom,5v-boost-gpio",
+						0);
+	if (!gpio_is_valid(panel->reset_config.disp_en_gpio)) {
+		pr_debug("[%s] 5v-boot-gpio is not set, rc=%d\n",
+			 panel->name, rc);
+		panel->reset_config.disp_en_gpio = of_get_named_gpio(of_node,
+							"qcom,platform-en-gpio",
+							0);
+		if (!gpio_is_valid(panel->reset_config.disp_en_gpio)) {
+			pr_debug("[%s] platform-en-gpio is not set, rc=%d\n",
+				 panel->name, rc);
+		}
+	}
+
+	/* TODO:  release memory */
+	rc = dsi_panel_parse_reset_sequence(panel, of_node);
+	if (rc) {
+		pr_err("[%s] failed to parse reset sequence, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_bl_pwm_config(struct dsi_backlight_config *config,
+					 struct device_node *of_node)
+{
+	int rc = 0;
+	u32 val;
+
+	rc = of_property_read_u32(of_node, "qcom,dsi-bl-pmic-bank-select",
+				  &val);
+	if (rc) {
+		pr_err("bl-pmic-bank-select is not defined, rc=%d\n", rc);
+		goto error;
+	}
+	config->pwm_pmic_bank = val;
+
+	rc = of_property_read_u32(of_node, "qcom,dsi-bl-pmic-pwm-frequency",
+				  &val);
+	if (rc) {
+		pr_err("bl-pmic-bank-select is not defined, rc=%d\n", rc);
+		goto error;
+	}
+	config->pwm_period_usecs = val;
+
+	config->pwm_pmi_control = of_property_read_bool(of_node,
+						"qcom,mdss-dsi-bl-pwm-pmi");
+
+	config->pwm_gpio = of_get_named_gpio(of_node,
+					     "qcom,mdss-dsi-pwm-gpio",
+					     0);
+	if (!gpio_is_valid(config->pwm_gpio)) {
+		pr_err("pwm gpio is invalid\n");
+		rc = -EINVAL;
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_panel_parse_bl_config(struct dsi_panel *panel,
+				     struct device_node *of_node)
+{
+	int rc = 0;
+	const char *bl_type;
+	u32 val = 0;
+
+	bl_type = of_get_property(of_node,
+				  "qcom,mdss-dsi-bl-pmic-control-type",
+				  NULL);
+	if (!bl_type) {
+		panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
+	} else if (!strcmp(bl_type, "bl_ctrl_pwm")) {
+		panel->bl_config.type = DSI_BACKLIGHT_PWM;
+	} else if (!strcmp(bl_type, "bl_ctrl_wled")) {
+		panel->bl_config.type = DSI_BACKLIGHT_WLED;
+	} else if (!strcmp(bl_type, "bl_ctrl_dcs")) {
+		panel->bl_config.type = DSI_BACKLIGHT_DCS;
+	} else {
+		pr_debug("[%s] bl-pmic-control-type unknown-%s\n",
+			 panel->name, bl_type);
+		panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-bl-min-level", &val);
+	if (rc) {
+		pr_debug("[%s] bl-min-level unspecified, defaulting to zero\n",
+			 panel->name);
+		panel->bl_config.bl_min_level = 0;
+	} else {
+		panel->bl_config.bl_min_level = val;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-bl-max-level", &val);
+	if (rc) {
+		pr_debug("[%s] bl-max-level unspecified, defaulting to max level\n",
+			 panel->name);
+		panel->bl_config.bl_max_level = MAX_BL_LEVEL;
+	} else {
+		panel->bl_config.bl_max_level = val;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-brightness-max-level",
+		&val);
+	if (rc) {
+		pr_debug("[%s] brigheness-max-level unspecified, defaulting to 255\n",
+			 panel->name);
+		panel->bl_config.brightness_max_level = 255;
+	} else {
+		panel->bl_config.brightness_max_level = val;
+	}
+
+	if (panel->bl_config.type == DSI_BACKLIGHT_PWM) {
+		rc = dsi_panel_parse_bl_pwm_config(&panel->bl_config, of_node);
+		if (rc) {
+			pr_err("[%s] failed to parse pwm config, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+
+	panel->bl_config.en_gpio = of_get_named_gpio(of_node,
+					      "qcom,platform-bklight-en-gpio",
+					      0);
+	if (!gpio_is_valid(panel->bl_config.en_gpio)) {
+		pr_err("[%s] failed get bklt gpio, rc=%d\n", panel->name, rc);
+		rc = -EINVAL;
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+struct dsi_panel *dsi_panel_get(struct device *parent,
+				struct device_node *of_node)
+{
+	struct dsi_panel *panel;
+	int rc = 0;
+
+	panel = kzalloc(sizeof(*panel), GFP_KERNEL);
+	if (!panel)
+		return ERR_PTR(-ENOMEM);
+
+	panel->name = of_get_property(of_node, "qcom,mdss-dsi-panel-name",
+				      NULL);
+	if (!panel->name)
+		panel->name = DSI_PANEL_DEFAULT_LABEL;
+
+	rc = dsi_panel_parse_timing(&panel->mode.timing, of_node);
+	if (rc) {
+		pr_err("failed to parse panel timing, rc=%d\n", rc);
+		goto error;
+	}
+
+	panel->mode.pixel_clk_khz = (DSI_H_TOTAL(&panel->mode.timing) *
+				    DSI_V_TOTAL(&panel->mode.timing) *
+				    panel->mode.timing.refresh_rate) / 1000;
+	rc = dsi_panel_parse_host_config(panel, of_node);
+	if (rc) {
+		pr_err("failed to parse host configuration, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_panel_mode(panel, of_node);
+	if (rc) {
+		pr_err("failed to parse panel mode configuration, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_dfps_caps(&panel->dfps_caps, of_node, panel->name);
+	if (rc)
+		pr_err("failed to parse dfps configuration, rc=%d\n", rc);
+
+	rc = dsi_panel_parse_phy_props(&panel->phy_props, of_node, panel->name);
+	if (rc) {
+		pr_err("failed to parse panel physical dimension, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_cmd_sets(panel, of_node);
+	if (rc) {
+		pr_err("failed to parse command sets, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_panel_parse_power_cfg(parent, panel, of_node);
+	if (rc)
+		pr_err("failed to parse power config, rc=%d\n", rc);
+
+	rc = dsi_panel_parse_gpios(panel, of_node);
+	if (rc)
+		pr_err("failed to parse panel gpios, rc=%d\n", rc);
+
+	rc = dsi_panel_parse_bl_config(panel, of_node);
+	if (rc)
+		pr_err("failed to parse backlight config, rc=%d\n", rc);
+
+	panel->panel_of_node = of_node;
+	drm_panel_init(&panel->drm_panel);
+	mutex_init(&panel->panel_lock);
+	panel->parent = parent;
+	return panel;
+error:
+	kfree(panel);
+	return ERR_PTR(rc);
+}
+
+void dsi_panel_put(struct dsi_panel *panel)
+{
+	u32 i;
+
+	for (i = 0; i < DSI_CMD_SET_MAX; i++)
+		dsi_panel_destroy_cmd_packets(&panel->cmd_sets[i]);
+
+	/* TODO:  more free */
+	kfree(panel);
+}
+
+int dsi_panel_drv_init(struct dsi_panel *panel,
+		       struct mipi_dsi_host *host)
+{
+	int rc = 0;
+	struct mipi_dsi_device *dev;
+
+	if (!panel || !host) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	dev = &panel->mipi_device;
+
+	dev->host = host;
+	/*
+	 * We dont have device structure since panel is not a device node.
+	 * When using drm panel framework, the device is probed when the host is
+	 * create.
+	 */
+	dev->channel = 0;
+	dev->lanes = 4;
+
+	panel->host = host;
+	rc = dsi_panel_vreg_get(panel);
+	if (rc) {
+		pr_err("[%s] Failed to get panel regulators, rc=%d\n",
+		       panel->name, rc);
+		goto exit;
+	}
+
+	rc = dsi_panel_pinctrl_init(panel);
+	if (rc) {
+		pr_err("[%s] failed to init pinctrl, rc=%d\n", panel->name, rc);
+		goto error_vreg_put;
+	}
+
+	rc = dsi_panel_gpio_request(panel);
+	if (rc) {
+		pr_err("[%s] failed to request gpios, rc=%d\n", panel->name,
+		       rc);
+		goto error_pinctrl_deinit;
+	}
+
+	rc = dsi_panel_bl_register(panel);
+	if (rc) {
+		if (rc != -EPROBE_DEFER)
+			pr_err("[%s] failed to register backlight, rc=%d\n",
+			       panel->name, rc);
+		goto error_gpio_release;
+	}
+
+	goto exit;
+
+error_gpio_release:
+	(void)dsi_panel_gpio_release(panel);
+error_pinctrl_deinit:
+	(void)dsi_panel_pinctrl_deinit(panel);
+error_vreg_put:
+	(void)dsi_panel_vreg_put(panel);
+exit:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_drv_deinit(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_bl_unregister(panel);
+	if (rc)
+		pr_err("[%s] failed to unregister backlight, rc=%d\n",
+		       panel->name, rc);
+
+	rc = dsi_panel_gpio_release(panel);
+	if (rc)
+		pr_err("[%s] failed to release gpios, rc=%d\n", panel->name,
+		       rc);
+
+	rc = dsi_panel_pinctrl_deinit(panel);
+	if (rc)
+		pr_err("[%s] failed to deinit gpios, rc=%d\n", panel->name,
+		       rc);
+
+	rc = dsi_panel_vreg_put(panel);
+	if (rc)
+		pr_err("[%s] failed to put regs, rc=%d\n", panel->name, rc);
+
+	panel->host = NULL;
+	memset(&panel->mipi_device, 0x0, sizeof(panel->mipi_device));
+
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_validate_mode(struct dsi_panel *panel,
+			    struct dsi_display_mode *mode)
+{
+	return 0;
+}
+
+int dsi_panel_get_mode_count(struct dsi_panel *panel, u32 *count)
+{
+	int rc = 0;
+
+	if (!panel || !count) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+	/* TODO:  DT format has not been decided for multiple modes. */
+	*count = 1;
+
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_get_phy_props(struct dsi_panel *panel,
+			    struct dsi_panel_phy_props *phy_props)
+{
+	int rc = 0;
+
+	if (!panel || !phy_props) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	memcpy(phy_props, &panel->phy_props, sizeof(*phy_props));
+
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_get_dfps_caps(struct dsi_panel *panel,
+			    struct dsi_dfps_capabilities *dfps_caps)
+{
+	int rc = 0;
+
+	if (!panel || !dfps_caps) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	memcpy(dfps_caps, &panel->dfps_caps, sizeof(*dfps_caps));
+
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_get_mode(struct dsi_panel *panel,
+			u32 index,
+			struct dsi_display_mode *mode)
+{
+	int rc = 0;
+
+	if (!panel || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+	if (index != 0)
+		rc = -ENOTSUPP; /* TODO: Support more than one mode */
+	else
+		memcpy(mode, &panel->mode, sizeof(*mode));
+
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_get_host_cfg_for_mode(struct dsi_panel *panel,
+				    struct dsi_display_mode *mode,
+				    struct dsi_host_config *config)
+{
+	int rc = 0;
+
+	if (!panel || !mode || !config) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	config->panel_mode = panel->mode.panel_mode;
+	memcpy(&config->common_config, &panel->host_config,
+	       sizeof(config->common_config));
+
+	if (mode->panel_mode == DSI_OP_VIDEO_MODE) {
+		memcpy(&config->u.video_engine, &panel->video_config,
+		       sizeof(config->u.video_engine));
+	} else {
+		memcpy(&config->u.cmd_engine, &panel->cmd_config,
+		       sizeof(config->u.cmd_engine));
+	}
+
+	memcpy(&config->video_timing, &mode->timing,
+	       sizeof(config->video_timing));
+
+	config->esc_clk_rate_hz = 19200000;
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_pre_prepare(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	/* If LP11_INIT is set, panel will be powered up during prepare() */
+	if (panel->lp11_init)
+		goto error;
+
+	rc = dsi_panel_power_on(panel);
+	if (rc) {
+		pr_err("[%s] Panel power on failed, rc=%d\n", panel->name, rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_prepare(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	if (panel->lp11_init) {
+		rc = dsi_panel_power_on(panel);
+		if (rc) {
+			pr_err("[%s] panel power on failed, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_PRE_ON);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_PRE_ON cmds, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_enable(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_ON);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_ON cmds, rc=%d\n",
+		       panel->name, rc);
+	}
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_post_enable(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_POST_ON);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_POST_ON cmds, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_pre_disable(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_PRE_OFF);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_PRE_OFF cmds, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_disable(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_OFF);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_OFF cmds, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_unprepare(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_POST_OFF);
+	if (rc) {
+		pr_err("[%s] failed to send DSI_CMD_SET_POST_OFF cmds, rc=%d\n",
+		       panel->name, rc);
+		goto error;
+	}
+
+	if (panel->lp11_init) {
+		rc = dsi_panel_power_off(panel);
+		if (rc) {
+			pr_err("[%s] panel power_Off failed, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
+
+int dsi_panel_post_unprepare(struct dsi_panel *panel)
+{
+	int rc = 0;
+
+	if (!panel) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&panel->panel_lock);
+
+	if (!panel->lp11_init) {
+		rc = dsi_panel_power_off(panel);
+		if (rc) {
+			pr_err("[%s] panel power_Off failed, rc=%d\n",
+			       panel->name, rc);
+			goto error;
+		}
+	}
+error:
+	mutex_unlock(&panel->panel_lock);
+	return rc;
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
new file mode 100644
index 0000000000000000000000000000000000000000..4d21a4cf6428978b145437c68621cde92121ce82
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_PANEL_H_
+#define _DSI_PANEL_H_
+
+#include <linux/of_device.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/leds.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_mipi_dsi.h>
+
+#include "dsi_defs.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_clk_pwr.h"
+
+#define MAX_BL_LEVEL 4096
+
+enum dsi_panel_rotation {
+	DSI_PANEL_ROTATE_NONE = 0,
+	DSI_PANEL_ROTATE_HV_FLIP,
+	DSI_PANEL_ROTATE_H_FLIP,
+	DSI_PANEL_ROTATE_V_FLIP
+};
+
+enum dsi_cmd_set_type {
+	DSI_CMD_SET_PRE_ON = 0,
+	DSI_CMD_SET_ON,
+	DSI_CMD_SET_POST_ON,
+	DSI_CMD_SET_PRE_OFF,
+	DSI_CMD_SET_OFF,
+	DSI_CMD_SET_POST_OFF,
+	DSI_CMD_SET_PRE_RES_SWITCH,
+	DSI_CMD_SET_RES_SWITCH,
+	DSI_CMD_SET_POST_RES_SWITCH,
+	DSI_CMD_SET_CMD_TO_VID_SWITCH,
+	DSI_CMD_SET_POST_CMD_TO_VID_SWITCH,
+	DSI_CMD_SET_VID_TO_CMD_SWITCH,
+	DSI_CMD_SET_POST_VID_TO_CMD_SWITCH,
+	DSI_CMD_SET_PANEL_STATUS,
+	DSI_CMD_SET_MAX
+};
+
+enum dsi_cmd_set_state {
+	DSI_CMD_SET_STATE_LP = 0,
+	DSI_CMD_SET_STATE_HS,
+	DSI_CMD_SET_STATE_MAX
+};
+
+enum dsi_backlight_type {
+	DSI_BACKLIGHT_PWM = 0,
+	DSI_BACKLIGHT_WLED,
+	DSI_BACKLIGHT_DCS,
+	DSI_BACKLIGHT_UNKNOWN,
+	DSI_BACKLIGHT_MAX,
+};
+
+struct dsi_dfps_capabilities {
+	bool dfps_support;
+	enum dsi_dfps_type type;
+	u32 min_refresh_rate;
+	u32 max_refresh_rate;
+};
+
+struct dsi_pinctrl_info {
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *active;
+	struct pinctrl_state *suspend;
+};
+
+struct dsi_panel_phy_props {
+	u32 panel_width_mm;
+	u32 panel_height_mm;
+	enum dsi_panel_rotation rotation;
+};
+
+struct dsi_cmd_desc {
+	struct mipi_dsi_msg msg;
+	bool last_command;
+	u32  post_wait_ms;
+};
+
+struct dsi_panel_cmd_set {
+	enum dsi_cmd_set_type type;
+	enum dsi_cmd_set_state state;
+	u32 count;
+	struct dsi_cmd_desc *cmds;
+};
+
+struct dsi_backlight_config {
+	enum dsi_backlight_type type;
+
+	u32 bl_min_level;
+	u32 bl_max_level;
+	u32 brightness_max_level;
+
+	int en_gpio;
+	/* PWM params */
+	bool pwm_pmi_control;
+	u32 pwm_pmic_bank;
+	u32 pwm_period_usecs;
+	int pwm_gpio;
+
+	/* WLED params */
+	struct led_trigger *wled;
+	struct backlight_device *bd;
+};
+
+struct dsi_reset_seq {
+	u32 level;
+	u32 sleep_ms;
+};
+
+struct dsi_panel_reset_config {
+	struct dsi_reset_seq *sequence;
+	u32 count;
+
+	int reset_gpio;
+	int disp_en_gpio;
+};
+
+struct dsi_panel {
+	const char *name;
+	struct device_node *panel_of_node;
+	struct mipi_dsi_device mipi_device;
+
+	struct mutex panel_lock;
+	struct drm_panel drm_panel;
+	struct mipi_dsi_host *host;
+	struct device *parent;
+
+	struct dsi_host_common_cfg host_config;
+	struct dsi_video_engine_cfg video_config;
+	struct dsi_cmd_engine_cfg cmd_config;
+
+	struct dsi_dfps_capabilities dfps_caps;
+
+	struct dsi_panel_cmd_set cmd_sets[DSI_CMD_SET_MAX];
+	struct dsi_panel_phy_props phy_props;
+
+	struct dsi_regulator_info power_info;
+	struct dsi_display_mode mode;
+
+	struct dsi_backlight_config bl_config;
+	struct dsi_panel_reset_config reset_config;
+	struct dsi_pinctrl_info pinctrl;
+
+	bool lp11_init;
+};
+
+struct dsi_panel *dsi_panel_get(struct device *parent,
+				struct device_node *of_node);
+void dsi_panel_put(struct dsi_panel *panel);
+
+int dsi_panel_drv_init(struct dsi_panel *panel, struct mipi_dsi_host *host);
+int dsi_panel_drv_deinit(struct dsi_panel *panel);
+
+int dsi_panel_get_mode_count(struct dsi_panel *panel, u32 *count);
+int dsi_panel_get_mode(struct dsi_panel *panel,
+		       u32 index,
+		       struct dsi_display_mode *mode);
+int dsi_panel_validate_mode(struct dsi_panel *panel,
+			    struct dsi_display_mode *mode);
+int dsi_panel_get_host_cfg_for_mode(struct dsi_panel *panel,
+				    struct dsi_display_mode *mode,
+				    struct dsi_host_config *config);
+
+int dsi_panel_get_phy_props(struct dsi_panel *panel,
+			    struct dsi_panel_phy_props *phy_props);
+int dsi_panel_get_dfps_caps(struct dsi_panel *panel,
+			    struct dsi_dfps_capabilities *dfps_caps);
+
+int dsi_panel_pre_prepare(struct dsi_panel *panel);
+
+int dsi_panel_prepare(struct dsi_panel *panel);
+
+int dsi_panel_enable(struct dsi_panel *panel);
+
+int dsi_panel_post_enable(struct dsi_panel *panel);
+
+int dsi_panel_pre_disable(struct dsi_panel *panel);
+
+int dsi_panel_disable(struct dsi_panel *panel);
+
+int dsi_panel_unprepare(struct dsi_panel *panel);
+
+int dsi_panel_post_unprepare(struct dsi_panel *panel);
+
+int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl);
+#endif /* _DSI_PANEL_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ccbbe7df57359428de447fb4427bdc3e338b1ae
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -0,0 +1,859 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"msm-dsi-phy:[%s] " fmt, __func__
+
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/msm-bus.h>
+#include <linux/list.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_gpu.h"
+#include "dsi_phy.h"
+#include "dsi_phy_hw.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_catalog.h"
+
+#define DSI_PHY_DEFAULT_LABEL "MDSS PHY CTRL"
+
+struct dsi_phy_list_item {
+	struct msm_dsi_phy *phy;
+	struct list_head list;
+};
+
+static LIST_HEAD(dsi_phy_list);
+static DEFINE_MUTEX(dsi_phy_list_lock);
+
+static const struct dsi_ver_spec_info dsi_phy_v1_0 = {
+	.version = DSI_PHY_VERSION_1_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v2_0 = {
+	.version = DSI_PHY_VERSION_2_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v3_0 = {
+	.version = DSI_PHY_VERSION_3_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v4_0 = {
+	.version = DSI_PHY_VERSION_4_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+
+static const struct of_device_id msm_dsi_phy_of_match[] = {
+	{ .compatible = "qcom,dsi-phy-v1.0",
+	  .data = &dsi_phy_v1_0,},
+	{ .compatible = "qcom,dsi-phy-v2.0",
+	  .data = &dsi_phy_v2_0,},
+	{ .compatible = "qcom,dsi-phy-v3.0",
+	  .data = &dsi_phy_v3_0,},
+	{ .compatible = "qcom,dsi-phy-v4.0",
+	  .data = &dsi_phy_v4_0,},
+	{}
+};
+
+static int dsi_phy_regmap_init(struct platform_device *pdev,
+			       struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	void __iomem *ptr;
+
+	ptr = msm_ioremap(pdev, "dsi_phy", phy->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	phy->hw.base = ptr;
+
+	pr_debug("[%s] map dsi_phy registers to %p\n", phy->name, phy->hw.base);
+
+	return rc;
+}
+
+static int dsi_phy_regmap_deinit(struct msm_dsi_phy *phy)
+{
+	pr_debug("[%s] unmap registers\n", phy->name);
+	return 0;
+}
+
+static int dsi_phy_clocks_deinit(struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &phy->clks.core_clks;
+
+	if (core->mdp_core_clk)
+		devm_clk_put(&phy->pdev->dev, core->mdp_core_clk);
+	if (core->iface_clk)
+		devm_clk_put(&phy->pdev->dev, core->iface_clk);
+	if (core->core_mmss_clk)
+		devm_clk_put(&phy->pdev->dev, core->core_mmss_clk);
+	if (core->bus_clk)
+		devm_clk_put(&phy->pdev->dev, core->bus_clk);
+
+	memset(core, 0x0, sizeof(*core));
+
+	return rc;
+}
+
+static int dsi_phy_clocks_init(struct platform_device *pdev,
+			       struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &phy->clks.core_clks;
+
+	core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
+	if (IS_ERR(core->mdp_core_clk)) {
+		rc = PTR_ERR(core->mdp_core_clk);
+		pr_err("failed to get mdp_core_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
+	if (IS_ERR(core->iface_clk)) {
+		rc = PTR_ERR(core->iface_clk);
+		pr_err("failed to get iface_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
+	if (IS_ERR(core->core_mmss_clk)) {
+		rc = PTR_ERR(core->core_mmss_clk);
+		pr_err("failed to get core_mmss_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
+	if (IS_ERR(core->bus_clk)) {
+		rc = PTR_ERR(core->bus_clk);
+		pr_err("failed to get bus_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	return rc;
+fail:
+	dsi_phy_clocks_deinit(phy);
+	return rc;
+}
+
+static int dsi_phy_supplies_init(struct platform_device *pdev,
+				 struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_regulator_info *regs;
+	struct regulator *vreg = NULL;
+
+	regs = &phy->pwr_info.digital;
+	regs->vregs = devm_kzalloc(&pdev->dev, sizeof(struct dsi_vreg),
+				   GFP_KERNEL);
+	if (!regs->vregs)
+		goto error;
+
+	regs->count = 1;
+	snprintf(regs->vregs->vreg_name,
+		 ARRAY_SIZE(regs->vregs[i].vreg_name),
+		 "%s", "gdsc");
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &phy->pwr_info.phy_pwr,
+					  "qcom,phy-supply-entries");
+	if (rc) {
+		pr_err("failed to get host power supplies, rc = %d\n", rc);
+		goto error_digital;
+	}
+
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		rc = PTR_RET(vreg);
+		if (rc) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			goto error_host_pwr;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	regs = &phy->pwr_info.phy_pwr;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		rc = PTR_RET(vreg);
+		if (rc) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			for (--i; i >= 0; i--)
+				devm_regulator_put(regs->vregs[i].vreg);
+			goto error_digital_put;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	return rc;
+
+error_digital_put:
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++)
+		devm_regulator_put(regs->vregs[i].vreg);
+error_host_pwr:
+	devm_kfree(&pdev->dev, phy->pwr_info.phy_pwr.vregs);
+	phy->pwr_info.phy_pwr.vregs = NULL;
+	phy->pwr_info.phy_pwr.count = 0;
+error_digital:
+	devm_kfree(&pdev->dev, phy->pwr_info.digital.vregs);
+	phy->pwr_info.digital.vregs = NULL;
+	phy->pwr_info.digital.count = 0;
+error:
+	return rc;
+}
+
+static int dsi_phy_supplies_deinit(struct msm_dsi_phy *phy)
+{
+	int i = 0;
+	int rc = 0;
+	struct dsi_regulator_info *regs;
+
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	regs = &phy->pwr_info.phy_pwr;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	if (phy->pwr_info.phy_pwr.vregs) {
+		devm_kfree(&phy->pdev->dev, phy->pwr_info.phy_pwr.vregs);
+		phy->pwr_info.phy_pwr.vregs = NULL;
+		phy->pwr_info.phy_pwr.count = 0;
+	}
+	if (phy->pwr_info.digital.vregs) {
+		devm_kfree(&phy->pdev->dev, phy->pwr_info.digital.vregs);
+		phy->pwr_info.digital.vregs = NULL;
+		phy->pwr_info.digital.count = 0;
+	}
+
+	return rc;
+}
+
+static int dsi_phy_parse_dt_per_lane_cfgs(struct platform_device *pdev,
+					  struct dsi_phy_per_lane_cfgs *cfg,
+					  char *property)
+{
+	int rc = 0, i = 0, j = 0;
+	const u8 *data;
+	u32 len = 0;
+
+	data = of_get_property(pdev->dev.of_node, property, &len);
+	if (!data) {
+		pr_err("Unable to read Phy %s settings\n", property);
+		return -EINVAL;
+	}
+
+	if (len != DSI_LANE_MAX * cfg->count_per_lane) {
+		pr_err("incorrect phy %s settings, exp=%d, act=%d\n",
+		       property, (DSI_LANE_MAX * cfg->count_per_lane), len);
+		return -EINVAL;
+	}
+
+	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+		for (j = 0; j < cfg->count_per_lane; j++) {
+			cfg->lane[i][j] = *data;
+			data++;
+		}
+	}
+
+	return rc;
+}
+
+static int dsi_phy_settings_init(struct platform_device *pdev,
+				 struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_phy_per_lane_cfgs *lane = &phy->cfg.lanecfg;
+	struct dsi_phy_per_lane_cfgs *strength = &phy->cfg.strength;
+	struct dsi_phy_per_lane_cfgs *timing = &phy->cfg.timing;
+	struct dsi_phy_per_lane_cfgs *regs = &phy->cfg.regulators;
+
+	lane->count_per_lane = phy->ver_info->lane_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, lane,
+					    "qcom,platform-lane-config");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	strength->count_per_lane = phy->ver_info->strength_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, strength,
+					    "qcom,platform-strength-ctrl");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	regs->count_per_lane = phy->ver_info->regulator_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, regs,
+					    "qcom,platform-regulator-settings");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	/* Actual timing values are dependent on panel */
+	timing->count_per_lane = phy->ver_info->timing_cfg_count;
+
+err:
+	lane->count_per_lane = 0;
+	strength->count_per_lane = 0;
+	regs->count_per_lane = 0;
+	timing->count_per_lane = 0;
+	return rc;
+}
+
+static int dsi_phy_settings_deinit(struct msm_dsi_phy *phy)
+{
+	memset(&phy->cfg.lanecfg, 0x0, sizeof(phy->cfg.lanecfg));
+	memset(&phy->cfg.strength, 0x0, sizeof(phy->cfg.strength));
+	memset(&phy->cfg.timing, 0x0, sizeof(phy->cfg.timing));
+	memset(&phy->cfg.regulators, 0x0, sizeof(phy->cfg.regulators));
+	return 0;
+}
+
+static int dsi_phy_driver_probe(struct platform_device *pdev)
+{
+	struct msm_dsi_phy *dsi_phy;
+	struct dsi_phy_list_item *item;
+	const struct of_device_id *id;
+	const struct dsi_ver_spec_info *ver_info;
+	int rc = 0;
+	u32 index = 0;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	id = of_match_node(msm_dsi_phy_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+
+	ver_info = id->data;
+
+	item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
+	if (!item)
+		return -ENOMEM;
+
+
+	dsi_phy = devm_kzalloc(&pdev->dev, sizeof(*dsi_phy), GFP_KERNEL);
+	if (!dsi_phy) {
+		devm_kfree(&pdev->dev, item);
+		return -ENOMEM;
+	}
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
+	if (rc) {
+		pr_debug("cell index not set, default to 0\n");
+		index = 0;
+	}
+
+	dsi_phy->index = index;
+
+	dsi_phy->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!dsi_phy->name)
+		dsi_phy->name = DSI_PHY_DEFAULT_LABEL;
+
+	pr_debug("Probing %s device\n", dsi_phy->name);
+
+	rc = dsi_phy_regmap_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("Failed to parse register information, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_phy_clocks_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("failed to parse clock information, rc = %d\n", rc);
+		goto fail_regmap;
+	}
+
+	rc = dsi_phy_supplies_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("failed to parse voltage supplies, rc = %d\n", rc);
+		goto fail_clks;
+	}
+
+	rc = dsi_catalog_phy_setup(&dsi_phy->hw, ver_info->version,
+				   dsi_phy->index);
+	if (rc) {
+		pr_err("Catalog does not support version (%d)\n",
+		       ver_info->version);
+		goto fail_supplies;
+	}
+
+	dsi_phy->ver_info = ver_info;
+	rc = dsi_phy_settings_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("Failed to parse phy setting, rc=%d\n", rc);
+		goto fail_supplies;
+	}
+
+	item->phy = dsi_phy;
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_add(&item->list, &dsi_phy_list);
+	mutex_unlock(&dsi_phy_list_lock);
+
+	mutex_init(&dsi_phy->phy_lock);
+	/** TODO: initialize debugfs */
+	dsi_phy->pdev = pdev;
+	platform_set_drvdata(pdev, dsi_phy);
+	pr_debug("Probe successful for %s\n", dsi_phy->name);
+	return 0;
+
+fail_supplies:
+	(void)dsi_phy_supplies_deinit(dsi_phy);
+fail_clks:
+	(void)dsi_phy_clocks_deinit(dsi_phy);
+fail_regmap:
+	(void)dsi_phy_regmap_deinit(dsi_phy);
+fail:
+	devm_kfree(&pdev->dev, dsi_phy);
+	devm_kfree(&pdev->dev, item);
+	return rc;
+}
+
+static int dsi_phy_driver_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
+	struct list_head *pos, *tmp;
+
+	if (!pdev || !phy) {
+		pr_err("Invalid device\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_phy_list) {
+		struct dsi_phy_list_item *n;
+
+		n = list_entry(pos, struct dsi_phy_list_item, list);
+		if (n->phy == phy) {
+			list_del(&n->list);
+			devm_kfree(&pdev->dev, n);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_phy_list_lock);
+
+	mutex_lock(&phy->phy_lock);
+	rc = dsi_phy_settings_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize phy settings, rc=%d\n", rc);
+
+	rc = dsi_phy_supplies_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize voltage supplies, rc=%d\n", rc);
+
+	rc = dsi_phy_clocks_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize clocks, rc=%d\n", rc);
+
+	rc = dsi_phy_regmap_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize regmap, rc=%d\n", rc);
+	mutex_unlock(&phy->phy_lock);
+
+	mutex_destroy(&phy->phy_lock);
+	devm_kfree(&pdev->dev, phy);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver dsi_phy_platform_driver = {
+	.probe      = dsi_phy_driver_probe,
+	.remove     = dsi_phy_driver_remove,
+	.driver     = {
+		.name   = "dsi_phy",
+		.of_match_table = msm_dsi_phy_of_match,
+	},
+};
+
+static void dsi_phy_enable_hw(struct msm_dsi_phy *phy)
+{
+	if (phy->hw.ops.regulator_enable)
+		phy->hw.ops.regulator_enable(&phy->hw, &phy->cfg.regulators);
+
+	if (phy->hw.ops.enable)
+		phy->hw.ops.enable(&phy->hw, &phy->cfg);
+}
+
+static void dsi_phy_disable_hw(struct msm_dsi_phy *phy)
+{
+	if (phy->hw.ops.disable)
+		phy->hw.ops.disable(&phy->hw);
+
+	if (phy->hw.ops.regulator_disable)
+		phy->hw.ops.regulator_disable(&phy->hw);
+}
+
+/**
+ * dsi_phy_get() - get a dsi phy handle from device node
+ * @of_node:           device node for dsi phy controller
+ *
+ * Gets the DSI PHY handle for the corresponding of_node. The ref count is
+ * incremented to one all subsequents get will fail until the original client
+ * calls a put.
+ *
+ * Return: DSI PHY handle or an error code.
+ */
+struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node)
+{
+	struct list_head *pos, *tmp;
+	struct msm_dsi_phy *phy = NULL;
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_phy_list) {
+		struct dsi_phy_list_item *n;
+
+		n = list_entry(pos, struct dsi_phy_list_item, list);
+		if (n->phy->pdev->dev.of_node == of_node) {
+			phy = n->phy;
+			break;
+		}
+	}
+	mutex_unlock(&dsi_phy_list_lock);
+
+	if (!phy) {
+		pr_err("Device with of node not found\n");
+		phy = ERR_PTR(-EPROBE_DEFER);
+		return phy;
+	}
+
+	mutex_lock(&phy->phy_lock);
+	if (phy->refcount > 0) {
+		pr_err("[PHY_%d] Device under use\n", phy->index);
+		phy = ERR_PTR(-EINVAL);
+	} else {
+		phy->refcount++;
+	}
+	mutex_unlock(&phy->phy_lock);
+	return phy;
+}
+
+/**
+ * dsi_phy_put() - release dsi phy handle
+ * @dsi_phy:              DSI PHY handle.
+ *
+ * Release the DSI PHY hardware. Driver will clean up all resources and puts
+ * back the DSI PHY into reset state.
+ */
+void dsi_phy_put(struct msm_dsi_phy *dsi_phy)
+{
+	mutex_lock(&dsi_phy->phy_lock);
+
+	if (dsi_phy->refcount == 0)
+		pr_err("Unbalanced dsi_phy_put call\n");
+	else
+		dsi_phy->refcount--;
+
+	mutex_unlock(&dsi_phy->phy_lock);
+}
+
+/**
+ * dsi_phy_drv_init() - initialize dsi phy driver
+ * @dsi_phy:         DSI PHY handle.
+ *
+ * Initializes DSI PHY driver. Should be called after dsi_phy_get().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy)
+{
+	return 0;
+}
+
+/**
+ * dsi_phy_drv_deinit() - de-initialize dsi phy driver
+ * @dsi_phy:          DSI PHY handle.
+ *
+ * Release all resources acquired by dsi_phy_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy)
+{
+	return 0;
+}
+
+/**
+ * dsi_phy_validate_mode() - validate a display mode
+ * @dsi_phy:            DSI PHY handle.
+ * @mode:               Mode information.
+ *
+ * Validation will fail if the mode cannot be supported by the PHY driver or
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
+			  struct dsi_mode_info *mode)
+{
+	int rc = 0;
+
+	if (!dsi_phy || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy->phy_lock);
+
+	pr_debug("[PHY_%d] Skipping validation\n", dsi_phy->index);
+
+	mutex_unlock(&dsi_phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
+ * @dsi_phy:               DSI PHY handle.
+ * @enable:                Boolean flag to enable/disable.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_phy) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy->phy_lock);
+
+	if (enable == dsi_phy->power_state) {
+		pr_err("[PHY_%d] No state change\n", dsi_phy->index);
+		goto error;
+	}
+
+	if (enable) {
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital, true);
+		if (rc) {
+			pr_err("failed to enable digital regulator\n");
+			goto error;
+		}
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.phy_pwr, true);
+		if (rc) {
+			pr_err("failed to enable phy power\n");
+			(void)dsi_pwr_enable_regulator(
+						&dsi_phy->pwr_info.digital,
+						false
+						);
+			goto error;
+		}
+	} else {
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.phy_pwr,
+					      false);
+		if (rc) {
+			pr_err("failed to enable digital regulator\n");
+			goto error;
+		}
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital,
+					      false);
+		if (rc) {
+			pr_err("failed to enable phy power\n");
+			goto error;
+		}
+	}
+
+	dsi_phy->power_state = enable;
+error:
+	mutex_unlock(&dsi_phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_enable() - enable DSI PHY hardware
+ * @dsi_phy:            DSI PHY handle.
+ * @config:             DSI host configuration.
+ * @pll_source:         Source PLL for PHY clock.
+ * @skip_validation:    Validation will not be performed on parameters.
+ *
+ * Validates and enables DSI PHY.
+ *
+ * Return: error code.
+ */
+int dsi_phy_enable(struct msm_dsi_phy *phy,
+		   struct dsi_host_config *config,
+		   enum dsi_phy_pll_source pll_source,
+		   bool skip_validation)
+{
+	int rc = 0;
+
+	if (!phy || !config) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	if (!skip_validation)
+		pr_debug("[PHY_%d] TODO: perform validation\n", phy->index);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, true);
+	if (rc) {
+		pr_err("failed to enable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+	memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
+	phy->data_lanes = config->common_config.data_lanes;
+	phy->dst_format = config->common_config.dst_format;
+	phy->lane_map = config->lane_map;
+	phy->cfg.pll_source = pll_source;
+
+	rc = phy->hw.ops.calculate_timing_params(&phy->hw,
+						 &phy->mode,
+						 &config->common_config,
+						 &phy->cfg.timing);
+	if (rc) {
+		pr_err("[%s] failed to set timing, rc=%d\n", phy->name, rc);
+		goto error_disable_clks;
+	}
+
+	dsi_phy_enable_hw(phy);
+
+error_disable_clks:
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, false);
+	if (rc) {
+		pr_err("failed to disable clocks, skip phy disable\n");
+		goto error;
+	}
+error:
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_disable() - disable DSI PHY hardware.
+ * @phy:        DSI PHY handle.
+ *
+ * Return: error code.
+ */
+int dsi_phy_disable(struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+
+	if (!phy) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, true);
+	if (rc) {
+		pr_err("failed to enable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+	dsi_phy_disable_hw(phy);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, false);
+	if (rc) {
+		pr_err("failed to disable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_set_timing_params() - timing parameters for the panel
+ * @phy:          DSI PHY handle
+ * @timing:       array holding timing params.
+ * @size:         size of the array.
+ *
+ * When PHY timing calculator is not implemented, this array will be used to
+ * pass PHY timing information.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
+			      u8 *timing, u32 size)
+{
+	int rc = 0;
+	int i, j;
+	struct dsi_phy_per_lane_cfgs *timing_cfg;
+
+	if (!phy || !timing || !size) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	if (size != (DSI_LANE_MAX * phy->cfg.timing.count_per_lane)) {
+		pr_err("Unexpected timing array size %d\n", size);
+		rc = -EINVAL;
+	} else {
+		timing_cfg = &phy->cfg.timing;
+		for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+			for (j = 0; j < timing_cfg->count_per_lane; j++) {
+				timing_cfg->lane[i][j] = *timing;
+				timing++;
+			}
+		}
+	}
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+void dsi_phy_drv_register(void)
+{
+	platform_driver_register(&dsi_phy_platform_driver);
+}
+
+void dsi_phy_drv_unregister(void)
+{
+	platform_driver_unregister(&dsi_phy_platform_driver);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c31bfa3ea004f9bcbd08284865609689e1e655f
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_PHY_H_
+#define _DSI_PHY_H_
+
+#include "dsi_defs.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_phy_hw.h"
+
+struct dsi_ver_spec_info {
+	enum dsi_phy_version version;
+	u32 lane_cfg_count;
+	u32 strength_cfg_count;
+	u32 regulator_cfg_count;
+	u32 timing_cfg_count;
+};
+
+/**
+ * struct dsi_phy_clk_info - clock information for DSI controller
+ * @core_clks:         Core clocks needed to access PHY registers.
+ */
+struct dsi_phy_clk_info {
+	struct dsi_core_clk_info core_clks;
+};
+
+/**
+ * struct dsi_phy_power_info - digital and analog power supplies for DSI PHY
+ * @digital:       Digital power supply for DSI PHY.
+ * @phy_pwr:       Analog power supplies for DSI PHY to work.
+ */
+struct dsi_phy_power_info {
+	struct dsi_regulator_info digital;
+	struct dsi_regulator_info phy_pwr;
+};
+
+/**
+ * struct msm_dsi_phy - DSI PHY object
+ * @pdev:              Pointer to platform device.
+ * @index:             Instance id.
+ * @name:              Name of the PHY instance.
+ * @refcount:          Reference count.
+ * @phy_lock:          Mutex for hardware and object access.
+ * @ver_info:          Version specific phy parameters.
+ * @hw:                DSI PHY hardware object.
+ * @cfg:               DSI phy configuration.
+ * @power_state:       True if PHY is powered on.
+ * @mode:              Current mode.
+ * @data_lanes:        Number of data lanes used.
+ * @dst_format:        Destination format.
+ * @lane_map:          Map between logical and physical lanes.
+ */
+struct msm_dsi_phy {
+	struct platform_device *pdev;
+	int index;
+	const char *name;
+	u32 refcount;
+	struct mutex phy_lock;
+
+	const struct dsi_ver_spec_info *ver_info;
+	struct dsi_phy_hw hw;
+
+	struct dsi_phy_clk_info clks;
+	struct dsi_phy_power_info pwr_info;
+
+	struct dsi_phy_cfg cfg;
+
+	bool power_state;
+	struct dsi_mode_info mode;
+	enum dsi_data_lanes data_lanes;
+	enum dsi_pixel_format dst_format;
+	struct dsi_lane_mapping lane_map;
+};
+
+/**
+ * dsi_phy_get() - get a dsi phy handle from device node
+ * @of_node:           device node for dsi phy controller
+ *
+ * Gets the DSI PHY handle for the corresponding of_node. The ref count is
+ * incremented to one all subsequents get will fail until the original client
+ * calls a put.
+ *
+ * Return: DSI PHY handle or an error code.
+ */
+struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node);
+
+/**
+ * dsi_phy_put() - release dsi phy handle
+ * @dsi_phy:              DSI PHY handle.
+ *
+ * Release the DSI PHY hardware. Driver will clean up all resources and puts
+ * back the DSI PHY into reset state.
+ */
+void dsi_phy_put(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_drv_init() - initialize dsi phy driver
+ * @dsi_phy:         DSI PHY handle.
+ *
+ * Initializes DSI PHY driver. Should be called after dsi_phy_get().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_drv_deinit() - de-initialize dsi phy driver
+ * @dsi_phy:          DSI PHY handle.
+ *
+ * Release all resources acquired by dsi_phy_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_validate_mode() - validate a display mode
+ * @dsi_phy:            DSI PHY handle.
+ * @mode:               Mode information.
+ *
+ * Validation will fail if the mode cannot be supported by the PHY driver or
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
+			  struct dsi_mode_info *mode);
+
+/**
+ * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
+ * @dsi_phy:               DSI PHY handle.
+ * @enable:                Boolean flag to enable/disable.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable);
+
+/**
+ * dsi_phy_enable() - enable DSI PHY hardware
+ * @dsi_phy:            DSI PHY handle.
+ * @config:             DSI host configuration.
+ * @pll_source:         Source PLL for PHY clock.
+ * @skip_validation:    Validation will not be performed on parameters.
+ *
+ * Validates and enables DSI PHY.
+ *
+ * Return: error code.
+ */
+int dsi_phy_enable(struct msm_dsi_phy *dsi_phy,
+		   struct dsi_host_config *config,
+		   enum dsi_phy_pll_source pll_source,
+		   bool skip_validation);
+
+/**
+ * dsi_phy_disable() - disable DSI PHY hardware.
+ * @phy:        DSI PHY handle.
+ *
+ * Return: error code.
+ */
+int dsi_phy_disable(struct msm_dsi_phy *phy);
+
+/**
+ * dsi_phy_set_timing_params() - timing parameters for the panel
+ * @phy:          DSI PHY handle
+ * @timing:       array holding timing params.
+ * @size:         size of the array.
+ *
+ * When PHY timing calculator is not implemented, this array will be used to
+ * pass PHY timing information.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
+			      u8 *timing, u32 size);
+
+/**
+ * dsi_phy_drv_register() - register platform driver for dsi phy
+ */
+void dsi_phy_drv_register(void);
+
+/**
+ * dsi_phy_drv_unregister() - unregister platform driver
+ */
+void dsi_phy_drv_unregister(void);
+
+#endif /* _DSI_PHY_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..5edfd5e627389ffbc9af4d545bf15d0ff1c18768
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_PHY_HW_H_
+#define _DSI_PHY_HW_H_
+
+#include "dsi_defs.h"
+
+#define DSI_MAX_SETTINGS 8
+
+/**
+ * enum dsi_phy_version - DSI PHY version enumeration
+ * @DSI_PHY_VERSION_UNKNOWN:    Unknown version.
+ * @DSI_PHY_VERSION_1_0:        28nm-HPM.
+ * @DSI_PHY_VERSION_2_0:        28nm-LPM.
+ * @DSI_PHY_VERSION_3_0:        20nm.
+ * @DSI_PHY_VERSION_4_0:        14nm.
+ * @DSI_PHY_VERSION_MAX:
+ */
+enum dsi_phy_version {
+	DSI_PHY_VERSION_UNKNOWN,
+	DSI_PHY_VERSION_1_0, /* 28nm-HPM */
+	DSI_PHY_VERSION_2_0, /* 28nm-LPM */
+	DSI_PHY_VERSION_3_0, /* 20nm */
+	DSI_PHY_VERSION_4_0, /* 14nm */
+	DSI_PHY_VERSION_MAX
+};
+
+/**
+ * enum dsi_phy_hw_features - features supported by DSI PHY hardware
+ * @DSI_PHY_DPHY:        Supports DPHY
+ * @DSI_PHY_CPHY:        Supports CPHY
+ */
+enum dsi_phy_hw_features {
+	DSI_PHY_DPHY,
+	DSI_PHY_CPHY,
+	DSI_PHY_MAX_FEATURES
+};
+
+/**
+ * enum dsi_phy_pll_source - pll clock source for PHY.
+ * @DSI_PLL_SOURCE_STANDALONE:    Clock is sourced from native PLL and is not
+ *				  shared by other PHYs.
+ * @DSI_PLL_SOURCE_NATIVE:        Clock is sourced from native PLL and is
+ *				  shared by other PHYs.
+ * @DSI_PLL_SOURCE_NON_NATIVE:    Clock is sourced from other PHYs.
+ * @DSI_PLL_SOURCE_MAX:
+ */
+enum dsi_phy_pll_source {
+	DSI_PLL_SOURCE_STANDALONE = 0,
+	DSI_PLL_SOURCE_NATIVE,
+	DSI_PLL_SOURCE_NON_NATIVE,
+	DSI_PLL_SOURCE_MAX
+};
+
+/**
+ * struct dsi_phy_per_lane_cfgs - Holds register values for PHY parameters
+ * @lane:           A set of maximum 8 values for each lane.
+ * @count_per_lane: Number of values per each lane.
+ */
+struct dsi_phy_per_lane_cfgs {
+	u8 lane[DSI_LANE_MAX][DSI_MAX_SETTINGS];
+	u32 count_per_lane;
+};
+
+/**
+ * struct dsi_phy_cfg - DSI PHY configuration
+ * @lanecfg:          Lane configuration settings.
+ * @strength:         Strength settings for lanes.
+ * @timing:           Timing parameters for lanes.
+ * @regulators:       Regulator settings for lanes.
+ * @pll_source:       PLL source.
+ */
+struct dsi_phy_cfg {
+	struct dsi_phy_per_lane_cfgs lanecfg;
+	struct dsi_phy_per_lane_cfgs strength;
+	struct dsi_phy_per_lane_cfgs timing;
+	struct dsi_phy_per_lane_cfgs regulators;
+	enum dsi_phy_pll_source pll_source;
+};
+
+struct dsi_phy_hw;
+
+/**
+ * struct dsi_phy_hw_ops - Operations for DSI PHY hardware.
+ * @regulator_enable:          Enable PHY regulators.
+ * @regulator_disable:         Disable PHY regulators.
+ * @enable:                    Enable PHY.
+ * @disable:                   Disable PHY.
+ * @calculate_timing_params:   Calculate PHY timing params from mode information
+ */
+struct dsi_phy_hw_ops {
+	/**
+	 * regulator_enable() - enable regulators for DSI PHY
+	 * @phy:      Pointer to DSI PHY hardware object.
+	 * @reg_cfg:  Regulator configuration for all DSI lanes.
+	 */
+	void (*regulator_enable)(struct dsi_phy_hw *phy,
+				 struct dsi_phy_per_lane_cfgs *reg_cfg);
+
+	/**
+	 * regulator_disable() - disable regulators
+	 * @phy:      Pointer to DSI PHY hardware object.
+	 */
+	void (*regulator_disable)(struct dsi_phy_hw *phy);
+
+	/**
+	 * enable() - Enable PHY hardware
+	 * @phy:      Pointer to DSI PHY hardware object.
+	 * @cfg:      Per lane configurations for timing, strength and lane
+	 *	      configurations.
+	 */
+	void (*enable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
+
+	/**
+	 * disable() - Disable PHY hardware
+	 * @phy:      Pointer to DSI PHY hardware object.
+	 */
+	void (*disable)(struct dsi_phy_hw *phy);
+
+	/**
+	 * calculate_timing_params() - calculates timing parameters.
+	 * @phy:      Pointer to DSI PHY hardware object.
+	 * @mode:     Mode information for which timing has to be calculated.
+	 * @config:   DSI host configuration for this mode.
+	 * @timing:   Timing parameters for each lane which will be returned.
+	 */
+	int (*calculate_timing_params)(struct dsi_phy_hw *phy,
+				       struct dsi_mode_info *mode,
+				       struct dsi_host_common_cfg *config,
+				       struct dsi_phy_per_lane_cfgs *timing);
+};
+
+/**
+ * struct dsi_phy_hw - DSI phy hardware object specific to an instance
+ * @base:                  VA for the DSI PHY base address.
+ * @length:                Length of the DSI PHY register base map.
+ * @index:                 Instance ID of the controller.
+ * @version:               DSI PHY version.
+ * @feature_map:           Features supported by DSI PHY.
+ * @ops:                   Function pointer to PHY operations.
+ */
+struct dsi_phy_hw {
+	void __iomem *base;
+	u32 length;
+	u32 index;
+
+	enum dsi_phy_version version;
+
+	DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES);
+	struct dsi_phy_hw_ops ops;
+};
+
+#endif /* _DSI_PHY_HW_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c
new file mode 100644
index 0000000000000000000000000000000000000000..512352d96f9831ec75e8d8bc3af2d13d3395e389
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c
@@ -0,0 +1,858 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "dsi-phy-hw:" fmt
+#include <linux/math64.h>
+#include <linux/delay.h>
+#include "dsi_hw.h"
+#include "dsi_phy_hw.h"
+
+#define DSIPHY_CMN_REVISION_ID0                   0x0000
+#define DSIPHY_CMN_REVISION_ID1                   0x0004
+#define DSIPHY_CMN_REVISION_ID2                   0x0008
+#define DSIPHY_CMN_REVISION_ID3                   0x000C
+#define DSIPHY_CMN_CLK_CFG0                       0x0010
+#define DSIPHY_CMN_CLK_CFG1                       0x0014
+#define DSIPHY_CMN_GLBL_TEST_CTRL                 0x0018
+#define DSIPHY_CMN_CTRL_0                         0x001C
+#define DSIPHY_CMN_CTRL_1                         0x0020
+#define DSIPHY_CMN_CAL_HW_TRIGGER                 0x0024
+#define DSIPHY_CMN_CAL_SW_CFG0                    0x0028
+#define DSIPHY_CMN_CAL_SW_CFG1                    0x002C
+#define DSIPHY_CMN_CAL_SW_CFG2                    0x0030
+#define DSIPHY_CMN_CAL_HW_CFG0                    0x0034
+#define DSIPHY_CMN_CAL_HW_CFG1                    0x0038
+#define DSIPHY_CMN_CAL_HW_CFG2                    0x003C
+#define DSIPHY_CMN_CAL_HW_CFG3                    0x0040
+#define DSIPHY_CMN_CAL_HW_CFG4                    0x0044
+#define DSIPHY_CMN_PLL_CNTRL                      0x0048
+#define DSIPHY_CMN_LDO_CNTRL                      0x004C
+
+#define DSIPHY_CMN_REGULATOR_CAL_STATUS0          0x0064
+#define DSIPHY_CMN_REGULATOR_CAL_STATUS1          0x0068
+
+/* n = 0..3 for data lanes and n = 4 for clock lane */
+#define DSIPHY_DLNX_CFG0(n)                     (0x100 + ((n) * 0x80))
+#define DSIPHY_DLNX_CFG1(n)                     (0x104 + ((n) * 0x80))
+#define DSIPHY_DLNX_CFG2(n)                     (0x108 + ((n) * 0x80))
+#define DSIPHY_DLNX_CFG3(n)                     (0x10C + ((n) * 0x80))
+#define DSIPHY_DLNX_TEST_DATAPATH(n)            (0x110 + ((n) * 0x80))
+#define DSIPHY_DLNX_TEST_STR(n)                 (0x114 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_4(n)            (0x118 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_5(n)            (0x11C + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_6(n)            (0x120 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_7(n)            (0x124 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_8(n)            (0x128 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_9(n)            (0x12C + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_10(n)           (0x130 + ((n) * 0x80))
+#define DSIPHY_DLNX_TIMING_CTRL_11(n)           (0x134 + ((n) * 0x80))
+#define DSIPHY_DLNX_STRENGTH_CTRL_0(n)          (0x138 + ((n) * 0x80))
+#define DSIPHY_DLNX_STRENGTH_CTRL_1(n)          (0x13C + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_POLY(n)                (0x140 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_SEED0(n)               (0x144 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_SEED1(n)               (0x148 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_HEAD(n)                (0x14C + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_SOT(n)                 (0x150 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_CTRL0(n)               (0x154 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_CTRL1(n)               (0x158 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_CTRL2(n)               (0x15C + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_CTRL3(n)               (0x160 + ((n) * 0x80))
+#define DSIPHY_DLNX_VREG_CNTRL(n)               (0x164 + ((n) * 0x80))
+#define DSIPHY_DLNX_HSTX_STR_STATUS(n)          (0x168 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_STATUS0(n)             (0x16C + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_STATUS1(n)             (0x170 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_STATUS2(n)             (0x174 + ((n) * 0x80))
+#define DSIPHY_DLNX_BIST_STATUS3(n)             (0x178 + ((n) * 0x80))
+#define DSIPHY_DLNX_MISR_STATUS(n)              (0x17C + ((n) * 0x80))
+
+#define DSIPHY_PLL_CLKBUFLR_EN                  0x041C
+#define DSIPHY_PLL_PLL_BANDGAP                  0x0508
+
+/**
+ * struct timing_entry - Calculated values for each timing parameter.
+ * @mipi_min:
+ * @mipi_max:
+ * @rec_min:
+ * @rec_max:
+ * @rec:
+ * @reg_value:       Value to be programmed in register.
+ */
+struct timing_entry {
+	s32 mipi_min;
+	s32 mipi_max;
+	s32 rec_min;
+	s32 rec_max;
+	s32 rec;
+	u8 reg_value;
+};
+
+/**
+ * struct phy_timing_desc - Timing parameters for DSI PHY.
+ */
+struct phy_timing_desc {
+	struct timing_entry clk_prepare;
+	struct timing_entry clk_zero;
+	struct timing_entry clk_trail;
+	struct timing_entry hs_prepare;
+	struct timing_entry hs_zero;
+	struct timing_entry hs_trail;
+	struct timing_entry hs_rqst;
+	struct timing_entry hs_rqst_clk;
+	struct timing_entry hs_exit;
+	struct timing_entry ta_go;
+	struct timing_entry ta_sure;
+	struct timing_entry ta_set;
+	struct timing_entry clk_post;
+	struct timing_entry clk_pre;
+};
+
+/**
+ * struct phy_clk_params - Clock parameters for PHY timing calculations.
+ */
+struct phy_clk_params {
+	u32 bitclk_mbps;
+	u32 escclk_numer;
+	u32 escclk_denom;
+	u32 tlpx_numer_ns;
+	u32 treot_ns;
+};
+
+/**
+ * regulator_enable() - enable regulators for DSI PHY
+ * @phy:      Pointer to DSI PHY hardware object.
+ * @reg_cfg:  Regulator configuration for all DSI lanes.
+ */
+void dsi_phy_hw_v4_0_regulator_enable(struct dsi_phy_hw *phy,
+				      struct dsi_phy_per_lane_cfgs *reg_cfg)
+{
+	int i;
+
+	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
+		DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), reg_cfg->lane[i][0]);
+
+	/* make sure all values are written to hardware */
+	wmb();
+
+	pr_debug("[DSI_%d] Phy regulators enabled\n", phy->index);
+}
+
+/**
+ * regulator_disable() - disable regulators
+ * @phy:      Pointer to DSI PHY hardware object.
+ */
+void dsi_phy_hw_v4_0_regulator_disable(struct dsi_phy_hw *phy)
+{
+	pr_debug("[DSI_%d] Phy regulators disabled\n", phy->index);
+}
+
+/**
+ * enable() - Enable PHY hardware
+ * @phy:      Pointer to DSI PHY hardware object.
+ * @cfg:      Per lane configurations for timing, strength and lane
+ *	      configurations.
+ */
+void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
+			    struct dsi_phy_cfg *cfg)
+{
+	int i;
+	struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
+	u32 data;
+
+	DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C);
+
+	DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0x1);
+	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+
+		DSI_W32(phy, DSIPHY_DLNX_CFG0(i), cfg->lanecfg.lane[i][0]);
+		DSI_W32(phy, DSIPHY_DLNX_CFG1(i), cfg->lanecfg.lane[i][1]);
+		DSI_W32(phy, DSIPHY_DLNX_CFG2(i), cfg->lanecfg.lane[i][2]);
+		DSI_W32(phy, DSIPHY_DLNX_CFG3(i), cfg->lanecfg.lane[i][3]);
+
+		DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i), 0x88);
+
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_4(i), timing->lane[i][0]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_5(i), timing->lane[i][1]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_6(i), timing->lane[i][2]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_7(i), timing->lane[i][3]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_8(i), timing->lane[i][4]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_9(i), timing->lane[i][5]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_10(i), timing->lane[i][6]);
+		DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL_11(i), timing->lane[i][7]);
+
+		DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL_0(i),
+			cfg->strength.lane[i][0]);
+		DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL_1(i),
+			cfg->strength.lane[i][1]);
+	}
+
+	/* make sure all values are written to hardware before enabling phy */
+	wmb();
+
+	DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x80);
+	udelay(100);
+	DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x00);
+
+	data = DSI_R32(phy, DSIPHY_CMN_GLBL_TEST_CTRL);
+
+	switch (cfg->pll_source) {
+	case DSI_PLL_SOURCE_STANDALONE:
+		DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x01);
+		data &= ~BIT(2);
+		break;
+	case DSI_PLL_SOURCE_NATIVE:
+		DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x03);
+		data &= ~BIT(2);
+		break;
+	case DSI_PLL_SOURCE_NON_NATIVE:
+		DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x00);
+		data |= BIT(2);
+		break;
+	default:
+		break;
+	}
+
+	DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, data);
+
+	/* Enable bias current for pll1 during split display case */
+	if (cfg->pll_source == DSI_PLL_SOURCE_NON_NATIVE)
+		DSI_W32(phy, DSIPHY_PLL_PLL_BANDGAP, 0x3);
+
+	pr_debug("[DSI_%d]Phy enabled ", phy->index);
+}
+
+/**
+ * disable() - Disable PHY hardware
+ * @phy:      Pointer to DSI PHY hardware object.
+ */
+void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy)
+{
+	DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0);
+	DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
+	DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0);
+	pr_debug("[DSI_%d]Phy disabled ", phy->index);
+}
+
+static const u32 bits_per_pixel[DSI_PIXEL_FORMAT_MAX] = {
+	16, 18, 18, 24, 3, 8, 12 };
+
+/**
+ * calc_clk_prepare - calculates prepare timing params for clk lane.
+ */
+static int calc_clk_prepare(struct phy_clk_params *clk_params,
+			    struct phy_timing_desc *desc,
+			    s32 *actual_frac,
+			    s64 *actual_intermediate)
+{
+	u32 const min_prepare_frac = 50;
+	u64 const multiplier = BIT(20);
+
+	struct timing_entry *t = &desc->clk_prepare;
+	int rc = 0;
+	u64 dividend, temp, temp_multiple;
+	s32 frac = 0;
+	s64 intermediate;
+	s64 clk_prep_actual;
+
+	dividend = ((t->rec_max - t->rec_min) * min_prepare_frac * multiplier);
+	temp  = roundup(div_s64(dividend, 100), multiplier);
+	temp += (t->rec_min * multiplier);
+	t->rec = div_s64(temp, multiplier);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor clk_prepare\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	/* calculate theoretical value */
+	temp_multiple = 8 * t->reg_value * clk_params->tlpx_numer_ns
+			 * multiplier;
+	intermediate = div_s64(temp_multiple, clk_params->bitclk_mbps);
+	div_s64_rem(temp_multiple, clk_params->bitclk_mbps, &frac);
+	clk_prep_actual = div_s64((intermediate + frac), multiplier);
+
+	pr_debug("CLK_PREPARE:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max);
+	pr_debug(" reg_value=%d, actual=%lld\n", t->reg_value, clk_prep_actual);
+
+	*actual_frac = frac;
+	*actual_intermediate = intermediate;
+
+	return rc;
+}
+
+/**
+ * calc_clk_zero - calculates zero timing params for clk lane.
+ */
+static int calc_clk_zero(struct phy_clk_params *clk_params,
+			 struct phy_timing_desc *desc,
+			 s32 actual_frac,
+			 s64 actual_intermediate)
+{
+	u32 const clk_zero_min_frac = 2;
+	u64 const multiplier = BIT(20);
+
+	int rc = 0;
+	struct timing_entry *t = &desc->clk_zero;
+	s64 mipi_min, rec_temp1, rec_temp2, rec_temp3, rec_min;
+
+	mipi_min = ((300 * multiplier) - (actual_intermediate + actual_frac));
+	t->mipi_min = div_s64(mipi_min, multiplier);
+
+	rec_temp1 = div_s64((mipi_min * clk_params->bitclk_mbps),
+			    clk_params->tlpx_numer_ns);
+	rec_temp2 = (rec_temp1 - (11 * multiplier));
+	rec_temp3 = roundup(div_s64(rec_temp2, 8), multiplier);
+	rec_min = (div_s64(rec_temp3, multiplier) - 3);
+	t->rec_min = rec_min;
+	t->rec_max = ((t->rec_min > 255) ? 511 : 255);
+
+	t->rec = DIV_ROUND_UP(
+			(((t->rec_max - t->rec_min) * clk_zero_min_frac) +
+			 (t->rec_min * 100)),
+			100);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor clk_zero\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("CLK_ZERO:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+	return rc;
+}
+
+/**
+ * calc_clk_trail - calculates prepare trail params for clk lane.
+ */
+static int calc_clk_trail(struct phy_clk_params *clk_params,
+			  struct phy_timing_desc *desc,
+			  s64 *teot_clk_lane)
+{
+	u64 const multiplier = BIT(20);
+	u32 const phy_timing_frac = 30;
+
+	int rc = 0;
+	struct timing_entry *t = &desc->clk_trail;
+	u64 temp_multiple;
+	s32 frac;
+	s64 mipi_max_tr, rec_temp1, rec_temp2, rec_temp3, mipi_max;
+	s64 teot_clk_lane1;
+
+	temp_multiple = div_s64(
+			(12 * multiplier * clk_params->tlpx_numer_ns),
+			clk_params->bitclk_mbps);
+	div_s64_rem(temp_multiple, multiplier, &frac);
+
+	mipi_max_tr = ((105 * multiplier) +
+		       (temp_multiple + frac));
+	teot_clk_lane1 = div_s64(mipi_max_tr, multiplier);
+
+	mipi_max = (mipi_max_tr - (clk_params->treot_ns * multiplier));
+	t->mipi_max = div_s64(mipi_max, multiplier);
+
+	temp_multiple = div_s64(
+			(t->mipi_min * multiplier * clk_params->bitclk_mbps),
+			clk_params->tlpx_numer_ns);
+
+	div_s64_rem(temp_multiple, multiplier, &frac);
+	rec_temp1 = temp_multiple + frac + (3 * multiplier);
+	rec_temp2 = div_s64(rec_temp1, 8);
+	rec_temp3 = roundup(rec_temp2, multiplier);
+
+	t->rec_min = div_s64(rec_temp3, multiplier);
+
+	/* recommended max */
+	rec_temp1 = div_s64((mipi_max * clk_params->bitclk_mbps),
+			    clk_params->tlpx_numer_ns);
+	rec_temp2 = rec_temp1 + (3 * multiplier);
+	rec_temp3 = rec_temp2 / 8;
+	t->rec_max = div_s64(rec_temp3, multiplier);
+
+	t->rec = DIV_ROUND_UP(
+		(((t->rec_max - t->rec_min) * phy_timing_frac) +
+		 (t->rec_min * 100)),
+		 100);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor clk_zero\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	*teot_clk_lane = teot_clk_lane1;
+	pr_debug("CLK_TRAIL:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+	return rc;
+
+}
+
+/**
+ * calc_hs_prepare - calculates prepare timing params for data lanes in HS.
+ */
+static int calc_hs_prepare(struct phy_clk_params *clk_params,
+			   struct phy_timing_desc *desc,
+			   u64 *temp_mul)
+{
+	u64 const multiplier = BIT(20);
+	u32 const min_prepare_frac = 50;
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_prepare;
+	u64 temp_multiple, dividend, temp;
+	s32 frac;
+	s64 rec_temp1, rec_temp2, mipi_max, mipi_min;
+	u32 low_clk_multiplier = 0;
+
+	if (clk_params->bitclk_mbps <= 120)
+		low_clk_multiplier = 2;
+	/* mipi min */
+	temp_multiple = div_s64((4 * multiplier * clk_params->tlpx_numer_ns),
+				clk_params->bitclk_mbps);
+	div_s64_rem(temp_multiple, multiplier, &frac);
+	mipi_min = (40 * multiplier) + (temp_multiple + frac);
+	t->mipi_min = div_s64(mipi_min, multiplier);
+
+	/* mipi_max */
+	temp_multiple = div_s64(
+			(6 * multiplier * clk_params->tlpx_numer_ns),
+			clk_params->bitclk_mbps);
+	div_s64_rem(temp_multiple, multiplier, &frac);
+	mipi_max = (85 * multiplier) + temp_multiple;
+	t->mipi_max = div_s64(mipi_max, multiplier);
+
+	/* recommended min */
+	temp_multiple = div_s64((mipi_min * clk_params->bitclk_mbps),
+				clk_params->tlpx_numer_ns);
+	temp_multiple -= (low_clk_multiplier * multiplier);
+	div_s64_rem(temp_multiple, multiplier, &frac);
+	rec_temp1 = roundup(((temp_multiple + frac) / 8), multiplier);
+	t->rec_min = div_s64(rec_temp1, multiplier);
+
+	/* recommended max */
+	temp_multiple = div_s64((mipi_max * clk_params->bitclk_mbps),
+				clk_params->tlpx_numer_ns);
+	temp_multiple -= (low_clk_multiplier * multiplier);
+	div_s64_rem(temp_multiple, multiplier, &frac);
+	rec_temp2 = rounddown((temp_multiple / 8), multiplier);
+	t->rec_max = div_s64(rec_temp2, multiplier);
+
+	/* register value */
+	dividend = ((rec_temp2 - rec_temp1) * min_prepare_frac);
+	temp = roundup(div_u64(dividend, 100), multiplier);
+	t->rec = div_s64((temp + rec_temp1), multiplier);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_prepare\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	temp_multiple = div_s64(
+			(8 * (temp + rec_temp1) * clk_params->tlpx_numer_ns),
+			clk_params->bitclk_mbps);
+
+	*temp_mul = temp_multiple;
+	pr_debug("HS_PREP:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+	return rc;
+}
+
+/**
+ * calc_hs_zero - calculates zero timing params for data lanes in HS.
+ */
+static int calc_hs_zero(struct phy_clk_params *clk_params,
+			struct phy_timing_desc *desc,
+			u64 temp_multiple)
+{
+	u32 const hs_zero_min_frac = 10;
+	u64 const multiplier = BIT(20);
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_zero;
+	s64 rec_temp1, rec_temp2, rec_temp3, mipi_min;
+	s64 rec_min;
+
+	mipi_min = div_s64((10 * clk_params->tlpx_numer_ns * multiplier),
+			   clk_params->bitclk_mbps);
+	rec_temp1 = (145 * multiplier) + mipi_min - temp_multiple;
+	t->mipi_min = div_s64(rec_temp1, multiplier);
+
+	/* recommended min */
+	rec_temp1 = div_s64((rec_temp1 * clk_params->bitclk_mbps),
+			    clk_params->tlpx_numer_ns);
+	rec_temp2 = rec_temp1 - (11 * multiplier);
+	rec_temp3 = roundup((rec_temp2 / 8), multiplier);
+	rec_min = rec_temp3 - (3 * multiplier);
+	t->rec_min =  div_s64(rec_min, multiplier);
+	t->rec_max = ((t->rec_min > 255) ? 511 : 255);
+
+	t->rec = DIV_ROUND_UP(
+			(((t->rec_max - t->rec_min) * hs_zero_min_frac) +
+			 (t->rec_min * 100)),
+			100);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_zero\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("HS_ZERO:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+
+	return rc;
+}
+
+/**
+ * calc_hs_trail - calculates trail timing params for data lanes in HS.
+ */
+static int calc_hs_trail(struct phy_clk_params *clk_params,
+			 struct phy_timing_desc *desc,
+			 u64 teot_clk_lane)
+{
+	u32 const phy_timing_frac = 30;
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_trail;
+	s64 rec_temp1;
+
+	t->mipi_min = 60 +
+			mult_frac(clk_params->tlpx_numer_ns, 4,
+				  clk_params->bitclk_mbps);
+
+	t->mipi_max = teot_clk_lane - clk_params->treot_ns;
+
+	t->rec_min = DIV_ROUND_UP(
+		((t->mipi_min * clk_params->bitclk_mbps) +
+		 (3 * clk_params->tlpx_numer_ns)),
+		(8 * clk_params->tlpx_numer_ns));
+
+	rec_temp1 = ((t->mipi_max * clk_params->bitclk_mbps) +
+		     (3 * clk_params->tlpx_numer_ns));
+	t->rec_max = (rec_temp1 / (8 * clk_params->tlpx_numer_ns));
+	rec_temp1 = DIV_ROUND_UP(
+			((t->rec_max - t->rec_min) * phy_timing_frac),
+			100);
+	t->rec = rec_temp1 + t->rec_min;
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_trail\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("HS_TRAIL:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+
+	return rc;
+}
+
+/**
+ * calc_hs_rqst - calculates rqst timing params for data lanes in HS.
+ */
+static int calc_hs_rqst(struct phy_clk_params *clk_params,
+			struct phy_timing_desc *desc)
+{
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_rqst;
+
+	t->rec = DIV_ROUND_UP(
+		((t->mipi_min * clk_params->bitclk_mbps) -
+		 (8 * clk_params->tlpx_numer_ns)),
+		(8 * clk_params->tlpx_numer_ns));
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_rqst, %d\n", t->rec);
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("HS_RQST:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+
+	return rc;
+}
+
+/**
+ * calc_hs_exit - calculates exit timing params for data lanes in HS.
+ */
+static int calc_hs_exit(struct phy_clk_params *clk_params,
+			struct phy_timing_desc *desc)
+{
+	u32 const hs_exit_min_frac = 10;
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_exit;
+
+	t->rec_min = (DIV_ROUND_UP(
+			(t->mipi_min * clk_params->bitclk_mbps),
+			(8 * clk_params->tlpx_numer_ns)) - 1);
+
+	t->rec = DIV_ROUND_UP(
+		(((t->rec_max - t->rec_min) * hs_exit_min_frac) +
+		 (t->rec_min * 100)),
+		100);
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_exit\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("HS_EXIT:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+
+	return rc;
+}
+
+/**
+ * calc_hs_rqst_clk - calculates rqst timing params for clock lane..
+ */
+static int calc_hs_rqst_clk(struct phy_clk_params *clk_params,
+			    struct phy_timing_desc *desc)
+{
+	int rc = 0;
+	struct timing_entry *t = &desc->hs_rqst_clk;
+
+	t->rec = DIV_ROUND_UP(
+		((t->mipi_min * clk_params->bitclk_mbps) -
+		 (8 * clk_params->tlpx_numer_ns)),
+		(8 * clk_params->tlpx_numer_ns));
+
+	if (t->rec & 0xffffff00) {
+		pr_err("Incorrect rec valuefor hs_rqst_clk\n");
+		rc = -EINVAL;
+	} else {
+		t->reg_value = t->rec;
+	}
+
+	pr_debug("HS_RQST_CLK:mipi_min=%d, mipi_max=%d, rec_min=%d, rec_max=%d, reg_val=%d\n",
+		 t->mipi_min, t->mipi_max, t->rec_min, t->rec_max,
+		 t->reg_value);
+
+	return rc;
+}
+
+/**
+ * dsi_phy_calc_timing_params - calculates timing paramets for a given bit clock
+ */
+static int dsi_phy_calc_timing_params(struct phy_clk_params *clk_params,
+				      struct phy_timing_desc *desc)
+{
+	int rc = 0;
+	s32 actual_frac = 0;
+	s64 actual_intermediate = 0;
+	u64 temp_multiple;
+	s64 teot_clk_lane;
+
+	rc = calc_clk_prepare(clk_params, desc, &actual_frac,
+			      &actual_intermediate);
+	if (rc) {
+		pr_err("clk_prepare calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_clk_zero(clk_params, desc, actual_frac, actual_intermediate);
+	if (rc) {
+		pr_err("clk_zero calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_clk_trail(clk_params, desc, &teot_clk_lane);
+	if (rc) {
+		pr_err("clk_trail calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_prepare(clk_params, desc, &temp_multiple);
+	if (rc) {
+		pr_err("hs_prepare calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_zero(clk_params, desc, temp_multiple);
+	if (rc) {
+		pr_err("hs_zero calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_trail(clk_params, desc, teot_clk_lane);
+	if (rc) {
+		pr_err("hs_trail calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_rqst(clk_params, desc);
+	if (rc) {
+		pr_err("hs_rqst calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_exit(clk_params, desc);
+	if (rc) {
+		pr_err("hs_exit calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = calc_hs_rqst_clk(clk_params, desc);
+	if (rc) {
+		pr_err("hs_rqst_clk calculations failed, rc=%d\n", rc);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+/**
+ * calculate_timing_params() - calculates timing parameters.
+ * @phy:      Pointer to DSI PHY hardware object.
+ * @mode:     Mode information for which timing has to be calculated.
+ * @config:   DSI host configuration for this mode.
+ * @timing:   Timing parameters for each lane which will be returned.
+ */
+int dsi_phy_hw_v4_0_calculate_timing_params(struct dsi_phy_hw *phy,
+					    struct dsi_mode_info *mode,
+					    struct dsi_host_common_cfg *host,
+					   struct dsi_phy_per_lane_cfgs *timing)
+{
+	/* constants */
+	u32 const esc_clk_mhz = 192; /* TODO: esc clock is hardcoded */
+	u32 const esc_clk_mmss_cc_prediv = 10;
+	u32 const tlpx_numer = 1000;
+	u32 const tr_eot = 20;
+	u32 const clk_prepare_spec_min = 38;
+	u32 const clk_prepare_spec_max = 95;
+	u32 const clk_trail_spec_min = 60;
+	u32 const hs_exit_spec_min = 100;
+	u32 const hs_exit_reco_max = 255;
+	u32 const hs_rqst_spec_min = 50;
+
+	/* local vars */
+	int rc = 0;
+	int i;
+	u32 h_total, v_total;
+	u64 inter_num;
+	u32 num_of_lanes = 0;
+	u32 bpp;
+	u64 x, y;
+	struct phy_timing_desc desc;
+	struct phy_clk_params clk_params = {0};
+
+	memset(&desc, 0x0, sizeof(desc));
+	h_total = DSI_H_TOTAL(mode);
+	v_total = DSI_V_TOTAL(mode);
+
+	bpp = bits_per_pixel[host->dst_format];
+
+	inter_num = bpp * mode->refresh_rate;
+
+	if (host->data_lanes & DSI_DATA_LANE_0)
+		num_of_lanes++;
+	if (host->data_lanes & DSI_DATA_LANE_1)
+		num_of_lanes++;
+	if (host->data_lanes & DSI_DATA_LANE_2)
+		num_of_lanes++;
+	if (host->data_lanes & DSI_DATA_LANE_3)
+		num_of_lanes++;
+
+
+	x = mult_frac(v_total * h_total, inter_num, num_of_lanes);
+	y = rounddown(x, 1);
+
+	clk_params.bitclk_mbps = rounddown(mult_frac(y, 1, 1000000), 1);
+	clk_params.escclk_numer = esc_clk_mhz;
+	clk_params.escclk_denom = esc_clk_mmss_cc_prediv;
+	clk_params.tlpx_numer_ns = tlpx_numer;
+	clk_params.treot_ns = tr_eot;
+
+
+	/* Setup default parameters */
+	desc.clk_prepare.mipi_min = clk_prepare_spec_min;
+	desc.clk_prepare.mipi_max = clk_prepare_spec_max;
+	desc.clk_trail.mipi_min = clk_trail_spec_min;
+	desc.hs_exit.mipi_min = hs_exit_spec_min;
+	desc.hs_exit.rec_max = hs_exit_reco_max;
+
+	desc.clk_prepare.rec_min = DIV_ROUND_UP(
+			(desc.clk_prepare.mipi_min * clk_params.bitclk_mbps),
+			(8 * clk_params.tlpx_numer_ns)
+			);
+
+	desc.clk_prepare.rec_max = rounddown(
+		mult_frac((desc.clk_prepare.mipi_max * clk_params.bitclk_mbps),
+			  1, (8 * clk_params.tlpx_numer_ns)),
+		1);
+
+	desc.hs_rqst.mipi_min = hs_rqst_spec_min;
+	desc.hs_rqst_clk.mipi_min = hs_rqst_spec_min;
+
+	pr_debug("BIT CLOCK = %d, tlpx_numer_ns=%d, treot_ns=%d\n",
+	       clk_params.bitclk_mbps, clk_params.tlpx_numer_ns,
+	       clk_params.treot_ns);
+	rc = dsi_phy_calc_timing_params(&clk_params, &desc);
+	if (rc) {
+		pr_err("Timing calc failed, rc=%d\n", rc);
+		goto error;
+	}
+
+
+	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+		timing->lane[i][0] = desc.hs_exit.reg_value;
+
+		if (i == DSI_LOGICAL_CLOCK_LANE)
+			timing->lane[i][1] = desc.clk_zero.reg_value;
+		else
+			timing->lane[i][1] = desc.hs_zero.reg_value;
+
+		if (i == DSI_LOGICAL_CLOCK_LANE)
+			timing->lane[i][2] = desc.clk_prepare.reg_value;
+		else
+			timing->lane[i][2] = desc.hs_prepare.reg_value;
+
+		if (i == DSI_LOGICAL_CLOCK_LANE)
+			timing->lane[i][3] = desc.clk_trail.reg_value;
+		else
+			timing->lane[i][3] = desc.hs_trail.reg_value;
+
+		if (i == DSI_LOGICAL_CLOCK_LANE)
+			timing->lane[i][4] = desc.hs_rqst_clk.reg_value;
+		else
+			timing->lane[i][4] = desc.hs_rqst.reg_value;
+
+		timing->lane[i][5] = 0x3;
+		timing->lane[i][6] = 0x4;
+		timing->lane[i][7] = 0xA0;
+		pr_debug("[%d][%d %d %d %d %d]\n", i, timing->lane[i][0],
+						    timing->lane[i][1],
+						    timing->lane[i][2],
+						    timing->lane[i][3],
+						    timing->lane[i][4]);
+	}
+	timing->count_per_lane = 8;
+
+error:
+	return rc;
+}
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 1f4a95eeb348190a01aaa05207abc9c20679982a..ba5921149ac38f006f463c4c85137c520ac3ab39 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2016 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -56,7 +56,7 @@ static irqreturn_t hdmi_irq(int irq, void *dev_id)
 
 	/* Process HDCP: */
 	if (hdmi->hdcp_ctrl)
-		hdmi_hdcp_irq(hdmi->hdcp_ctrl);
+		hdmi_hdcp_ctrl_irq(hdmi->hdcp_ctrl);
 
 	/* TODO audio.. */
 
@@ -75,7 +75,8 @@ static void hdmi_destroy(struct hdmi *hdmi)
 		flush_workqueue(hdmi->workq);
 		destroy_workqueue(hdmi->workq);
 	}
-	hdmi_hdcp_destroy(hdmi);
+
+	hdmi_hdcp_ctrl_destroy(hdmi);
 	if (phy)
 		phy->funcs->destroy(phy);
 
@@ -228,7 +229,7 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
 		goto fail;
 	}
 
-	hdmi->hdcp_ctrl = hdmi_hdcp_init(hdmi);
+	hdmi->hdcp_ctrl = hdmi_hdcp_ctrl_init(hdmi);
 	if (IS_ERR(hdmi->hdcp_ctrl)) {
 		dev_warn(&pdev->dev, "failed to init hdcp: disabled\n");
 		hdmi->hdcp_ctrl = NULL;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index d0e663192d01f6b3471f8ef578bc16a2e538cd10..e22ddcd51248f2c0d147aed835af4d809a6d4a8b 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -187,10 +187,10 @@ struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi);
 /*
  * hdcp
  */
-struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi);
-void hdmi_hdcp_destroy(struct hdmi *hdmi);
-void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
-void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
-void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
+struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi);
+void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi);
+void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
+void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
+void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
 
 #endif /* __HDMI_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 92b69ae8caf9c41c9c6cb80249ed726faafde5f8..5b6a90abd108bd6ef716cf79131725a0c9e94206 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -106,7 +106,7 @@ static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
 	hdmi_set_mode(hdmi, true);
 
 	if (hdmi->hdcp_ctrl)
-		hdmi_hdcp_on(hdmi->hdcp_ctrl);
+		hdmi_hdcp_ctrl_on(hdmi->hdcp_ctrl);
 }
 
 static void hdmi_bridge_enable(struct drm_bridge *bridge)
@@ -124,7 +124,7 @@ static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
 	struct hdmi_phy *phy = hdmi->phy;
 
 	if (hdmi->hdcp_ctrl)
-		hdmi_hdcp_off(hdmi->hdcp_ctrl);
+		hdmi_hdcp_ctrl_off(hdmi->hdcp_ctrl);
 
 	DBG("power down");
 	hdmi_set_mode(hdmi, false);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
index 1dc9c34eb0df2867a5c018f3bbbad0b6bfa8f8c1..e56a8675c0a4c57e4e017ae7b310e9d920e49c5f 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -14,6 +14,7 @@
 #include "hdmi.h"
 #include <linux/qcom_scm.h>
 
+#ifdef CONFIG_DRM_MSM_HDCP
 #define HDCP_REG_ENABLE 0x01
 #define HDCP_REG_DISABLE 0x00
 #define HDCP_PORT_ADDR 0x74
@@ -202,7 +203,7 @@ static int hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg,
 	return ret;
 }
 
-void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
 {
 	struct hdmi *hdmi = hdcp_ctrl->hdmi;
 	u32 reg_val, hdcp_int_status;
@@ -1310,7 +1311,7 @@ end:
 	}
 }
 
-void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
 {
 	struct hdmi *hdmi = hdcp_ctrl->hdmi;
 	u32 reg_val;
@@ -1335,7 +1336,7 @@ void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
 	queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work);
 }
 
-void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
 {
 	struct hdmi *hdmi = hdcp_ctrl->hdmi;
 	unsigned long flags;
@@ -1399,7 +1400,7 @@ void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
 	DBG("HDCP: Off");
 }
 
-struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi)
+struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi)
 {
 	struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL;
 
@@ -1428,10 +1429,33 @@ struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi)
 	return hdcp_ctrl;
 }
 
-void hdmi_hdcp_destroy(struct hdmi *hdmi)
+void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi)
 {
 	if (hdmi && hdmi->hdcp_ctrl) {
 		kfree(hdmi->hdcp_ctrl);
 		hdmi->hdcp_ctrl = NULL;
 	}
 }
+
+#else
+struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi)
+{
+	return NULL;
+}
+
+void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi)
+{
+}
+
+void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+{
+}
+
+void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+{
+}
+
+void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
+{
+}
+#endif
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index b532faa8026d95079dc2cf19ad0aef0f97782849..f7aebf5516ce990e3fbd384ae2d6639f96fad40e 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -595,7 +595,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 	mdelay(16);
 
 	if (config->platform.iommu) {
-		mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
+		mmu = msm_smmu_new(&pdev->dev,
+				MSM_SMMU_DOMAIN_UNSECURE);
 		if (IS_ERR(mmu)) {
 			ret = PTR_ERR(mmu);
 			dev_err(dev->dev, "failed to init iommu: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c b/drivers/gpu/drm/msm/mdp/mdp_format.c
index 1c2caffc97e400b650b96a3e554fb5fe25d312a8..d2fa728158335f3f3f1b7b325b7f31a2c5f9c86d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2016 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -165,7 +165,11 @@ uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats,
 	return i;
 }
 
-const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format)
+const struct msm_format *mdp_get_format(
+		struct msm_kms *kms,
+		uint32_t format,
+		const uint64_t *modifiers,
+		uint32_t modifiers_len)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(formats); i++) {
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h
index 30313032074845c4602a9feae9c8a3d5f76c2b07..0d0723d32a03c29d4a88f92843dd85c0eb13938a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h
@@ -98,7 +98,9 @@ struct mdp_format {
 #define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
 
 uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
-const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
+const struct msm_format *mdp_get_format(struct msm_kms *kms,
+		uint32_t format, const uint64_t *modifiers,
+		uint32_t modifiers_len);
 
 /* MDP capabilities */
 #define MDP_CAP_SMP		BIT(0)	/* Shared Memory Pool                 */
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 7eb253bc24df3156b75f6409f6b9a9df184b66ae..d8791155236c8091bb41bd9fce81ea5b99fe2e1b 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
  * Copyright (C) 2014 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -25,10 +26,9 @@ struct msm_commit {
 	uint32_t fence;
 	struct msm_fence_cb fence_cb;
 	uint32_t crtc_mask;
+	struct kthread_work commit_work;
 };
 
-static void fence_cb(struct msm_fence_cb *cb);
-
 /* block until specified crtcs are no longer pending update, and
  * atomically mark them as pending update
  */
@@ -59,75 +59,351 @@ static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
 	spin_unlock(&priv->pending_crtcs_event.lock);
 }
 
-static struct msm_commit *commit_init(struct drm_atomic_state *state)
+static void commit_destroy(struct msm_commit *commit)
+{
+	end_atomic(commit->dev->dev_private, commit->crtc_mask);
+	kfree(commit);
+}
+
+static void msm_atomic_wait_for_commit_done(
+		struct drm_device *dev,
+		struct drm_atomic_state *old_state,
+		int modeset_flags)
 {
-	struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL);
+	struct drm_crtc *crtc;
+	struct msm_drm_private *priv = old_state->dev->dev_private;
+	struct msm_kms *kms = priv->kms;
+	int ncrtcs = old_state->dev->mode_config.num_crtc;
+	int i;
 
-	if (!c)
-		return NULL;
+	for (i = 0; i < ncrtcs; i++) {
+		int private_flags;
 
-	c->dev = state->dev;
-	c->state = state;
+		crtc = old_state->crtcs[i];
 
-	/* TODO we might need a way to indicate to run the cb on a
-	 * different wq so wait_for_vblanks() doesn't block retiring
-	 * bo's..
-	 */
-	INIT_FENCE_CB(&c->fence_cb, fence_cb);
+		if (!crtc || !crtc->state || !crtc->state->enable)
+			continue;
+
+		/* If specified, only wait if requested flag is true */
+		private_flags = crtc->state->adjusted_mode.private_flags;
+		if (modeset_flags && !(modeset_flags & private_flags))
+			continue;
+
+		/* Legacy cursor ioctls are completely unsynced, and userspace
+		 * relies on that (by doing tons of cursor updates). */
+		if (old_state->legacy_cursor_update)
+			continue;
 
-	return c;
+		if (kms->funcs->wait_for_crtc_commit_done)
+			kms->funcs->wait_for_crtc_commit_done(kms, crtc);
+	}
 }
 
-static void commit_destroy(struct msm_commit *c)
+static void
+msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
 {
-	end_atomic(c->dev->dev_private, c->crtc_mask);
-	kfree(c);
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state;
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *old_crtc_state;
+	int i;
+
+	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
+		const struct drm_encoder_helper_funcs *funcs;
+		struct drm_encoder *encoder;
+		struct drm_crtc_state *old_crtc_state;
+		unsigned int crtc_idx;
+
+		/*
+		 * Shut down everything that's in the changeset and currently
+		 * still on. So need to check the old, saved state.
+		 */
+		if (!old_conn_state->crtc)
+			continue;
+
+		crtc_idx = drm_crtc_index(old_conn_state->crtc);
+		old_crtc_state = old_state->crtc_states[crtc_idx];
+
+		if (!old_crtc_state->active ||
+		    !drm_atomic_crtc_needs_modeset(old_conn_state->crtc->state))
+			continue;
+
+		encoder = old_conn_state->best_encoder;
+
+		/* We shouldn't get this far if we didn't previously have
+		 * an encoder.. but WARN_ON() rather than explode.
+		 */
+		if (WARN_ON(!encoder))
+			continue;
+
+		if (msm_is_mode_seamless(
+				&connector->encoder->crtc->state->mode))
+			continue;
+
+		funcs = encoder->helper_private;
+
+		DRM_DEBUG_ATOMIC("disabling [ENCODER:%d:%s]\n",
+				 encoder->base.id, encoder->name);
+
+		/*
+		 * Each encoder has at most one connector (since we always steal
+		 * it away), so we won't call disable hooks twice.
+		 */
+		drm_bridge_disable(encoder->bridge);
+
+		/* Right function depends upon target state. */
+		if (connector->state->crtc && funcs->prepare)
+			funcs->prepare(encoder);
+		else if (funcs->disable)
+			funcs->disable(encoder);
+		else
+			funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
+
+		drm_bridge_post_disable(encoder->bridge);
+	}
+
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+		const struct drm_crtc_helper_funcs *funcs;
+
+		/* Shut down everything that needs a full modeset. */
+		if (!drm_atomic_crtc_needs_modeset(crtc->state))
+			continue;
+
+		if (!old_crtc_state->active)
+			continue;
+
+		if (msm_is_mode_seamless(&crtc->state->mode))
+			continue;
+
+		funcs = crtc->helper_private;
+
+		DRM_DEBUG_ATOMIC("disabling [CRTC:%d]\n",
+				 crtc->base.id);
+
+		/* Right function depends upon target state. */
+		if (crtc->state->enable && funcs->prepare)
+			funcs->prepare(crtc);
+		else if (funcs->disable)
+			funcs->disable(crtc);
+		else
+			funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+	}
 }
 
-static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
+static void
+msm_crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
+{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *old_crtc_state;
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state;
+	int i;
+
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+		const struct drm_crtc_helper_funcs *funcs;
+
+		if (!crtc->state->mode_changed)
+			continue;
+
+		funcs = crtc->helper_private;
+
+		if (crtc->state->enable && funcs->mode_set_nofb) {
+			DRM_DEBUG_ATOMIC("modeset on [CRTC:%d]\n",
+					 crtc->base.id);
+
+			funcs->mode_set_nofb(crtc);
+		}
+	}
+
+	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
+		const struct drm_encoder_helper_funcs *funcs;
+		struct drm_crtc_state *new_crtc_state;
+		struct drm_encoder *encoder;
+		struct drm_display_mode *mode, *adjusted_mode;
+
+		if (!connector->state->best_encoder)
+			continue;
+
+		encoder = connector->state->best_encoder;
+		funcs = encoder->helper_private;
+		new_crtc_state = connector->state->crtc->state;
+		mode = &new_crtc_state->mode;
+		adjusted_mode = &new_crtc_state->adjusted_mode;
+
+		if (!new_crtc_state->mode_changed)
+			continue;
+
+		DRM_DEBUG_ATOMIC("modeset on [ENCODER:%d:%s]\n",
+				 encoder->base.id, encoder->name);
+
+		/*
+		 * Each encoder has at most one connector (since we always steal
+		 * it away), so we won't call mode_set hooks twice.
+		 */
+		if (funcs->mode_set)
+			funcs->mode_set(encoder, mode, adjusted_mode);
+
+		drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode);
+	}
+}
+
+/**
+ * msm_atomic_helper_commit_modeset_disables - modeset commit to disable outputs
+ * @dev: DRM device
+ * @old_state: atomic state object with old state structures
+ *
+ * This function shuts down all the outputs that need to be shut down and
+ * prepares them (if required) with the new mode.
+ *
+ * For compatibility with legacy crtc helpers this should be called before
+ * drm_atomic_helper_commit_planes(), which is what the default commit function
+ * does. But drivers with different needs can group the modeset commits together
+ * and do the plane commits at the end. This is useful for drivers doing runtime
+ * PM since planes updates then only happen when the CRTC is actually enabled.
+ */
+static void msm_atomic_helper_commit_modeset_disables(struct drm_device *dev,
+		struct drm_atomic_state *old_state)
+{
+	msm_disable_outputs(dev, old_state);
+
+	drm_atomic_helper_update_legacy_modeset_state(dev, old_state);
+
+	msm_crtc_set_mode(dev, old_state);
+}
+
+/**
+ * msm_atomic_helper_commit_modeset_enables - modeset commit to enable outputs
+ * @dev: DRM device
+ * @old_state: atomic state object with old state structures
+ *
+ * This function enables all the outputs with the new configuration which had to
+ * be turned off for the update.
+ *
+ * For compatibility with legacy crtc helpers this should be called after
+ * drm_atomic_helper_commit_planes(), which is what the default commit function
+ * does. But drivers with different needs can group the modeset commits together
+ * and do the plane commits at the end. This is useful for drivers doing runtime
+ * PM since planes updates then only happen when the CRTC is actually enabled.
+ */
+static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev,
 		struct drm_atomic_state *old_state)
 {
 	struct drm_crtc *crtc;
-	struct msm_drm_private *priv = old_state->dev->dev_private;
+	struct drm_crtc_state *old_crtc_state;
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state;
+	struct msm_drm_private *priv = dev->dev_private;
 	struct msm_kms *kms = priv->kms;
-	int ncrtcs = old_state->dev->mode_config.num_crtc;
+	int bridge_enable_count = 0;
 	int i;
 
-	for (i = 0; i < ncrtcs; i++) {
-		crtc = old_state->crtcs[i];
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+		const struct drm_crtc_helper_funcs *funcs;
 
-		if (!crtc)
+		/* Need to filter out CRTCs where only planes change. */
+		if (!drm_atomic_crtc_needs_modeset(crtc->state))
 			continue;
 
-		if (!crtc->state->enable)
+		if (!crtc->state->active)
 			continue;
 
-		/* Legacy cursor ioctls are completely unsynced, and userspace
-		 * relies on that (by doing tons of cursor updates). */
-		if (old_state->legacy_cursor_update)
+		if (msm_is_mode_seamless(&crtc->state->mode))
+			continue;
+
+		funcs = crtc->helper_private;
+
+		if (crtc->state->enable) {
+			DRM_DEBUG_ATOMIC("enabling [CRTC:%d]\n",
+					 crtc->base.id);
+
+			if (funcs->enable)
+				funcs->enable(crtc);
+			else
+				funcs->commit(crtc);
+		}
+	}
+
+	/* ensure bridge/encoder updates happen on same vblank */
+	msm_atomic_wait_for_commit_done(dev, old_state,
+			MSM_MODE_FLAG_VBLANK_PRE_MODESET);
+
+	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
+		const struct drm_encoder_helper_funcs *funcs;
+		struct drm_encoder *encoder;
+
+		if (!connector->state->best_encoder)
+			continue;
+
+		if (!connector->state->crtc->state->active ||
+		    !drm_atomic_crtc_needs_modeset(
+				    connector->state->crtc->state))
+			continue;
+
+		encoder = connector->state->best_encoder;
+		funcs = encoder->helper_private;
+
+		DRM_DEBUG_ATOMIC("enabling [ENCODER:%d:%s]\n",
+				 encoder->base.id, encoder->name);
+
+		/*
+		 * Each encoder has at most one connector (since we always steal
+		 * it away), so we won't call enable hooks twice.
+		 */
+		drm_bridge_pre_enable(encoder->bridge);
+		++bridge_enable_count;
+
+		if (funcs->enable)
+			funcs->enable(encoder);
+		else
+			funcs->commit(encoder);
+	}
+
+	if (kms->funcs->commit) {
+		DRM_DEBUG_ATOMIC("triggering commit\n");
+		kms->funcs->commit(kms, old_state);
+	}
+
+	/* If no bridges were pre_enabled, skip iterating over them again */
+	if (bridge_enable_count == 0)
+		return;
+
+	for_each_connector_in_state(old_state, connector, old_conn_state, i) {
+		struct drm_encoder *encoder;
+
+		if (!connector->state->best_encoder)
+			continue;
+
+		if (!connector->state->crtc->state->active ||
+		    !drm_atomic_crtc_needs_modeset(
+				    connector->state->crtc->state))
 			continue;
 
-		kms->funcs->wait_for_crtc_commit_done(kms, crtc);
+		encoder = connector->state->best_encoder;
+
+		DRM_DEBUG_ATOMIC("bridge enable enabling [ENCODER:%d:%s]\n",
+				 encoder->base.id, encoder->name);
+
+		drm_bridge_enable(encoder->bridge);
 	}
 }
 
 /* The (potentially) asynchronous part of the commit.  At this point
  * nothing can fail short of armageddon.
  */
-static void complete_commit(struct msm_commit *c)
+static void complete_commit(struct msm_commit *commit)
 {
-	struct drm_atomic_state *state = c->state;
+	struct drm_atomic_state *state = commit->state;
 	struct drm_device *dev = state->dev;
 	struct msm_drm_private *priv = dev->dev_private;
 	struct msm_kms *kms = priv->kms;
 
 	kms->funcs->prepare_commit(kms, state);
 
-	drm_atomic_helper_commit_modeset_disables(dev, state);
+	msm_atomic_helper_commit_modeset_disables(dev, state);
 
 	drm_atomic_helper_commit_planes(dev, state, false);
 
-	drm_atomic_helper_commit_modeset_enables(dev, state);
+	msm_atomic_helper_commit_modeset_enables(dev, state);
 
 	/* NOTE: _wait_for_vblanks() only waits for vblank on
 	 * enabled CRTCs.  So we end up faulting when disabling
@@ -142,7 +418,7 @@ static void complete_commit(struct msm_commit *c)
 	 * not be critical path)
 	 */
 
-	msm_atomic_wait_for_commit_done(dev, state);
+	msm_atomic_wait_for_commit_done(dev, state, 0);
 
 	drm_atomic_helper_cleanup_planes(dev, state);
 
@@ -150,38 +426,97 @@ static void complete_commit(struct msm_commit *c)
 
 	drm_atomic_state_free(state);
 
-	commit_destroy(c);
+	commit_destroy(commit);
 }
 
 static void fence_cb(struct msm_fence_cb *cb)
 {
-	struct msm_commit *c =
+	struct msm_commit *commit =
 			container_of(cb, struct msm_commit, fence_cb);
-	complete_commit(c);
+	complete_commit(commit);
 }
 
-static void add_fb(struct msm_commit *c, struct drm_framebuffer *fb)
+static void _msm_drm_commit_work_cb(struct kthread_work *work)
 {
-	struct drm_gem_object *obj = msm_framebuffer_bo(fb, 0);
-	c->fence = max(c->fence, msm_gem_fence(to_msm_bo(obj), MSM_PREP_READ));
+	struct msm_commit *commit =  NULL;
+
+	if (!work) {
+		DRM_ERROR("%s: Invalid commit work data!\n", __func__);
+		return;
+	}
+
+	commit = container_of(work, struct msm_commit, commit_work);
+
+	complete_commit(commit);
 }
 
-int msm_atomic_check(struct drm_device *dev,
-		     struct drm_atomic_state *state)
+static struct msm_commit *commit_init(struct drm_atomic_state *state)
 {
-	int ret;
+	struct msm_commit *commit = kzalloc(sizeof(*commit), GFP_KERNEL);
 
-	/*
-	 * msm ->atomic_check can update ->mode_changed for pixel format
-	 * changes, hence must be run before we check the modeset changes.
+	if (!commit) {
+		DRM_ERROR("invalid commit\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	commit->dev = state->dev;
+	commit->state = state;
+
+	/* TODO we might need a way to indicate to run the cb on a
+	 * different wq so wait_for_vblanks() doesn't block retiring
+	 * bo's..
 	 */
-	ret = drm_atomic_helper_check_planes(dev, state);
-	if (ret)
-		return ret;
+	INIT_FENCE_CB(&commit->fence_cb, fence_cb);
+	init_kthread_work(&commit->commit_work, _msm_drm_commit_work_cb);
 
-	ret = drm_atomic_helper_check_modeset(dev, state);
-	if (ret)
-		return ret;
+	return commit;
+}
+
+static void commit_set_fence(struct msm_commit *commit,
+		struct drm_framebuffer *fb)
+{
+	struct drm_gem_object *obj = msm_framebuffer_bo(fb, 0);
+	commit->fence = max(commit->fence,
+			msm_gem_fence(to_msm_bo(obj), MSM_PREP_READ));
+}
+
+/* Start display thread function */
+static int msm_atomic_commit_dispatch(struct drm_device *dev,
+		struct drm_atomic_state *state, struct msm_commit *commit)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	struct drm_crtc *crtc = NULL;
+	struct drm_crtc_state *crtc_state = NULL;
+	int ret = -EINVAL, i = 0, j = 0;
+
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		for (j = 0; j < priv->num_crtcs; j++) {
+			if (priv->disp_thread[j].crtc_id ==
+						crtc->base.id) {
+				if (priv->disp_thread[j].thread) {
+					queue_kthread_work(
+						&priv->disp_thread[j].worker,
+							&commit->commit_work);
+					/* only return zero if work is
+					 * queued successfully.
+					 */
+					ret = 0;
+				} else {
+					DRM_ERROR(" Error for crtc_id: %d\n",
+						priv->disp_thread[j].crtc_id);
+				}
+				break;
+			}
+		}
+		/*
+		 * TODO: handle cases where there will be more than
+		 * one crtc per commit cycle. Remove this check then.
+		 * Current assumption is there will be only one crtc
+		 * per commit cycle.
+		 */
+		if (j < priv->num_crtcs)
+			break;
+	}
 
 	return ret;
 }
@@ -192,9 +527,8 @@ int msm_atomic_check(struct drm_device *dev,
  * @state: the driver state object
  * @async: asynchronous commit
  *
- * This function commits a with drm_atomic_helper_check() pre-validated state
- * object. This can still fail when e.g. the framebuffer reservation fails. For
- * now this doesn't implement asynchronous commits.
+ * This function commits with drm_atomic_helper_check() pre-validated state
+ * object. This can still fail when e.g. the framebuffer reservation fails.
  *
  * RETURNS
  * Zero for success or -errno.
@@ -202,19 +536,21 @@ int msm_atomic_check(struct drm_device *dev,
 int msm_atomic_commit(struct drm_device *dev,
 		struct drm_atomic_state *state, bool async)
 {
+	struct msm_drm_private *priv = dev->dev_private;
 	int nplanes = dev->mode_config.num_total_plane;
 	int ncrtcs = dev->mode_config.num_crtc;
 	ktime_t timeout;
-	struct msm_commit *c;
+	struct msm_commit *commit;
 	int i, ret;
 
 	ret = drm_atomic_helper_prepare_planes(dev, state);
 	if (ret)
 		return ret;
 
-	c = commit_init(state);
-	if (!c) {
-		ret = -ENOMEM;
+	commit = commit_init(state);
+	if (IS_ERR_OR_NULL(commit)) {
+		ret = PTR_ERR(commit);
+		DRM_ERROR("commit_init failed: %d\n", ret);
 		goto error;
 	}
 
@@ -225,7 +561,7 @@ int msm_atomic_commit(struct drm_device *dev,
 		struct drm_crtc *crtc = state->crtcs[i];
 		if (!crtc)
 			continue;
-		c->crtc_mask |= (1 << drm_crtc_index(crtc));
+		commit->crtc_mask |= (1 << drm_crtc_index(crtc));
 	}
 
 	/*
@@ -239,16 +575,17 @@ int msm_atomic_commit(struct drm_device *dev,
 			continue;
 
 		if ((plane->state->fb != new_state->fb) && new_state->fb)
-			add_fb(c, new_state->fb);
+			commit_set_fence(commit, new_state->fb);
 	}
 
 	/*
 	 * Wait for pending updates on any of the same crtc's and then
 	 * mark our set of crtc's as busy:
 	 */
-	ret = start_atomic(dev->dev_private, c->crtc_mask);
+	ret = start_atomic(dev->dev_private, commit->crtc_mask);
 	if (ret) {
-		kfree(c);
+		DRM_ERROR("start_atomic failed: %d\n", ret);
+		commit_destroy(commit);
 		goto error;
 	}
 
@@ -260,6 +597,16 @@ int msm_atomic_commit(struct drm_device *dev,
 
 	drm_atomic_helper_swap_state(dev, state);
 
+	/*
+	 * Provide the driver a chance to prepare for output fences. This is
+	 * done after the point of no return, but before asynchronous commits
+	 * are dispatched to work queues, so that the fence preparation is
+	 * finished before the .atomic_commit returns.
+	 */
+	if (priv && priv->kms && priv->kms->funcs &&
+			priv->kms->funcs->prepare_fence)
+		priv->kms->funcs->prepare_fence(priv->kms, state);
+
 	/*
 	 * Everything below can be run asynchronously without the need to grab
 	 * any modeset locks at all under one conditions: It must be guaranteed
@@ -277,16 +624,22 @@ int msm_atomic_commit(struct drm_device *dev,
 	 */
 
 	if (async) {
-		msm_queue_fence_cb(dev, &c->fence_cb, c->fence);
+		ret = msm_atomic_commit_dispatch(dev, state, commit);
+		if (ret) {
+			DRM_ERROR("%s: atomic commit failed\n", __func__);
+			drm_atomic_state_free(state);
+			commit_destroy(commit);
+			goto error;
+		}
 		return 0;
 	}
 
 	timeout = ktime_add_ms(ktime_get(), 1000);
 
 	/* uninterruptible wait */
-	msm_wait_fence(dev, c->fence, &timeout, false);
+	msm_wait_fence(dev, commit->fence, &timeout, false);
 
-	complete_commit(c);
+	complete_commit(commit);
 
 	return 0;
 
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index b88ce514eb8e75d58bf069a52ac1f704605ce0d5..5d04b03842151b8b188c02e43bb0429e99149d52 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -15,9 +16,13 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/of_address.h>
 #include "msm_drv.h"
 #include "msm_gpu.h"
 #include "msm_kms.h"
+#include "sde_wb.h"
+
+#define TEARDOWN_DEADLOCK_RETRY_MAX 5
 
 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
@@ -29,7 +34,7 @@ static void msm_fb_output_poll_changed(struct drm_device *dev)
 static const struct drm_mode_config_funcs mode_config_funcs = {
 	.fb_create = msm_framebuffer_create,
 	.output_poll_changed = msm_fb_output_poll_changed,
-	.atomic_check = msm_atomic_check,
+	.atomic_check = drm_atomic_helper_check,
 	.atomic_commit = msm_atomic_commit,
 };
 
@@ -46,6 +51,29 @@ int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
 	return idx;
 }
 
+void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	int idx;
+
+	if (priv->num_mmus <= 0) {
+		dev_err(dev->dev, "invalid num mmus %d\n", priv->num_mmus);
+		return;
+	}
+
+	idx = priv->num_mmus - 1;
+
+	/* only support reverse-order deallocation */
+	if (priv->mmus[idx] != mmu) {
+		dev_err(dev->dev, "unexpected mmu at idx %d\n", idx);
+		return;
+	}
+
+	--priv->num_mmus;
+	priv->mmus[idx] = 0;
+}
+
+
 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
 static bool reglog = false;
 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
@@ -99,6 +127,11 @@ void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 	return ptr;
 }
 
+void msm_iounmap(struct platform_device *pdev, void __iomem *addr)
+{
+	devm_iounmap(&pdev->dev, addr);
+}
+
 void msm_writel(u32 data, void __iomem *addr)
 {
 	if (reglog)
@@ -120,7 +153,7 @@ struct vblank_event {
 	bool enable;
 };
 
-static void vblank_ctrl_worker(struct work_struct *work)
+static void vblank_ctrl_worker(struct kthread_work *work)
 {
 	struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
 						struct msm_vblank_ctrl, work);
@@ -168,7 +201,7 @@ static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
 	list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
 	spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
 
-	queue_work(priv->wq, &vbl_ctrl->work);
+	queue_kthread_work(&priv->disp_thread[crtc_id].worker, &vbl_ctrl->work);
 
 	return 0;
 }
@@ -180,21 +213,32 @@ static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
 static int msm_unload(struct drm_device *dev)
 {
 	struct msm_drm_private *priv = dev->dev_private;
+	struct platform_device *pdev = dev->platformdev;
 	struct msm_kms *kms = priv->kms;
 	struct msm_gpu *gpu = priv->gpu;
 	struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
 	struct vblank_event *vbl_ev, *tmp;
+	int i;
 
 	/* We must cancel and cleanup any pending vblank enable/disable
 	 * work before drm_irq_uninstall() to avoid work re-enabling an
 	 * irq after uninstall has disabled it.
 	 */
-	cancel_work_sync(&vbl_ctrl->work);
+	flush_kthread_work(&vbl_ctrl->work);
 	list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
 		list_del(&vbl_ev->node);
 		kfree(vbl_ev);
 	}
 
+	/* clean up display commit worker threads */
+	for (i = 0; i < priv->num_crtcs; i++) {
+		if (priv->disp_thread[i].thread) {
+			flush_kthread_worker(&priv->disp_thread[i].worker);
+			kthread_stop(priv->disp_thread[i].thread);
+			priv->disp_thread[i].thread = NULL;
+		}
+	}
+
 	drm_kms_helper_poll_fini(dev);
 	drm_mode_config_cleanup(dev);
 	drm_vblank_cleanup(dev);
@@ -226,6 +270,11 @@ static int msm_unload(struct drm_device *dev)
 				priv->vram.paddr, &attrs);
 	}
 
+	sde_evtlog_destroy();
+
+	sde_power_client_destroy(&priv->phandle, priv->pclient);
+	sde_power_resource_deinit(pdev, &priv->phandle);
+
 	component_unbind_all(dev->dev, dev);
 
 	dev->dev_private = NULL;
@@ -235,13 +284,20 @@ static int msm_unload(struct drm_device *dev)
 	return 0;
 }
 
+#define KMS_MDP4 0
+#define KMS_MDP5 1
+#define KMS_SDE  2
+
 static int get_mdp_ver(struct platform_device *pdev)
 {
 #ifdef CONFIG_OF
 	static const struct of_device_id match_types[] = { {
 		.compatible = "qcom,mdss_mdp",
-		.data	= (void	*)5,
-	}, {
+		.data	= (void	*)KMS_MDP5,
+	},
+	{
+		.compatible = "qcom,sde-kms",
+		.data	= (void	*)KMS_SDE,
 		/* end node */
 	} };
 	struct device *dev = &pdev->dev;
@@ -250,11 +306,9 @@ static int get_mdp_ver(struct platform_device *pdev)
 	if (match)
 		return (int)(unsigned long)match->data;
 #endif
-	return 4;
+	return KMS_MDP4;
 }
 
-#include <linux/of_address.h>
-
 static int msm_init_vram(struct drm_device *dev)
 {
 	struct msm_drm_private *priv = dev->dev_private;
@@ -330,12 +384,32 @@ static int msm_init_vram(struct drm_device *dev)
 	return ret;
 }
 
+#ifdef CONFIG_OF
+static int msm_component_bind_all(struct device *dev,
+				struct drm_device *drm_dev)
+{
+	int ret;
+
+	ret = component_bind_all(dev, drm_dev);
+	if (ret)
+		DRM_ERROR("component_bind_all failed: %d\n", ret);
+
+	return ret;
+}
+#else
+static int msm_component_bind_all(struct device *dev,
+				struct drm_device *drm_dev)
+{
+	return 0;
+}
+#endif
+
 static int msm_load(struct drm_device *dev, unsigned long flags)
 {
 	struct platform_device *pdev = dev->platformdev;
 	struct msm_drm_private *priv;
 	struct msm_kms *kms;
-	int ret;
+	int ret, i;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv) {
@@ -345,22 +419,36 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 
 	dev->dev_private = priv;
 
-	priv->wq = alloc_ordered_workqueue("msm", 0);
+	priv->wq = alloc_ordered_workqueue("msm_drm", 0);
 	init_waitqueue_head(&priv->fence_event);
 	init_waitqueue_head(&priv->pending_crtcs_event);
 
+	INIT_LIST_HEAD(&priv->client_event_list);
 	INIT_LIST_HEAD(&priv->inactive_list);
 	INIT_LIST_HEAD(&priv->fence_cbs);
 	INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
-	INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
+	init_kthread_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
 	spin_lock_init(&priv->vblank_ctrl.lock);
 
 	drm_mode_config_init(dev);
 
 	platform_set_drvdata(pdev, dev);
 
+	ret = sde_power_resource_init(pdev, &priv->phandle);
+	if (ret) {
+		pr_err("sde power resource init failed\n");
+		goto fail;
+	}
+
+	priv->pclient = sde_power_client_create(&priv->phandle, "sde");
+	if (IS_ERR_OR_NULL(priv->pclient)) {
+		pr_err("sde power client create failed\n");
+		ret = -EINVAL;
+		goto fail;
+	}
+
 	/* Bind all our sub-components: */
-	ret = component_bind_all(dev->dev, dev);
+	ret = msm_component_bind_all(dev->dev, dev);
 	if (ret)
 		return ret;
 
@@ -368,13 +456,22 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 	if (ret)
 		goto fail;
 
+	ret = sde_evtlog_init(dev->primary->debugfs_root);
+	if (ret) {
+		dev_err(dev->dev, "failed to init evtlog: %d\n", ret);
+		goto fail;
+	}
+
 	switch (get_mdp_ver(pdev)) {
-	case 4:
+	case KMS_MDP4:
 		kms = mdp4_kms_init(dev);
 		break;
-	case 5:
+	case KMS_MDP5:
 		kms = mdp5_kms_init(dev);
 		break;
+	case KMS_SDE:
+		kms = sde_kms_init(dev);
+		break;
 	default:
 		kms = ERR_PTR(-ENODEV);
 		break;
@@ -387,15 +484,16 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 		 * and (for example) use dmabuf/prime to share buffers with
 		 * imx drm driver on iMX5
 		 */
+		priv->kms = NULL;
 		dev_err(dev->dev, "failed to load kms\n");
 		ret = PTR_ERR(kms);
 		goto fail;
 	}
 
 	priv->kms = kms;
+	pm_runtime_enable(dev->dev);
 
-	if (kms) {
-		pm_runtime_enable(dev->dev);
+	if (kms && kms->funcs && kms->funcs->hw_init) {
 		ret = kms->funcs->hw_init(kms);
 		if (ret) {
 			dev_err(dev->dev, "kms hw init failed: %d\n", ret);
@@ -403,6 +501,29 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 		}
 	}
 
+	/* initialize commit thread structure */
+	for (i = 0; i < priv->num_crtcs; i++) {
+		priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
+		init_kthread_worker(&priv->disp_thread[i].worker);
+		priv->disp_thread[i].dev = dev;
+		priv->disp_thread[i].thread =
+			kthread_run(kthread_worker_fn,
+				&priv->disp_thread[i].worker,
+				"crtc_commit:%d",
+				priv->disp_thread[i].crtc_id);
+
+		if (IS_ERR(priv->disp_thread[i].thread)) {
+			dev_err(dev->dev, "failed to create kthread\n");
+			priv->disp_thread[i].thread = NULL;
+			/* clean up previously created threads if any */
+			for (i -= 1; i >= 0; i--) {
+				kthread_stop(priv->disp_thread[i].thread);
+				priv->disp_thread[i].thread = NULL;
+			}
+			goto fail;
+		}
+	}
+
 	dev->mode_config.funcs = &mode_config_funcs;
 
 	ret = drm_vblank_init(dev, priv->num_crtcs);
@@ -430,6 +551,15 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 	if (ret)
 		goto fail;
 
+	/* perform subdriver post initialization */
+	if (kms && kms->funcs && kms->funcs->postinit) {
+		ret = kms->funcs->postinit(kms);
+		if (ret) {
+			dev_err(dev->dev, "kms post init failed: %d\n", ret);
+			goto fail;
+		}
+	}
+
 	drm_kms_helper_poll_init(dev);
 
 	return 0;
@@ -439,6 +569,11 @@ fail:
 	return ret;
 }
 
+#ifdef CONFIG_QCOM_KGSL
+static void load_gpu(struct drm_device *dev)
+{
+}
+#else
 static void load_gpu(struct drm_device *dev)
 {
 	static DEFINE_MUTEX(init_lock);
@@ -451,6 +586,7 @@ static void load_gpu(struct drm_device *dev)
 
 	mutex_unlock(&init_lock);
 }
+#endif
 
 static int msm_open(struct drm_device *dev, struct drm_file *file)
 {
@@ -467,17 +603,34 @@ static int msm_open(struct drm_device *dev, struct drm_file *file)
 
 	file->driver_priv = ctx;
 
+	if (dev && dev->dev_private) {
+		struct msm_drm_private *priv = dev->dev_private;
+		struct msm_kms *kms;
+
+		kms = priv->kms;
+		if (kms && kms->funcs && kms->funcs->postopen)
+			kms->funcs->postopen(kms, file);
+	}
 	return 0;
 }
 
 static void msm_preclose(struct drm_device *dev, struct drm_file *file)
 {
 	struct msm_drm_private *priv = dev->dev_private;
-	struct msm_file_private *ctx = file->driver_priv;
 	struct msm_kms *kms = priv->kms;
 
-	if (kms)
+	if (kms && kms->funcs && kms->funcs->preclose)
 		kms->funcs->preclose(kms, file);
+}
+
+static void msm_postclose(struct drm_device *dev, struct drm_file *file)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	struct msm_file_private *ctx = file->driver_priv;
+	struct msm_kms *kms = priv->kms;
+
+	if (kms && kms->funcs && kms->funcs->postclose)
+		kms->funcs->postclose(kms, file);
 
 	mutex_lock(&dev->struct_mutex);
 	if (ctx == priv->lastctx)
@@ -487,11 +640,126 @@ static void msm_preclose(struct drm_device *dev, struct drm_file *file)
 	kfree(ctx);
 }
 
+static int msm_disable_all_modes_commit(
+		struct drm_device *dev,
+		struct drm_atomic_state *state)
+{
+	struct drm_plane *plane;
+	struct drm_crtc *crtc;
+	unsigned plane_mask;
+	int ret;
+
+	plane_mask = 0;
+	drm_for_each_plane(plane, dev) {
+		struct drm_plane_state *plane_state;
+
+		plane_state = drm_atomic_get_plane_state(state, plane);
+		if (IS_ERR(plane_state)) {
+			ret = PTR_ERR(plane_state);
+			goto fail;
+		}
+
+		plane_state->rotation = BIT(DRM_ROTATE_0);
+
+		plane->old_fb = plane->fb;
+		plane_mask |= 1 << drm_plane_index(plane);
+
+		/* disable non-primary: */
+		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+			continue;
+
+		DRM_DEBUG("disabling plane %d\n", plane->base.id);
+
+		ret = __drm_atomic_helper_disable_plane(plane, plane_state);
+		if (ret != 0)
+			DRM_ERROR("error %d disabling plane %d\n", ret,
+					plane->base.id);
+	}
+
+	drm_for_each_crtc(crtc, dev) {
+		struct drm_mode_set mode_set;
+
+		memset(&mode_set, 0, sizeof(struct drm_mode_set));
+		mode_set.crtc = crtc;
+
+		DRM_DEBUG("disabling crtc %d\n", crtc->base.id);
+
+		ret = __drm_atomic_helper_set_config(&mode_set, state);
+		if (ret != 0)
+			DRM_ERROR("error %d disabling crtc %d\n", ret,
+					crtc->base.id);
+	}
+
+	DRM_DEBUG("committing disables\n");
+	ret = drm_atomic_commit(state);
+
+fail:
+	drm_atomic_clean_old_fb(dev, plane_mask, ret);
+	DRM_DEBUG("disables result %d\n", ret);
+	return ret;
+}
+
+/**
+ * msm_clear_all_modes - disables all planes and crtcs via an atomic commit
+ *	based on restore_fbdev_mode_atomic in drm_fb_helper.c
+ * @dev: device pointer
+ * @Return: 0 on success, otherwise -error
+ */
+static int msm_disable_all_modes(struct drm_device *dev)
+{
+	struct drm_atomic_state *state;
+	int ret, i;
+
+	state = drm_atomic_state_alloc(dev);
+	if (!state)
+		return -ENOMEM;
+
+	state->acquire_ctx = dev->mode_config.acquire_ctx;
+
+	for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
+		ret = msm_disable_all_modes_commit(dev, state);
+		if (ret != -EDEADLK)
+			break;
+		drm_atomic_state_clear(state);
+		drm_atomic_legacy_backoff(state);
+	}
+
+	/* on successful atomic commit state ownership transfers to framework */
+	if (ret != 0)
+		drm_atomic_state_free(state);
+
+	return ret;
+}
+
 static void msm_lastclose(struct drm_device *dev)
 {
 	struct msm_drm_private *priv = dev->dev_private;
-	if (priv->fbdev)
+	struct msm_kms *kms = priv->kms;
+	int i;
+
+	/*
+	 * clean up vblank disable immediately as this is the last close.
+	 */
+	for (i = 0; i < dev->num_crtcs; i++) {
+		struct drm_vblank_crtc *vblank = &dev->vblank[i];
+		struct timer_list *disable_timer = &vblank->disable_timer;
+
+		if (del_timer_sync(disable_timer))
+			disable_timer->function(disable_timer->data);
+	}
+
+	/* wait for pending vblank requests to be executed by worker thread */
+	flush_workqueue(priv->wq);
+
+	if (priv->fbdev) {
 		drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
+	} else {
+		drm_modeset_lock_all(dev);
+		msm_disable_all_modes(dev);
+		drm_modeset_unlock_all(dev);
+		if (kms && kms->funcs && kms->funcs->lastclose)
+			kms->funcs->lastclose(kms);
+	}
 }
 
 static irqreturn_t msm_irq(int irq, void *arg)
@@ -927,6 +1195,362 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
 	return msm_wait_fence(dev, args->fence, &timeout, true);
 }
 
+static int msm_event_supported(struct drm_device *dev,
+		struct drm_msm_event_req *req)
+{
+	int ret = -EINVAL;
+	struct drm_mode_object *arg_obj;
+	struct drm_crtc *crtc;
+
+	arg_obj = drm_mode_object_find(dev, req->object_id, req->object_type);
+	if (!arg_obj)
+		return -ENOENT;
+
+	if (arg_obj->type == DRM_MODE_OBJECT_CRTC) {
+		crtc = obj_to_crtc(arg_obj);
+		req->index = drm_crtc_index(crtc);
+	}
+
+	switch (req->event) {
+	case DRM_EVENT_VBLANK:
+	case DRM_EVENT_HISTOGRAM:
+	case DRM_EVENT_AD:
+		if (arg_obj->type == DRM_MODE_OBJECT_CRTC)
+			ret = 0;
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static void msm_vblank_read_cb(struct drm_pending_event *e)
+{
+	struct drm_pending_vblank_event *vblank;
+	struct msm_drm_private *priv;
+	struct drm_file *file_priv;
+	struct drm_device *dev;
+	struct msm_drm_event *v;
+	int ret = 0;
+	bool need_vblank = false;
+
+	if (!e) {
+		DRM_ERROR("invalid pending event payload\n");
+		return;
+	}
+
+	vblank = container_of(e, struct drm_pending_vblank_event, base);
+	file_priv = vblank->base.file_priv;
+	dev = (file_priv && file_priv->minor) ? file_priv->minor->dev : NULL;
+	priv = (dev) ? dev->dev_private : NULL;
+	if (!priv) {
+		DRM_ERROR("invalid msm private\n");
+		return;
+	}
+
+	list_for_each_entry(v, &priv->client_event_list, base.link) {
+		if (v->base.file_priv != file_priv ||
+		    (v->event.type != DRM_EVENT_VBLANK &&
+		     v->event.type != DRM_EVENT_AD))
+			continue;
+		need_vblank = true;
+		/**
+		 * User-space client requests for N vsyncs when event
+		 * requested is DRM_EVENT_AD. Once the count reaches zero,
+		 * notify stop requesting for additional vsync's.
+		 */
+		if (v->event.type == DRM_EVENT_AD) {
+			if (vblank->event.user_data)
+				vblank->event.user_data--;
+			need_vblank = (vblank->event.user_data) ? true : false;
+		}
+		break;
+	}
+
+	if (!need_vblank) {
+		kfree(vblank);
+	} else {
+		ret = drm_vblank_get(dev, vblank->pipe);
+		if (!ret) {
+			list_add(&vblank->base.link, &dev->vblank_event_list);
+		} else {
+			DRM_ERROR("vblank enable failed ret %d\n", ret);
+			kfree(vblank);
+		}
+	}
+}
+
+static int msm_enable_vblank_event(struct drm_device *dev,
+			struct drm_msm_event_req *req, struct drm_file *file)
+{
+	struct drm_pending_vblank_event *e;
+	int ret = 0;
+	unsigned long flags;
+	struct drm_vblank_crtc *vblank;
+
+	if (WARN_ON(req->index >= dev->num_crtcs))
+		return -EINVAL;
+
+	vblank = &dev->vblank[req->index];
+	e = kzalloc(sizeof(*e), GFP_KERNEL);
+	if (!e)
+		return -ENOMEM;
+
+	e->pipe = req->index;
+	e->base.pid = current->pid;
+	e->event.base.type = DRM_EVENT_VBLANK;
+	e->event.base.length = sizeof(e->event);
+	e->event.user_data = req->client_context;
+	e->base.event = &e->event.base;
+	e->base.file_priv = file;
+	e->base.destroy = msm_vblank_read_cb;
+
+	ret = drm_vblank_get(dev, e->pipe);
+	if (ret) {
+		DRM_ERROR("failed to enable the vblank\n");
+		goto free;
+	}
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	if (!vblank->enabled) {
+		ret = -EINVAL;
+		goto err_unlock;
+	}
+
+	if (file->event_space < sizeof(e->event)) {
+		ret = -EBUSY;
+		goto err_unlock;
+	}
+	file->event_space -= sizeof(e->event);
+	list_add_tail(&e->base.link, &dev->vblank_event_list);
+err_unlock:
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+free:
+	if (ret)
+		kfree(e);
+	return ret;
+}
+
+static int msm_enable_event(struct drm_device *dev,
+			struct drm_msm_event_req *req, struct drm_file *file)
+{
+	int ret = -EINVAL;
+
+	switch (req->event) {
+	case DRM_EVENT_AD:
+	case DRM_EVENT_VBLANK:
+		ret = msm_enable_vblank_event(dev, req, file);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int msm_disable_vblank_event(struct drm_device *dev,
+			    struct drm_msm_event_req *req,
+			    struct drm_file *file)
+{
+	struct drm_pending_vblank_event *e, *t;
+
+	list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) {
+		if (e->pipe != req->index || file != e->base.file_priv)
+			continue;
+		list_del(&e->base.link);
+		drm_vblank_put(dev, req->index);
+		kfree(e);
+	}
+	return 0;
+}
+
+static int msm_disable_event(struct drm_device *dev,
+			    struct drm_msm_event_req *req,
+			    struct drm_file *file)
+{
+	int ret = -EINVAL;
+
+	switch (req->event) {
+	case DRM_EVENT_AD:
+	case DRM_EVENT_VBLANK:
+		ret = msm_disable_vblank_event(dev, req, file);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+
+static int msm_ioctl_register_event(struct drm_device *dev, void *data,
+				    struct drm_file *file)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	struct drm_msm_event_req *req_event = data;
+	struct msm_drm_event *client;
+	struct msm_drm_event *v;
+	unsigned long flag = 0;
+	bool dup_request = false;
+	int ret = 0;
+
+	if (msm_event_supported(dev, req_event)) {
+		DRM_ERROR("unsupported event %x object %x object id %d\n",
+			req_event->event, req_event->object_type,
+			req_event->object_id);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&dev->event_lock, flag);
+	list_for_each_entry(v, &priv->client_event_list, base.link) {
+		if (v->base.file_priv != file)
+			continue;
+		if (v->event.type == req_event->event &&
+			v->info.object_id == req_event->object_id) {
+			DRM_ERROR("duplicate request for event %x obj id %d\n",
+				v->event.type, v->info.object_id);
+			dup_request = true;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flag);
+
+	if (dup_request)
+		return -EINVAL;
+
+	client = kzalloc(sizeof(*client), GFP_KERNEL);
+	if (!client)
+		return -ENOMEM;
+
+	client->base.file_priv = file;
+	client->base.pid = current->pid;
+	client->base.event = &client->event;
+	client->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
+	client->event.type = req_event->event;
+	memcpy(&client->info, req_event, sizeof(client->info));
+
+	spin_lock_irqsave(&dev->event_lock, flag);
+	list_add_tail(&client->base.link, &priv->client_event_list);
+	spin_unlock_irqrestore(&dev->event_lock, flag);
+
+	ret = msm_enable_event(dev, req_event, file);
+	if (ret) {
+		DRM_ERROR("failed to enable event %x object %x object id %d\n",
+			req_event->event, req_event->object_type,
+			req_event->object_id);
+		spin_lock_irqsave(&dev->event_lock, flag);
+		list_del(&client->base.link);
+		spin_unlock_irqrestore(&dev->event_lock, flag);
+		kfree(client);
+	}
+	return ret;
+}
+
+static int msm_ioctl_deregister_event(struct drm_device *dev, void *data,
+				      struct drm_file *file)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	struct drm_msm_event_req *req_event = data;
+	struct msm_drm_event *client = NULL;
+	struct msm_drm_event *v, *vt;
+	unsigned long flag = 0;
+
+	if (msm_event_supported(dev, req_event)) {
+		DRM_ERROR("unsupported event %x object %x object id %d\n",
+			req_event->event, req_event->object_type,
+			req_event->object_id);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&dev->event_lock, flag);
+	msm_disable_event(dev, req_event, file);
+	list_for_each_entry_safe(v, vt, &priv->client_event_list, base.link) {
+		if (v->event.type == req_event->event &&
+		    v->info.object_id == req_event->object_id &&
+		    v->base.file_priv == file) {
+			client = v;
+			list_del(&client->base.link);
+			client->base.destroy(&client->base);
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flag);
+
+	return 0;
+}
+
+void msm_send_crtc_notification(struct drm_crtc *crtc,
+				struct drm_event *event, u8 *payload)
+{
+	struct drm_device *dev = NULL;
+	struct msm_drm_private *priv = NULL;
+	unsigned long flags;
+	struct msm_drm_event *notify, *v;
+	int len = 0;
+
+	if (!crtc || !event || !event->length || !payload) {
+		DRM_ERROR("err param crtc %pK event %pK len %d payload %pK\n",
+			crtc, event, ((event) ? (event->length) : -1),
+			payload);
+		return;
+	}
+	dev = crtc->dev;
+	priv = (dev) ? dev->dev_private : NULL;
+	if (!dev || !priv) {
+		DRM_ERROR("invalid dev %pK priv %pK\n", dev, priv);
+		return;
+	}
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	list_for_each_entry(v, &priv->client_event_list, base.link) {
+		if (v->event.type != event->type ||
+			crtc->base.id != v->info.object_id)
+			continue;
+		len = event->length + sizeof(struct drm_msm_event_resp);
+		if (v->base.file_priv->event_space < len) {
+			DRM_ERROR("Insufficient space to notify\n");
+			continue;
+		}
+		notify = kzalloc(len, GFP_ATOMIC);
+		if (!notify)
+			continue;
+		notify->base.file_priv = v->base.file_priv;
+		notify->base.event = &notify->event;
+		notify->base.pid = v->base.pid;
+		notify->base.destroy =
+			(void (*)(struct drm_pending_event *)) kfree;
+		notify->event.type = v->event.type;
+		notify->event.length = len;
+		list_add(&notify->base.link,
+			&notify->base.file_priv->event_list);
+		notify->base.file_priv->event_space -= len;
+		memcpy(&notify->info, &v->info, sizeof(notify->info));
+		memcpy(notify->data, payload, event->length);
+		wake_up_interruptible(&notify->base.file_priv->event_wait);
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+}
+
+int msm_release(struct inode *inode, struct file *filp)
+{
+	struct drm_file *file_priv = filp->private_data;
+	struct drm_minor *minor = file_priv->minor;
+	struct drm_device *dev = minor->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+	struct msm_drm_event *v, *vt;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	list_for_each_entry_safe(v, vt, &priv->client_event_list, base.link) {
+		if (v->base.file_priv != file_priv)
+			continue;
+		list_del(&v->base.link);
+		msm_disable_event(dev, &v->info, file_priv);
+		v->base.destroy(&v->base);
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	return drm_release(inode, filp);
+}
+
 static const struct drm_ioctl_desc msm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_AUTH|DRM_RENDER_ALLOW),
@@ -935,6 +1559,11 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH),
+	DRM_IOCTL_DEF_DRV(MSM_REGISTER_EVENT,  msm_ioctl_register_event,
+			  DRM_UNLOCKED|DRM_CONTROL_ALLOW),
+	DRM_IOCTL_DEF_DRV(MSM_DEREGISTER_EVENT,  msm_ioctl_deregister_event,
+			  DRM_UNLOCKED|DRM_CONTROL_ALLOW),
 };
 
 static const struct vm_operations_struct vm_ops = {
@@ -946,7 +1575,7 @@ static const struct vm_operations_struct vm_ops = {
 static const struct file_operations fops = {
 	.owner              = THIS_MODULE,
 	.open               = drm_open,
-	.release            = drm_release,
+	.release            = msm_release,
 	.unlocked_ioctl     = drm_ioctl,
 #ifdef CONFIG_COMPAT
 	.compat_ioctl       = drm_compat_ioctl,
@@ -968,6 +1597,7 @@ static struct drm_driver msm_driver = {
 	.unload             = msm_unload,
 	.open               = msm_open,
 	.preclose           = msm_preclose,
+	.postclose          = msm_postclose,
 	.lastclose          = msm_lastclose,
 	.set_busid          = drm_platform_set_busid,
 	.irq_handler        = msm_irq,
@@ -1000,7 +1630,7 @@ static struct drm_driver msm_driver = {
 	.ioctls             = msm_ioctls,
 	.num_ioctls         = DRM_MSM_NUM_IOCTLS,
 	.fops               = &fops,
-	.name               = "msm",
+	.name               = "msm_drm",
 	.desc               = "MSM Snapdragon DRM",
 	.date               = "20130625",
 	.major              = 1,
@@ -1031,6 +1661,27 @@ static const struct dev_pm_ops msm_pm_ops = {
 	SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
 };
 
+static int msm_drm_bind(struct device *dev)
+{
+	int ret;
+
+	ret = drm_platform_init(&msm_driver, to_platform_device(dev));
+	if (ret)
+		DRM_ERROR("drm_platform_init failed: %d\n", ret);
+
+	return ret;
+}
+
+static void msm_drm_unbind(struct device *dev)
+{
+	drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
+}
+
+static const struct component_master_ops msm_drm_ops = {
+	.bind = msm_drm_bind,
+	.unbind = msm_drm_unbind,
+};
+
 /*
  * Componentized driver support:
  */
@@ -1062,27 +1713,31 @@ static int add_components(struct device *dev, struct component_match **matchptr,
 
 	return 0;
 }
-#else
-static int compare_dev(struct device *dev, void *data)
+
+static int msm_add_master_component(struct device *dev,
+					struct component_match *match)
 {
-	return dev == data;
+	int ret;
+
+	ret = component_master_add_with_match(dev, &msm_drm_ops, match);
+	if (ret)
+		DRM_ERROR("component add match failed: %d\n", ret);
+
+	return ret;
 }
-#endif
 
-static int msm_drm_bind(struct device *dev)
+#else
+static int compare_dev(struct device *dev, void *data)
 {
-	return drm_platform_init(&msm_driver, to_platform_device(dev));
+	return dev == data;
 }
 
-static void msm_drm_unbind(struct device *dev)
+static int msm_add_master_component(struct device *dev,
+					struct component_match *match)
 {
-	drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
+	return 0;
 }
-
-static const struct component_master_ops msm_drm_ops = {
-	.bind = msm_drm_bind,
-	.unbind = msm_drm_unbind,
-};
+#endif
 
 /*
  * Platform driver:
@@ -1090,7 +1745,9 @@ static const struct component_master_ops msm_drm_ops = {
 
 static int msm_pdev_probe(struct platform_device *pdev)
 {
+	int ret;
 	struct component_match *match = NULL;
+
 #ifdef CONFIG_OF
 	add_components(&pdev->dev, &match, "connectors");
 	add_components(&pdev->dev, &match, "gpus");
@@ -1120,15 +1777,16 @@ static int msm_pdev_probe(struct platform_device *pdev)
 		component_match_add(&pdev->dev, &match, compare_dev, dev);
 	}
 #endif
-
 	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-	return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
+	ret = msm_add_master_component(&pdev->dev, match);
+
+	return ret;
 }
 
 static int msm_pdev_remove(struct platform_device *pdev)
 {
+	msm_drm_unbind(&pdev->dev);
 	component_master_del(&pdev->dev, &msm_drm_ops);
-
 	return 0;
 }
 
@@ -1140,6 +1798,7 @@ static const struct platform_device_id msm_id[] = {
 static const struct of_device_id dt_match[] = {
 	{ .compatible = "qcom,mdp" },      /* mdp4 */
 	{ .compatible = "qcom,mdss_mdp" }, /* mdp5 */
+	{ .compatible = "qcom,sde-kms" },  /* sde  */
 	{}
 };
 MODULE_DEVICE_TABLE(of, dt_match);
@@ -1148,13 +1807,23 @@ static struct platform_driver msm_platform_driver = {
 	.probe      = msm_pdev_probe,
 	.remove     = msm_pdev_remove,
 	.driver     = {
-		.name   = "msm",
+		.name   = "msm_drm",
 		.of_match_table = dt_match,
 		.pm     = &msm_pm_ops,
 	},
 	.id_table   = msm_id,
 };
 
+#ifdef CONFIG_QCOM_KGSL
+void __init adreno_register(void)
+{
+}
+
+void __exit adreno_unregister(void)
+{
+}
+#endif
+
 static int __init msm_drm_register(void)
 {
 	DBG("init");
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 3be7a56b14f1d85c478cc802b69ea441ba2f498e..a2678882d57a298e26f67e7f1ddbde710fe380f5 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -31,7 +32,9 @@
 #include <linux/iommu.h>
 #include <linux/types.h>
 #include <linux/of_graph.h>
+#include <linux/mdss_io_util.h>
 #include <asm/sizes.h>
+#include <linux/kthread.h>
 
 #ifndef CONFIG_OF
 #include <mach/board.h>
@@ -48,6 +51,12 @@
 #include <drm/msm_drm.h>
 #include <drm/drm_gem.h>
 
+#include "sde_power_handle.h"
+
+#define GET_MAJOR_REV(rev)		((rev) >> 28)
+#define GET_MINOR_REV(rev)		(((rev) >> 16) & 0xFFF)
+#define GET_STEP_REV(rev)		((rev) & 0xFFFF)
+
 struct msm_kms;
 struct msm_gpu;
 struct msm_mmu;
@@ -55,7 +64,12 @@ struct msm_rd_state;
 struct msm_perf_state;
 struct msm_gem_submit;
 
-#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */
+#define NUM_DOMAINS    4    /* one for KMS, then one per gpu core (?) */
+#define MAX_CRTCS      8
+#define MAX_PLANES     12
+#define MAX_ENCODERS   8
+#define MAX_BRIDGES    8
+#define MAX_CONNECTORS 8
 
 struct msm_file_private {
 	/* currently we don't do anything useful with this.. but when
@@ -66,22 +80,181 @@ struct msm_file_private {
 };
 
 enum msm_mdp_plane_property {
-	PLANE_PROP_ZPOS,
+	/* blob properties, always put these first */
+	PLANE_PROP_SCALER_V1,
+	PLANE_PROP_SCALER_V2,
+	PLANE_PROP_CSC_V1,
+	PLANE_PROP_INFO,
+	PLANE_PROP_SCALER_LUT_ED,
+	PLANE_PROP_SCALER_LUT_CIR,
+	PLANE_PROP_SCALER_LUT_SEP,
+	PLANE_PROP_SKIN_COLOR,
+	PLANE_PROP_SKY_COLOR,
+	PLANE_PROP_FOLIAGE_COLOR,
+
+	/* # of blob properties */
+	PLANE_PROP_BLOBCOUNT,
+
+	/* range properties */
+	PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
 	PLANE_PROP_ALPHA,
-	PLANE_PROP_PREMULTIPLIED,
-	PLANE_PROP_MAX_NUM
+	PLANE_PROP_COLOR_FILL,
+	PLANE_PROP_H_DECIMATE,
+	PLANE_PROP_V_DECIMATE,
+	PLANE_PROP_INPUT_FENCE,
+	PLANE_PROP_HUE_ADJUST,
+	PLANE_PROP_SATURATION_ADJUST,
+	PLANE_PROP_VALUE_ADJUST,
+	PLANE_PROP_CONTRAST_ADJUST,
+
+	/* enum/bitmask properties */
+	PLANE_PROP_ROTATION,
+	PLANE_PROP_BLEND_OP,
+	PLANE_PROP_SRC_CONFIG,
+
+	/* total # of properties */
+	PLANE_PROP_COUNT
+};
+
+enum msm_mdp_crtc_property {
+	CRTC_PROP_INFO,
+
+	/* # of blob properties */
+	CRTC_PROP_BLOBCOUNT,
+
+	/* range properties */
+	CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
+	CRTC_PROP_OUTPUT_FENCE,
+	CRTC_PROP_OUTPUT_FENCE_OFFSET,
+	CRTC_PROP_CORE_CLK,
+	CRTC_PROP_CORE_AB,
+	CRTC_PROP_CORE_IB,
+
+	/* total # of properties */
+	CRTC_PROP_COUNT
+};
+
+enum msm_mdp_conn_property {
+	/* blob properties, always put these first */
+	CONNECTOR_PROP_SDE_INFO,
+
+	/* # of blob properties */
+	CONNECTOR_PROP_BLOBCOUNT,
+
+	/* range properties */
+	CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
+	CONNECTOR_PROP_RETIRE_FENCE,
+	CONNECTOR_PROP_DST_X,
+	CONNECTOR_PROP_DST_Y,
+	CONNECTOR_PROP_DST_W,
+	CONNECTOR_PROP_DST_H,
+
+	/* enum/bitmask properties */
+	CONNECTOR_PROP_TOPOLOGY_NAME,
+	CONNECTOR_PROP_TOPOLOGY_CONTROL,
+
+	/* total # of properties */
+	CONNECTOR_PROP_COUNT
 };
 
 struct msm_vblank_ctrl {
-	struct work_struct work;
+	struct kthread_work work;
 	struct list_head event_list;
 	spinlock_t lock;
 };
 
+#define MAX_H_TILES_PER_DISPLAY 2
+
+/**
+ * enum msm_display_compression - compression method used for pixel stream
+ * @MSM_DISPLAY_COMPRESS_NONE:     Pixel data is not compressed
+ * @MSM_DISPLAY_COMPRESS_DSC:      DSC compresison is used
+ * @MSM_DISPLAY_COMPRESS_FBC:      FBC compression is used
+ */
+enum msm_display_compression {
+	MSM_DISPLAY_COMPRESS_NONE,
+	MSM_DISPLAY_COMPRESS_DSC,
+	MSM_DISPLAY_COMPRESS_FBC,
+};
+
+/**
+ * enum msm_display_caps - features/capabilities supported by displays
+ * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
+ * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
+ * @MSM_DISPLAY_CAP_HOT_PLUG:           Hot plug detection supported
+ * @MSM_DISPLAY_CAP_EDID:               EDID supported
+ */
+enum msm_display_caps {
+	MSM_DISPLAY_CAP_VID_MODE	= BIT(0),
+	MSM_DISPLAY_CAP_CMD_MODE	= BIT(1),
+	MSM_DISPLAY_CAP_HOT_PLUG	= BIT(2),
+	MSM_DISPLAY_CAP_EDID		= BIT(3),
+};
+
+/**
+ * struct msm_display_info - defines display properties
+ * @intf_type:          DRM_MODE_CONNECTOR_ display type
+ * @capabilities:       Bitmask of display flags
+ * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
+ * @h_tile_instance:    Controller instance used per tile. Number of elements is
+ *                      based on num_of_h_tiles
+ * @is_connected:       Set to true if display is connected
+ * @width_mm:           Physical width
+ * @height_mm:          Physical height
+ * @max_width:          Max width of display. In case of hot pluggable display
+ *                      this is max width supported by controller
+ * @max_height:         Max height of display. In case of hot pluggable display
+ *                      this is max height supported by controller
+ * @compression:        Compression supported by the display
+ */
+struct msm_display_info {
+	int intf_type;
+	uint32_t capabilities;
+
+	uint32_t num_of_h_tiles;
+	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
+
+	bool is_connected;
+
+	unsigned int width_mm;
+	unsigned int height_mm;
+
+	uint32_t max_width;
+	uint32_t max_height;
+
+	enum msm_display_compression compression;
+};
+
+/**
+ * struct msm_drm_event - defines custom event notification struct
+ * @base: base object required for event notification by DRM framework.
+ * @event: event object required for event notification by DRM framework.
+ * @info: contains information of DRM object for which events has been
+ *        requested.
+ * @data: memory location which contains response payload for event.
+ */
+struct msm_drm_event {
+	struct drm_pending_event base;
+	struct drm_event event;
+	struct drm_msm_event_req info;
+	u8 data[];
+};
+
+/* Commit thread specific structure */
+struct msm_drm_commit {
+	struct drm_device *dev;
+	struct task_struct *thread;
+	unsigned int crtc_id;
+	struct kthread_worker worker;
+};
+
 struct msm_drm_private {
 
 	struct msm_kms *kms;
 
+	struct sde_power_handle phandle;
+	struct sde_power_client *pclient;
+
 	/* subordinate devices, if present: */
 	struct platform_device *gpu_pdev;
 
@@ -128,22 +301,29 @@ struct msm_drm_private {
 	struct msm_mmu *mmus[NUM_DOMAINS];
 
 	unsigned int num_planes;
-	struct drm_plane *planes[8];
+	struct drm_plane *planes[MAX_PLANES];
 
 	unsigned int num_crtcs;
-	struct drm_crtc *crtcs[8];
+	struct drm_crtc *crtcs[MAX_CRTCS];
+
+	struct msm_drm_commit disp_thread[MAX_CRTCS];
 
 	unsigned int num_encoders;
-	struct drm_encoder *encoders[8];
+	struct drm_encoder *encoders[MAX_ENCODERS];
 
 	unsigned int num_bridges;
-	struct drm_bridge *bridges[8];
+	struct drm_bridge *bridges[MAX_BRIDGES];
 
 	unsigned int num_connectors;
-	struct drm_connector *connectors[8];
+	struct drm_connector *connectors[MAX_CONNECTORS];
 
 	/* Properties */
-	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
+	struct drm_property *plane_property[PLANE_PROP_COUNT];
+	struct drm_property *crtc_property[CRTC_PROP_COUNT];
+	struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
+
+	/* Color processing properties for the crtc */
+	struct drm_property **cp_property;
 
 	/* VRAM carveout, used when no IOMMU: */
 	struct {
@@ -156,6 +336,9 @@ struct msm_drm_private {
 	} vram;
 
 	struct msm_vblank_ctrl vblank_ctrl;
+
+	/* list of clients waiting for events */
+	struct list_head client_event_list;
 };
 
 struct msm_format {
@@ -176,12 +359,11 @@ void __msm_fence_worker(struct work_struct *work);
 		(_cb)->func = _func;                         \
 	} while (0)
 
-int msm_atomic_check(struct drm_device *dev,
-		     struct drm_atomic_state *state);
 int msm_atomic_commit(struct drm_device *dev,
 		struct drm_atomic_state *state, bool async);
 
 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
+void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 
 int msm_wait_fence(struct drm_device *dev, uint32_t fence,
 		ktime_t *timeout, bool interruptible);
@@ -264,6 +446,15 @@ enum msm_dsi_encoder_id {
 	MSM_DSI_CMD_ENCODER_ID = 1,
 	MSM_DSI_ENCODER_NUM = 2
 };
+
+/* *
+ * msm_send_crtc_notification - notify user-space clients of crtc events.
+ * @crtc: crtc that is generating the event.
+ * @event: event that needs to be notified.
+ * @payload: payload for the event.
+ */
+void msm_send_crtc_notification(struct drm_crtc *crtc,
+		struct drm_event *event, u8 *payload);
 #ifdef CONFIG_DRM_MSM_DSI
 void __init msm_dsi_register(void);
 void __exit msm_dsi_unregister(void);
@@ -301,6 +492,7 @@ static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
 
 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 		const char *dbgname);
+void msm_iounmap(struct platform_device *dev, void __iomem *addr);
 void msm_writel(u32 data, void __iomem *addr);
 u32 msm_readl(const void __iomem *addr);
 
@@ -331,5 +523,4 @@ static inline int align_pitch(int width, int bpp)
 /* for conditionally setting boolean flag(s): */
 #define COND(bool, val) ((bool) ? (val) : 0)
 
-
 #endif /* __MSM_DRV_H__ */
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index 121713281417a92fc2270c7f907a082a1e0c4a87..dca4de382581a5eedb18412df42d5b20ae27ac94 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -133,8 +133,7 @@ struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane)
 
 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb)
 {
-	struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
-	return msm_fb->format;
+	return fb ? (to_msm_framebuffer(fb))->format : NULL;
 }
 
 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
@@ -175,18 +174,20 @@ struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
 	struct msm_framebuffer *msm_fb = NULL;
 	struct drm_framebuffer *fb;
 	const struct msm_format *format;
-	int ret, i, n;
+	int ret, i, num_planes;
 	unsigned int hsub, vsub;
+	bool is_modified = false;
 
 	DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)",
 			dev, mode_cmd, mode_cmd->width, mode_cmd->height,
 			(char *)&mode_cmd->pixel_format);
 
-	n = drm_format_num_planes(mode_cmd->pixel_format);
+	num_planes = drm_format_num_planes(mode_cmd->pixel_format);
 	hsub = drm_format_horz_chroma_subsampling(mode_cmd->pixel_format);
 	vsub = drm_format_vert_chroma_subsampling(mode_cmd->pixel_format);
 
-	format = kms->funcs->get_format(kms, mode_cmd->pixel_format);
+	format = kms->funcs->get_format(kms, mode_cmd->pixel_format,
+			mode_cmd->modifier, num_planes);
 	if (!format) {
 		dev_err(dev->dev, "unsupported pixel format: %4.4s\n",
 				(char *)&mode_cmd->pixel_format);
@@ -204,27 +205,53 @@ struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
 
 	msm_fb->format = format;
 
-	if (n > ARRAY_SIZE(msm_fb->planes)) {
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
+		for (i = 0; i < ARRAY_SIZE(mode_cmd->modifier); i++) {
+			if (mode_cmd->modifier[i]) {
+				is_modified = true;
+				break;
+			}
+		}
+	}
+
+	if (num_planes > ARRAY_SIZE(msm_fb->planes)) {
 		ret = -EINVAL;
 		goto fail;
 	}
 
-	for (i = 0; i < n; i++) {
-		unsigned int width = mode_cmd->width / (i ? hsub : 1);
-		unsigned int height = mode_cmd->height / (i ? vsub : 1);
-		unsigned int min_size;
-
-		min_size = (height - 1) * mode_cmd->pitches[i]
-			 + width * drm_format_plane_cpp(mode_cmd->pixel_format, i)
-			 + mode_cmd->offsets[i];
-
-		if (bos[i]->size < min_size) {
+	if (is_modified) {
+		if (!kms->funcs->check_modified_format) {
+			dev_err(dev->dev, "can't check modified fb format\n");
 			ret = -EINVAL;
 			goto fail;
+		} else {
+			ret = kms->funcs->check_modified_format(
+				kms, msm_fb->format, mode_cmd, bos);
+			if (ret)
+				goto fail;
+		}
+	} else {
+		for (i = 0; i < num_planes; i++) {
+			unsigned int width = mode_cmd->width / (i ? hsub : 1);
+			unsigned int height = mode_cmd->height / (i ? vsub : 1);
+			unsigned int min_size;
+			unsigned int cpp;
+
+			cpp = drm_format_plane_cpp(mode_cmd->pixel_format, i);
+
+			min_size = (height - 1) * mode_cmd->pitches[i]
+				 + width * cpp
+				 + mode_cmd->offsets[i];
+
+			if (bos[i]->size < min_size) {
+				ret = -EINVAL;
+				goto fail;
+			}
 		}
+	}
 
+	for (i = 0; i < num_planes; i++)
 		msm_fb->planes[i] = bos[i];
-	}
 
 	drm_helper_mode_fill_fb_struct(fb, mode_cmd);
 
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index c76cc853b08a57effec626b8c6f537b270ca61ac..6fa56abf0c78ac408af2eb8985bed8cd1344adb0 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -295,16 +295,23 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
 
 		if (iommu_present(&platform_bus_type)) {
 			struct msm_mmu *mmu = priv->mmus[id];
-			uint32_t offset;
 
 			if (WARN_ON(!mmu))
 				return -EINVAL;
 
-			offset = (uint32_t)mmap_offset(obj);
-			ret = mmu->funcs->map(mmu, offset, msm_obj->sgt,
-					obj->size, IOMMU_READ | IOMMU_WRITE);
-			msm_obj->domain[id].iova = offset;
+			if (obj->import_attach && mmu->funcs->map_dma_buf) {
+				ret = mmu->funcs->map_dma_buf(mmu, msm_obj->sgt,
+						obj->import_attach->dmabuf,
+						DMA_BIDIRECTIONAL);
+				if (ret) {
+					DRM_ERROR("Unable to map dma buf\n");
+					return ret;
+				}
+			}
+			msm_obj->domain[id].iova =
+				sg_dma_address(msm_obj->sgt->sgl);
 		} else {
+			WARN_ONCE(1, "physical address being used\n");
 			msm_obj->domain[id].iova = physaddr(obj);
 		}
 	}
@@ -524,8 +531,11 @@ void msm_gem_free_object(struct drm_gem_object *obj)
 	for (id = 0; id < ARRAY_SIZE(msm_obj->domain); id++) {
 		struct msm_mmu *mmu = priv->mmus[id];
 		if (mmu && msm_obj->domain[id].iova) {
-			uint32_t offset = msm_obj->domain[id].iova;
-			mmu->funcs->unmap(mmu, offset, msm_obj->sgt, obj->size);
+			if (obj->import_attach && mmu->funcs->unmap_dma_buf) {
+				mmu->funcs->unmap_dma_buf(mmu, msm_obj->sgt,
+						obj->import_attach->dmabuf,
+						DMA_BIDIRECTIONAL);
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index 6fc59bfeedeb52cb06a2518d53912f5f215a3437..2e4ae6b1c5d04ef5b66bfc9712586ab53750c952 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -53,8 +53,7 @@ struct msm_gem_object {
 	void *vaddr;
 
 	struct {
-		// XXX
-		uint32_t iova;
+		dma_addr_t iova;
 	} domain[NUM_DOMAINS];
 
 	/* normally (resv == &_resv) except for imported bo's */
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 9bcabaada17930d73a742dc603a65688335cf91e..2ab50919f514976cb7e3df7dc80cc9f6278ab666 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
@@ -25,6 +26,15 @@
 
 #define MAX_PLANE	4
 
+/**
+ * Device Private DRM Mode Flags
+ * drm_mode->private_flags
+ */
+/* Connector has interpreted seamless transition request as dynamic fps */
+#define MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS	(1<<0)
+/* Transition to new mode requires a wait-for-vblank before the modeset */
+#define MSM_MODE_FLAG_VBLANK_PRE_MODESET	(1<<1)
+
 /* As there are different display controller blocks depending on the
  * snapdragon version, the kms support is split out and the appropriate
  * implementation is loaded at runtime.  The kms module is responsible
@@ -33,6 +43,7 @@
 struct msm_kms_funcs {
 	/* hw initialization: */
 	int (*hw_init)(struct msm_kms *kms);
+	int (*postinit)(struct msm_kms *kms);
 	/* irq handling: */
 	void (*irq_preinstall)(struct msm_kms *kms);
 	int (*irq_postinstall)(struct msm_kms *kms);
@@ -41,21 +52,38 @@ struct msm_kms_funcs {
 	int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
 	void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
 	/* modeset, bracketing atomic_commit(): */
-	void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
-	void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
+	void (*prepare_fence)(struct msm_kms *kms,
+			struct drm_atomic_state *state);
+	void (*prepare_commit)(struct msm_kms *kms,
+			struct drm_atomic_state *state);
+	void (*commit)(struct msm_kms *kms, struct drm_atomic_state *state);
+	void (*complete_commit)(struct msm_kms *kms,
+			struct drm_atomic_state *state);
 	/* functions to wait for atomic commit completed on each CRTC */
 	void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
 					struct drm_crtc *crtc);
+	/* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
+	const struct msm_format *(*get_format)(struct msm_kms *kms,
+					const uint32_t format,
+					const uint64_t *modifiers,
+					const uint32_t modifiers_len);
+	/* do format checking on format modified through fb_cmd2 modifiers */
+	int (*check_modified_format)(const struct msm_kms *kms,
+			const struct msm_format *msm_fmt,
+			const struct drm_mode_fb_cmd2 *cmd,
+			struct drm_gem_object **bos);
 	/* misc: */
-	const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
 	long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
 			struct drm_encoder *encoder);
 	int (*set_split_display)(struct msm_kms *kms,
 			struct drm_encoder *encoder,
 			struct drm_encoder *slave_encoder,
 			bool is_cmd_mode);
+	void (*postopen)(struct msm_kms *kms, struct drm_file *file);
 	/* cleanup: */
 	void (*preclose)(struct msm_kms *kms, struct drm_file *file);
+	void (*postclose)(struct msm_kms *kms, struct drm_file *file);
+	void (*lastclose)(struct msm_kms *kms);
 	void (*destroy)(struct msm_kms *kms);
 };
 
@@ -74,7 +102,33 @@ static inline void msm_kms_init(struct msm_kms *kms,
 	kms->funcs = funcs;
 }
 
+#ifdef CONFIG_DRM_MSM_MDP4
 struct msm_kms *mdp4_kms_init(struct drm_device *dev);
+#else
+static inline
+struct msm_kms *mdp4_kms_init(struct drm_device *dev) { return NULL; };
+#endif
 struct msm_kms *mdp5_kms_init(struct drm_device *dev);
+struct msm_kms *sde_kms_init(struct drm_device *dev);
+
+/**
+ * Mode Set Utility Functions
+ */
+static inline bool msm_is_mode_seamless(const struct drm_display_mode *mode)
+{
+	return (mode->flags & DRM_MODE_FLAG_SEAMLESS);
+}
+
+static inline bool msm_is_mode_dynamic_fps(const struct drm_display_mode *mode)
+{
+	return ((mode->flags & DRM_MODE_FLAG_SEAMLESS) &&
+		(mode->private_flags & MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS));
+}
+
+static inline bool msm_needs_vblank_pre_modeset(
+		const struct drm_display_mode *mode)
+{
+	return (mode->private_flags & MSM_MODE_FLAG_VBLANK_PRE_MODESET);
+}
 
 #endif /* __MSM_KMS_H__ */
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
index 7cd88d9dc1555f4e4f20482c58650fdcc7689d7c..cbf0d4593522b3e62d4ab6193c62361f390c79db 100644
--- a/drivers/gpu/drm/msm/msm_mmu.h
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -20,6 +20,17 @@
 
 #include <linux/iommu.h>
 
+struct msm_mmu;
+struct msm_gpu;
+
+enum msm_mmu_domain_type {
+	MSM_SMMU_DOMAIN_UNSECURE,
+	MSM_SMMU_DOMAIN_NRT_UNSECURE,
+	MSM_SMMU_DOMAIN_SECURE,
+	MSM_SMMU_DOMAIN_NRT_SECURE,
+	MSM_SMMU_DOMAIN_MAX,
+};
+
 struct msm_mmu_funcs {
 	int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
 	void (*detach)(struct msm_mmu *mmu, const char **names, int cnt);
@@ -27,6 +38,14 @@ struct msm_mmu_funcs {
 			unsigned len, int prot);
 	int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
 			unsigned len);
+	int (*map_sg)(struct msm_mmu *mmu, struct sg_table *sgt,
+			enum dma_data_direction dir);
+	void (*unmap_sg)(struct msm_mmu *mmu, struct sg_table *sgt,
+		enum dma_data_direction dir);
+	int (*map_dma_buf)(struct msm_mmu *mmu, struct sg_table *sgt,
+			struct dma_buf *dma_buf, int dir);
+	void (*unmap_dma_buf)(struct msm_mmu *mmu, struct sg_table *sgt,
+			struct dma_buf *dma_buf, int dir);
 	void (*destroy)(struct msm_mmu *mmu);
 };
 
@@ -44,5 +63,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
 
 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain);
 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
+struct msm_mmu *msm_smmu_new(struct device *dev,
+	enum msm_mmu_domain_type domain);
 
 #endif /* __MSM_MMU_H__ */
diff --git a/drivers/gpu/drm/msm/msm_prop.c b/drivers/gpu/drm/msm/msm_prop.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a9e472ea59b600e201d0f2447865321f4ac46de
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_prop.c
@@ -0,0 +1,662 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm_prop.h"
+
+void msm_property_init(struct msm_property_info *info,
+		struct drm_mode_object *base,
+		struct drm_device *dev,
+		struct drm_property **property_array,
+		struct msm_property_data *property_data,
+		uint32_t property_count,
+		uint32_t blob_count,
+		uint32_t state_size)
+{
+	int i;
+
+	/* prevent access if any of these are NULL */
+	if (!base || !dev || !property_array || !property_data) {
+		property_count = 0;
+		blob_count = 0;
+
+		DRM_ERROR("invalid arguments, forcing zero properties\n");
+		return;
+	}
+
+	/* can't have more blob properties than total properties */
+	if (blob_count > property_count) {
+		blob_count = property_count;
+
+		DBG("Capping number of blob properties to %d", blob_count);
+	}
+
+	if (!info) {
+		DRM_ERROR("info pointer is NULL\n");
+	} else {
+		info->base = base;
+		info->dev = dev;
+		info->property_array = property_array;
+		info->property_data = property_data;
+		info->property_count = property_count;
+		info->blob_count = blob_count;
+		info->install_request = 0;
+		info->install_count = 0;
+		info->recent_idx = 0;
+		info->is_active = false;
+		info->state_size = state_size;
+		info->state_cache_size = 0;
+		mutex_init(&info->property_lock);
+
+		memset(property_data,
+				0,
+				sizeof(struct msm_property_data) *
+				property_count);
+		INIT_LIST_HEAD(&info->dirty_list);
+
+		for (i = 0; i < property_count; ++i)
+			INIT_LIST_HEAD(&property_data[i].dirty_node);
+	}
+}
+
+void msm_property_destroy(struct msm_property_info *info)
+{
+	if (!info)
+		return;
+
+	/* reset dirty list */
+	INIT_LIST_HEAD(&info->dirty_list);
+
+	/* free state cache */
+	while (info->state_cache_size > 0)
+		kfree(info->state_cache[--(info->state_cache_size)]);
+
+	mutex_destroy(&info->property_lock);
+}
+
+int msm_property_pop_dirty(struct msm_property_info *info)
+{
+	struct list_head *item;
+	int rc = 0;
+
+	if (!info) {
+		DRM_ERROR("invalid info\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&info->property_lock);
+	if (list_empty(&info->dirty_list)) {
+		rc = -EAGAIN;
+	} else {
+		item = info->dirty_list.next;
+		list_del_init(item);
+		rc = container_of(item, struct msm_property_data, dirty_node)
+			- info->property_data;
+		DRM_DEBUG_KMS("property %d dirty\n", rc);
+	}
+	mutex_unlock(&info->property_lock);
+
+	return rc;
+}
+
+/**
+ * _msm_property_set_dirty_no_lock - flag given property as being dirty
+ *                                   This function doesn't mutex protect the
+ *                                   dirty linked list.
+ * @info: Pointer to property info container struct
+ * @property_idx: Property index
+ */
+static void _msm_property_set_dirty_no_lock(
+		struct msm_property_info *info,
+		uint32_t property_idx)
+{
+	if (!info || property_idx >= info->property_count) {
+		DRM_ERROR("invalid argument(s), info %pK, idx %u\n",
+				info, property_idx);
+		return;
+	}
+
+	/* avoid re-inserting if already dirty */
+	if (!list_empty(&info->property_data[property_idx].dirty_node)) {
+		DRM_DEBUG_KMS("property %u already dirty\n", property_idx);
+		return;
+	}
+
+	list_add_tail(&info->property_data[property_idx].dirty_node,
+			&info->dirty_list);
+}
+
+/**
+ * _msm_property_install_integer - install standard drm range property
+ * @info: Pointer to property info container struct
+ * @name: Property name
+ * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
+ * @min: Min property value
+ * @max: Max property value
+ * @init: Default Property value
+ * @property_idx: Property index
+ * @force_dirty: Whether or not to filter 'dirty' status on unchanged values
+ */
+static void _msm_property_install_integer(struct msm_property_info *info,
+		const char *name, int flags, uint64_t min, uint64_t max,
+		uint64_t init, uint32_t property_idx, bool force_dirty)
+{
+	struct drm_property **prop;
+
+	if (!info)
+		return;
+
+	++info->install_request;
+
+	if (!name || (property_idx >= info->property_count)) {
+		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
+	} else {
+		prop = &info->property_array[property_idx];
+		/*
+		 * Properties need to be attached to each drm object that
+		 * uses them, but only need to be created once
+		 */
+		if (*prop == 0) {
+			*prop = drm_property_create_range(info->dev,
+					flags, name, min, max);
+			if (*prop == 0)
+				DRM_ERROR("create %s property failed\n", name);
+		}
+
+		/* save init value for later */
+		info->property_data[property_idx].default_value = init;
+		info->property_data[property_idx].force_dirty = force_dirty;
+
+		/* always attach property, if created */
+		if (*prop) {
+			drm_object_attach_property(info->base, *prop, init);
+			++info->install_count;
+		}
+	}
+}
+
+void msm_property_install_range(struct msm_property_info *info,
+		const char *name, int flags, uint64_t min, uint64_t max,
+		uint64_t init, uint32_t property_idx)
+{
+	_msm_property_install_integer(info, name, flags,
+			min, max, init, property_idx, false);
+}
+
+void msm_property_install_volatile_range(struct msm_property_info *info,
+		const char *name, int flags, uint64_t min, uint64_t max,
+		uint64_t init, uint32_t property_idx)
+{
+	_msm_property_install_integer(info, name, flags,
+			min, max, init, property_idx, true);
+}
+
+void msm_property_install_rotation(struct msm_property_info *info,
+		unsigned int supported_rotations, uint32_t property_idx)
+{
+	struct drm_property **prop;
+
+	if (!info)
+		return;
+
+	++info->install_request;
+
+	if (property_idx >= info->property_count) {
+		DRM_ERROR("invalid property index %d\n", property_idx);
+	} else {
+		prop = &info->property_array[property_idx];
+		/*
+		 * Properties need to be attached to each drm object that
+		 * uses them, but only need to be created once
+		 */
+		if (*prop == 0) {
+			*prop = drm_mode_create_rotation_property(info->dev,
+					supported_rotations);
+			if (*prop == 0)
+				DRM_ERROR("create rotation property failed\n");
+		}
+
+		/* save init value for later */
+		info->property_data[property_idx].default_value = 0;
+		info->property_data[property_idx].force_dirty = false;
+
+		/* always attach property, if created */
+		if (*prop) {
+			drm_object_attach_property(info->base, *prop, 0);
+			++info->install_count;
+		}
+	}
+}
+
+void msm_property_install_enum(struct msm_property_info *info,
+		const char *name, int flags, int is_bitmask,
+		const struct drm_prop_enum_list *values, int num_values,
+		uint32_t property_idx)
+{
+	struct drm_property **prop;
+
+	if (!info)
+		return;
+
+	++info->install_request;
+
+	if (!name || !values || !num_values ||
+			(property_idx >= info->property_count)) {
+		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
+	} else {
+		prop = &info->property_array[property_idx];
+		/*
+		 * Properties need to be attached to each drm object that
+		 * uses them, but only need to be created once
+		 */
+		if (*prop == 0) {
+			/* 'bitmask' is a special type of 'enum' */
+			if (is_bitmask)
+				*prop = drm_property_create_bitmask(info->dev,
+						DRM_MODE_PROP_BITMASK | flags,
+						name, values, num_values, -1);
+			else
+				*prop = drm_property_create_enum(info->dev,
+						DRM_MODE_PROP_ENUM | flags,
+						name, values, num_values);
+			if (*prop == 0)
+				DRM_ERROR("create %s property failed\n", name);
+		}
+
+		/* save init value for later */
+		info->property_data[property_idx].default_value = 0;
+		info->property_data[property_idx].force_dirty = false;
+
+		/* always attach property, if created */
+		if (*prop) {
+			drm_object_attach_property(info->base, *prop, 0);
+			++info->install_count;
+		}
+	}
+}
+
+void msm_property_install_blob(struct msm_property_info *info,
+		const char *name, int flags, uint32_t property_idx)
+{
+	struct drm_property **prop;
+
+	if (!info)
+		return;
+
+	++info->install_request;
+
+	if (!name || (property_idx >= info->blob_count)) {
+		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
+	} else {
+		prop = &info->property_array[property_idx];
+		/*
+		 * Properties need to be attached to each drm object that
+		 * uses them, but only need to be created once
+		 */
+		if (*prop == 0) {
+			/* use 'create' for blob property place holder */
+			*prop = drm_property_create(info->dev,
+					DRM_MODE_PROP_BLOB | flags, name, 0);
+			if (*prop == 0)
+				DRM_ERROR("create %s property failed\n", name);
+		}
+
+		/* save init value for later */
+		info->property_data[property_idx].default_value = 0;
+		info->property_data[property_idx].force_dirty = true;
+
+		/* always attach property, if created */
+		if (*prop) {
+			drm_object_attach_property(info->base, *prop, -1);
+			++info->install_count;
+		}
+	}
+}
+
+int msm_property_install_get_status(struct msm_property_info *info)
+{
+	int rc = -ENOMEM;
+
+	if (info && (info->install_request == info->install_count))
+		rc = 0;
+
+	return rc;
+}
+
+int msm_property_index(struct msm_property_info *info,
+		struct drm_property *property)
+{
+	uint32_t count;
+	int32_t idx;
+	int rc = -EINVAL;
+
+	if (!info || !property) {
+		DRM_ERROR("invalid argument(s)\n");
+	} else {
+		/*
+		 * Linear search, but start from last found index. This will
+		 * help if any single property is accessed multiple times in a
+		 * row. Ideally, we could keep a list of properties sorted in
+		 * the order of most recent access, but that may be overkill
+		 * for now.
+		 */
+		mutex_lock(&info->property_lock);
+		idx = info->recent_idx;
+		count = info->property_count;
+		while (count) {
+			--count;
+
+			/* stop searching on match */
+			if (info->property_array[idx] == property) {
+				info->recent_idx = idx;
+				rc = idx;
+				break;
+			}
+
+			/* move to next valid index */
+			if (--idx < 0)
+				idx = info->property_count - 1;
+		}
+		mutex_unlock(&info->property_lock);
+	}
+
+	return rc;
+}
+
+int msm_property_atomic_set(struct msm_property_info *info,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs,
+		struct drm_property *property, uint64_t val)
+{
+	struct drm_property_blob *blob;
+	int property_idx, rc = -EINVAL;
+
+	property_idx = msm_property_index(info, property);
+	if (!info || (property_idx == -EINVAL) || !property_values) {
+		DRM_DEBUG("Invalid argument(s)\n");
+	} else {
+		/* extra handling for incoming properties */
+		mutex_lock(&info->property_lock);
+		if ((property->flags & DRM_MODE_PROP_BLOB) &&
+			(property_idx < info->blob_count) &&
+			property_blobs) {
+			/* DRM lookup also takes a reference */
+			blob = drm_property_lookup_blob(info->dev,
+				(uint32_t)val);
+			if (!blob) {
+				DRM_ERROR("blob not found\n");
+				val = 0;
+			} else {
+				DBG("Blob %u saved", blob->base.id);
+				val = blob->base.id;
+
+				/* save blob - need to clear previous ref */
+				if (property_blobs[property_idx])
+					drm_property_unreference_blob(
+						property_blobs[property_idx]);
+				property_blobs[property_idx] = blob;
+			}
+		}
+
+		/* update value and flag as dirty */
+		if (property_values[property_idx] != val ||
+				info->property_data[property_idx].force_dirty) {
+			property_values[property_idx] = val;
+			_msm_property_set_dirty_no_lock(info, property_idx);
+
+			DBG("%s - %lld", property->name, val);
+		}
+		mutex_unlock(&info->property_lock);
+		rc = 0;
+	}
+
+	return rc;
+}
+
+int msm_property_atomic_get(struct msm_property_info *info,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs,
+		struct drm_property *property, uint64_t *val)
+{
+	int property_idx, rc = -EINVAL;
+
+	property_idx = msm_property_index(info, property);
+	if (!info || (property_idx == -EINVAL) || !property_values || !val) {
+		DRM_DEBUG("Invalid argument(s)\n");
+	} else {
+		mutex_lock(&info->property_lock);
+		*val = property_values[property_idx];
+		mutex_unlock(&info->property_lock);
+		rc = 0;
+	}
+
+	return rc;
+}
+
+void *msm_property_alloc_state(struct msm_property_info *info)
+{
+	void *state = NULL;
+
+	if (!info) {
+		DRM_ERROR("invalid property info\n");
+		return NULL;
+	}
+
+	mutex_lock(&info->property_lock);
+	if (info->state_cache_size)
+		state = info->state_cache[--(info->state_cache_size)];
+	mutex_unlock(&info->property_lock);
+
+	if (!state && info->state_size)
+		state = kmalloc(info->state_size, GFP_KERNEL);
+
+	if (!state)
+		DRM_ERROR("failed to allocate state\n");
+
+	return state;
+}
+
+/**
+ * _msm_property_free_state - helper function for freeing local state objects
+ * @info: Pointer to property info container struct
+ * @st: Pointer to state object
+ */
+static void _msm_property_free_state(struct msm_property_info *info, void *st)
+{
+	if (!info || !st)
+		return;
+
+	mutex_lock(&info->property_lock);
+	if (info->state_cache_size < MSM_PROP_STATE_CACHE_SIZE)
+		info->state_cache[(info->state_cache_size)++] = st;
+	else
+		kfree(st);
+	mutex_unlock(&info->property_lock);
+}
+
+void msm_property_reset_state(struct msm_property_info *info, void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs)
+{
+	uint32_t i;
+
+	if (!info) {
+		DRM_ERROR("invalid property info\n");
+		return;
+	}
+
+	if (state)
+		memset(state, 0, info->state_size);
+
+	/*
+	 * Assign default property values. This helper is mostly used
+	 * to initialize newly created state objects.
+	 */
+	if (property_values)
+		for (i = 0; i < info->property_count; ++i)
+			property_values[i] =
+				info->property_data[i].default_value;
+
+	if (property_blobs)
+		for (i = 0; i < info->blob_count; ++i)
+			property_blobs[i] = 0;
+}
+
+void msm_property_duplicate_state(struct msm_property_info *info,
+		void *old_state, void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs)
+{
+	uint32_t i;
+
+	if (!info || !old_state || !state) {
+		DRM_ERROR("invalid argument(s)\n");
+		return;
+	}
+
+	memcpy(state, old_state, info->state_size);
+
+	if (property_blobs) {
+		/* add ref count for blobs */
+		for (i = 0; i < info->blob_count; ++i)
+			if (property_blobs[i])
+				drm_property_reference_blob(property_blobs[i]);
+	}
+}
+
+void msm_property_destroy_state(struct msm_property_info *info, void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs)
+{
+	uint32_t i;
+
+	if (!info || !state) {
+		DRM_ERROR("invalid argument(s)\n");
+		return;
+	}
+	if (property_blobs) {
+		/* remove ref count for blobs */
+		for (i = 0; i < info->blob_count; ++i)
+			if (property_blobs[i])
+				drm_property_unreference_blob(
+						property_blobs[i]);
+	}
+
+	_msm_property_free_state(info, state);
+}
+
+void *msm_property_get_blob(struct msm_property_info *info,
+		struct drm_property_blob **property_blobs,
+		size_t *byte_len,
+		uint32_t property_idx)
+{
+	struct drm_property_blob *blob;
+	size_t len = 0;
+	void *rc = 0;
+
+	if (!info || !property_blobs || (property_idx >= info->blob_count)) {
+		DRM_ERROR("invalid argument(s)\n");
+	} else {
+		blob = property_blobs[property_idx];
+		if (blob) {
+			len = blob->length;
+			rc = &blob->data;
+		}
+	}
+
+	if (byte_len)
+		*byte_len = len;
+
+	return rc;
+}
+
+int msm_property_set_blob(struct msm_property_info *info,
+		struct drm_property_blob **blob_reference,
+		void *blob_data,
+		size_t byte_len,
+		uint32_t property_idx)
+{
+	struct drm_property_blob *blob = NULL;
+	int rc = -EINVAL;
+
+	if (!info || !blob_reference || (property_idx >= info->blob_count)) {
+		DRM_ERROR("invalid argument(s)\n");
+	} else {
+		/* create blob */
+		if (blob_data && byte_len) {
+			blob = drm_property_create_blob(info->dev,
+					byte_len,
+					blob_data);
+			if (IS_ERR_OR_NULL(blob)) {
+				rc = PTR_ERR(blob);
+				DRM_ERROR("failed to create blob, %d\n", rc);
+				goto exit;
+			}
+		}
+
+		/* update drm object */
+		rc = drm_object_property_set_value(info->base,
+				info->property_array[property_idx],
+				blob ? blob->base.id : 0);
+		if (rc) {
+			DRM_ERROR("failed to set blob to property\n");
+			if (blob)
+				drm_property_unreference_blob(blob);
+			goto exit;
+		}
+
+		/* update local reference */
+		if (*blob_reference)
+			drm_property_unreference_blob(*blob_reference);
+		*blob_reference = blob;
+	}
+
+exit:
+	return rc;
+}
+
+int msm_property_set_property(struct msm_property_info *info,
+		uint64_t *property_values,
+		uint32_t property_idx,
+		uint64_t val)
+{
+	int rc = -EINVAL;
+
+	if (!info || (property_idx >= info->property_count) ||
+			property_idx < info->blob_count || !property_values) {
+		DRM_ERROR("invalid argument(s)\n");
+	} else {
+		struct drm_property *drm_prop;
+
+		mutex_lock(&info->property_lock);
+
+		/* update cached value */
+		if (property_values)
+			property_values[property_idx] = val;
+
+		/* update the new default value for immutables */
+		drm_prop = info->property_array[property_idx];
+		if (drm_prop->flags & DRM_MODE_PROP_IMMUTABLE)
+			info->property_data[property_idx].default_value = val;
+
+		mutex_unlock(&info->property_lock);
+
+		/* update drm object */
+		rc = drm_object_property_set_value(info->base, drm_prop, val);
+		if (rc)
+			DRM_ERROR("failed set property value, idx %d rc %d\n",
+					property_idx, rc);
+
+	}
+
+	return rc;
+}
+
diff --git a/drivers/gpu/drm/msm/msm_prop.h b/drivers/gpu/drm/msm/msm_prop.h
new file mode 100644
index 0000000000000000000000000000000000000000..dbe28bdf56380bf3824d7dd9ebd7788979c62588
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_prop.h
@@ -0,0 +1,391 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MSM_PROP_H_
+#define _MSM_PROP_H_
+
+#include <linux/list.h>
+#include "msm_drv.h"
+
+#define MSM_PROP_STATE_CACHE_SIZE	2
+
+/**
+ * struct msm_property_data - opaque structure for tracking per
+ *                            drm-object per property stuff
+ * @default_value: Default property value for this drm object
+ * @dirty_node: Linked list node to track if property is dirty or not
+ * @force_dirty: Always dirty property on incoming sets, rather than checking
+ *               for modified values
+ */
+struct msm_property_data {
+	uint64_t default_value;
+	struct list_head dirty_node;
+	bool force_dirty;
+};
+
+/**
+ * struct msm_property_info: Structure for property/state helper functions
+ * @base: Pointer to base drm object (plane/crtc/etc.)
+ * @dev: Pointer to drm device object
+ * @property_array: Pointer to array for storing created property objects
+ * @property_data: Pointer to array for storing private property data
+ * @property_count: Total number of properties
+ * @blob_count: Total number of blob properties, should be <= count
+ * @install_request: Total number of property 'install' requests
+ * @install_count: Total number of successful 'install' requests
+ * @recent_idx: Index of property most recently accessed by set/get
+ * @dirty_list: List of all properties that have been 'atomic_set' but not
+ *              yet cleared with 'msm_property_pop_dirty'
+ * @is_active: Whether or not drm component properties are 'active'
+ * @state_cache: Cache of local states, to prevent alloc/free thrashing
+ * @state_size: Size of local state structures
+ * @state_cache_size: Number of state structures currently stored in state_cache
+ * @property_lock: Mutex to protect local variables
+ */
+struct msm_property_info {
+	struct drm_mode_object *base;
+	struct drm_device *dev;
+
+	struct drm_property **property_array;
+	struct msm_property_data *property_data;
+	uint32_t property_count;
+	uint32_t blob_count;
+	uint32_t install_request;
+	uint32_t install_count;
+
+	int32_t recent_idx;
+
+	struct list_head dirty_list;
+	bool is_active;
+
+	void *state_cache[MSM_PROP_STATE_CACHE_SIZE];
+	uint32_t state_size;
+	int32_t state_cache_size;
+	struct mutex property_lock;
+};
+
+/**
+ * msm_property_get_default - query default value of a property
+ * @info: Pointer to property info container struct
+ * @property_idx: Property index
+ * Returns: Default value for specified property
+ */
+static inline
+uint64_t msm_property_get_default(struct msm_property_info *info,
+		uint32_t property_idx)
+{
+	uint64_t rc = 0;
+
+	if (!info)
+		return 0;
+
+	mutex_lock(&info->property_lock);
+	if (property_idx < info->property_count)
+		rc = info->property_data[property_idx].default_value;
+	mutex_unlock(&info->property_lock);
+
+	return rc;
+}
+
+/**
+ * msm_property_set_is_active - set overall 'active' status for all properties
+ * @info: Pointer to property info container struct
+ * @is_active: New 'is active' status
+ */
+static inline
+void msm_property_set_is_active(struct msm_property_info *info, bool is_active)
+{
+	if (info) {
+		mutex_lock(&info->property_lock);
+		info->is_active = is_active;
+		mutex_unlock(&info->property_lock);
+	}
+}
+
+/**
+ * msm_property_get_is_active - query property 'is active' status
+ * @info: Pointer to property info container struct
+ * Returns: Current 'is active's status
+ */
+static inline
+bool msm_property_get_is_active(struct msm_property_info *info)
+{
+	bool rc = false;
+
+	if (info) {
+		mutex_lock(&info->property_lock);
+		rc = info->is_active;
+		mutex_unlock(&info->property_lock);
+	}
+
+	return rc;
+}
+
+/**
+ * msm_property_pop_dirty - determine next dirty property and clear
+ *                          its dirty flag
+ * @info: Pointer to property info container struct
+ * Returns: Valid msm property index on success,
+ *          -EAGAIN if no dirty properties are available
+ *          Property indicies returned from this function are similar
+ *          to those returned by the msm_property_index function.
+ */
+int msm_property_pop_dirty(struct msm_property_info *info);
+
+/**
+ * msm_property_init - initialize property info structure
+ * @info: Pointer to property info container struct
+ * @base: Pointer to base drm object (plane/crtc/etc.)
+ * @dev: Pointer to drm device object
+ * @property_array: Pointer to array for storing created property objects
+ * @property_data: Pointer to array for storing private property data
+ * @property_count: Total number of properties
+ * @blob_count: Total number of blob properties, should be <= count
+ * @state_size: Size of local state object
+ */
+void msm_property_init(struct msm_property_info *info,
+		struct drm_mode_object *base,
+		struct drm_device *dev,
+		struct drm_property **property_array,
+		struct msm_property_data *property_data,
+		uint32_t property_count,
+		uint32_t blob_count,
+		uint32_t state_size);
+
+/**
+ * msm_property_destroy - destroy helper info structure
+ *
+ * @info: Pointer to property info container struct
+ */
+void msm_property_destroy(struct msm_property_info *info);
+
+/**
+ * msm_property_install_range - install standard drm range property
+ * @info: Pointer to property info container struct
+ * @name: Property name
+ * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
+ * @min: Min property value
+ * @max: Max property value
+ * @init: Default Property value
+ * @property_idx: Property index
+ */
+void msm_property_install_range(struct msm_property_info *info,
+		const char *name,
+		int flags,
+		uint64_t min,
+		uint64_t max,
+		uint64_t init,
+		uint32_t property_idx);
+
+/**
+ * msm_property_install_volatile_range - install drm range property
+ *	This function is similar to msm_property_install_range, but assumes
+ *	that the property is meant for holding user pointers or descriptors
+ *	that may reference volatile data without having an updated value.
+ * @info: Pointer to property info container struct
+ * @name: Property name
+ * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
+ * @min: Min property value
+ * @max: Max property value
+ * @init: Default Property value
+ * @property_idx: Property index
+ */
+void msm_property_install_volatile_range(struct msm_property_info *info,
+		const char *name,
+		int flags,
+		uint64_t min,
+		uint64_t max,
+		uint64_t init,
+		uint32_t property_idx);
+
+/**
+ * msm_property_install_rotation - install standard drm rotation property
+ * @info: Pointer to property info container struct
+ * @supported_rotations: Bitmask of supported rotation values (see
+ *                       drm_mode_create_rotation_property for more details)
+ * @property_idx: Property index
+ */
+void msm_property_install_rotation(struct msm_property_info *info,
+		unsigned int supported_rotations,
+		uint32_t property_idx);
+
+/**
+ * msm_property_install_enum - install standard drm enum/bitmask property
+ * @info: Pointer to property info container struct
+ * @name: Property name
+ * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
+ * @is_bitmask: Set to non-zero to create a bitmask property, rather than an
+ *              enumeration one
+ * @values: Array of allowable enumeration/bitmask values
+ * @num_values: Size of values array
+ * @property_idx: Property index
+ */
+void msm_property_install_enum(struct msm_property_info *info,
+		const char *name,
+		int flags,
+		int is_bitmask,
+		const struct drm_prop_enum_list *values,
+		int num_values,
+		uint32_t property_idx);
+
+/**
+ * msm_property_install_blob - install standard drm blob property
+ * @info: Pointer to property info container struct
+ * @name: Property name
+ * @flags: Extra flags for property creation
+ * @property_idx: Property index
+ */
+void msm_property_install_blob(struct msm_property_info *info,
+		const char *name,
+		int flags,
+		uint32_t property_idx);
+
+/**
+ * msm_property_install_get_status - query overal status of property additions
+ * @info: Pointer to property info container struct
+ * Returns: Zero if previous property install calls were all successful
+ */
+int msm_property_install_get_status(struct msm_property_info *info);
+
+/**
+ * msm_property_index - determine property index from drm_property ptr
+ * @info: Pointer to property info container struct
+ * @property: Incoming property pointer
+ * Returns: Valid property index, or -EINVAL on error
+ */
+int msm_property_index(struct msm_property_info *info,
+		struct drm_property *property);
+
+/**
+ * msm_property_atomic_set - helper function for atomic property set callback
+ * @info: Pointer to property info container struct
+ * @property_values: Pointer to property values cache array
+ * @property_blobs: Pointer to property blobs cache array
+ * @property: Incoming property pointer
+ * @val: Incoming property value
+ * Returns: Zero on success
+ */
+int msm_property_atomic_set(struct msm_property_info *info,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs,
+		struct drm_property *property,
+		uint64_t val);
+
+/**
+ * msm_property_atomic_get - helper function for atomic property get callback
+ * @info: Pointer to property info container struct
+ * @property_values: Pointer to property values cache array
+ * @property_blobs: Pointer to property blobs cache array
+ * @property: Incoming property pointer
+ * @val: Pointer to variable for receiving property value
+ * Returns: Zero on success
+ */
+int msm_property_atomic_get(struct msm_property_info *info,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs,
+		struct drm_property *property,
+		uint64_t *val);
+
+/**
+ * msm_property_alloc_state - helper function for allocating local state objects
+ * @info: Pointer to property info container struct
+ */
+void *msm_property_alloc_state(struct msm_property_info *info);
+
+/**
+ * msm_property_reset_state - helper function for state reset callback
+ * @info: Pointer to property info container struct
+ * @state: Pointer to local state structure
+ * @property_values: Pointer to property values cache array
+ * @property_blobs: Pointer to property blobs cache array
+ */
+void msm_property_reset_state(struct msm_property_info *info,
+		void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs);
+
+/**
+ * msm_property_duplicate_state - helper function for duplicate state cb
+ * @info: Pointer to property info container struct
+ * @old_state: Pointer to original state structure
+ * @state: Pointer to newly created state structure
+ * @property_values: Pointer to property values cache array
+ * @property_blobs: Pointer to property blobs cache array
+ */
+void msm_property_duplicate_state(struct msm_property_info *info,
+		void *old_state,
+		void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs);
+
+/**
+ * msm_property_destroy_state - helper function for destroy state cb
+ * @info: Pointer to property info container struct
+ * @state: Pointer to local state structure
+ * @property_values: Pointer to property values cache array
+ * @property_blobs: Pointer to property blobs cache array
+ */
+void msm_property_destroy_state(struct msm_property_info *info,
+		void *state,
+		uint64_t *property_values,
+		struct drm_property_blob **property_blobs);
+
+/**
+ * msm_property_get_blob - obtain cached data pointer for drm blob property
+ * @info: Pointer to property info container struct
+ * @property_blobs: Pointer to property blobs cache array
+ * @byte_len: Optional pointer to variable for accepting blob size
+ * @property_idx: Property index
+ * Returns: Pointer to blob data
+ */
+void *msm_property_get_blob(struct msm_property_info *info,
+		struct drm_property_blob **property_blobs,
+		size_t *byte_len,
+		uint32_t property_idx);
+
+/**
+ * msm_property_set_blob - update blob property on a drm object
+ * This function updates the blob property value of the given drm object. Its
+ * intended use is to update blob properties that have been created with the
+ * DRM_MODE_PROP_IMMUTABLE flag set.
+ * @info: Pointer to property info container struct
+ * @blob_reference: Reference to a pointer that holds the created data blob
+ * @blob_data: Pointer to blob data
+ * @byte_len: Length of blob data, in bytes
+ * @property_idx: Property index
+ * Returns: Zero on success
+ */
+int msm_property_set_blob(struct msm_property_info *info,
+		struct drm_property_blob **blob_reference,
+		void *blob_data,
+		size_t byte_len,
+		uint32_t property_idx);
+
+/**
+ * msm_property_set_property - update property on a drm object
+ * This function updates the property value of the given drm object. Its
+ * intended use is to update properties that have been created with the
+ * DRM_MODE_PROP_IMMUTABLE flag set.
+ * Note: This function cannot be called on a blob.
+ * @info: Pointer to property info container struct
+ * @property_values: Pointer to property values cache array
+ * @property_idx: Property index
+ * @val: value of the property to set
+ * Returns: Zero on success
+ */
+int msm_property_set_property(struct msm_property_info *info,
+		uint64_t *property_values,
+		uint32_t property_idx,
+		uint64_t val);
+
+#endif /* _MSM_PROP_H_ */
+
diff --git a/drivers/gpu/drm/msm/msm_smmu.c b/drivers/gpu/drm/msm/msm_smmu.c
new file mode 100644
index 0000000000000000000000000000000000000000..f29c1df46691d8d78213e8fa54ab091fba372b3b
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_smmu.c
@@ -0,0 +1,502 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/msm_dma_iommu_mapping.h>
+
+#include <asm/dma-iommu.h>
+#include <soc/qcom/secure_buffer.h>
+
+#include "msm_drv.h"
+#include "msm_mmu.h"
+
+#ifndef SZ_4G
+#define SZ_4G	(((size_t) SZ_1G) * 4)
+#endif
+
+struct msm_smmu_client {
+	struct device *dev;
+	struct dma_iommu_mapping *mmu_mapping;
+	bool domain_attached;
+};
+
+struct msm_smmu {
+	struct msm_mmu base;
+	struct device *client_dev;
+	struct msm_smmu_client *client;
+};
+
+struct msm_smmu_domain {
+	const char *label;
+	size_t va_start;
+	size_t va_size;
+	bool secure;
+};
+
+#define to_msm_smmu(x) container_of(x, struct msm_smmu, base)
+#define msm_smmu_to_client(smmu) (smmu->client)
+
+static int _msm_smmu_create_mapping(struct msm_smmu_client *client,
+	const struct msm_smmu_domain *domain);
+
+static int msm_smmu_attach(struct msm_mmu *mmu, const char **names, int cnt)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+	int rc = 0;
+
+	if (!client) {
+		pr_err("undefined smmu client\n");
+		return -EINVAL;
+	}
+
+	/* domain attach only once */
+	if (client->domain_attached)
+		return 0;
+
+	rc = arm_iommu_attach_device(client->dev,
+			client->mmu_mapping);
+	if (rc) {
+		dev_err(client->dev, "iommu attach dev failed (%d)\n",
+				rc);
+		return rc;
+	}
+
+	client->domain_attached = true;
+
+	dev_dbg(client->dev, "iommu domain attached\n");
+
+	return 0;
+}
+
+static void msm_smmu_detach(struct msm_mmu *mmu, const char **names, int cnt)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+
+	if (!client) {
+		pr_err("undefined smmu client\n");
+		return;
+	}
+
+	if (!client->domain_attached)
+		return;
+
+	arm_iommu_detach_device(client->dev);
+	client->domain_attached = false;
+	dev_dbg(client->dev, "iommu domain detached\n");
+}
+
+static int msm_smmu_map(struct msm_mmu *mmu, uint32_t iova,
+		struct sg_table *sgt, unsigned len, int prot)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+	struct iommu_domain *domain;
+	struct scatterlist *sg;
+	unsigned int da = iova;
+	unsigned int i, j;
+	int ret;
+
+	if (!client)
+		return -ENODEV;
+
+	domain = client->mmu_mapping->domain;
+	if (!domain || !sgt)
+		return -EINVAL;
+
+	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+		u32 pa = sg_phys(sg) - sg->offset;
+		size_t bytes = sg->length + sg->offset;
+
+		VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes);
+
+		ret = iommu_map(domain, da, pa, bytes, prot);
+		if (ret)
+			goto fail;
+
+		da += bytes;
+	}
+
+	return 0;
+
+fail:
+	da = iova;
+
+	for_each_sg(sgt->sgl, sg, i, j) {
+		size_t bytes = sg->length + sg->offset;
+
+		iommu_unmap(domain, da, bytes);
+		da += bytes;
+	}
+	return ret;
+}
+
+static int msm_smmu_map_sg(struct msm_mmu *mmu, struct sg_table *sgt,
+		enum dma_data_direction dir)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+	int ret;
+
+	ret = dma_map_sg(client->dev, sgt->sgl, sgt->nents, dir);
+	if (ret != sgt->nents)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static void msm_smmu_unmap_sg(struct msm_mmu *mmu, struct sg_table *sgt,
+		enum dma_data_direction dir)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+
+	dma_unmap_sg(client->dev, sgt->sgl, sgt->nents, dir);
+}
+
+static int msm_smmu_unmap(struct msm_mmu *mmu, uint32_t iova,
+		struct sg_table *sgt, unsigned len)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+	struct iommu_domain *domain;
+	struct scatterlist *sg;
+	unsigned int da = iova;
+	int i;
+
+	if (!client)
+		return -ENODEV;
+
+	domain = client->mmu_mapping->domain;
+	if (!domain || !sgt)
+		return -EINVAL;
+
+	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+		size_t bytes = sg->length + sg->offset;
+		size_t unmapped;
+
+		unmapped = iommu_unmap(domain, da, bytes);
+		if (unmapped < bytes)
+			return unmapped;
+
+		VERB("unmap[%d]: %08x(%zx)", i, iova, bytes);
+
+		WARN_ON(!PAGE_ALIGNED(bytes));
+
+		da += bytes;
+	}
+
+	return 0;
+}
+
+static void msm_smmu_destroy(struct msm_mmu *mmu)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct platform_device *pdev = to_platform_device(smmu->client_dev);
+
+	if (smmu->client_dev)
+		platform_device_unregister(pdev);
+	kfree(smmu);
+}
+
+static int msm_smmu_map_dma_buf(struct msm_mmu *mmu, struct sg_table *sgt,
+			struct dma_buf *dma_buf, int dir)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+	int ret;
+
+	ret = msm_dma_map_sg_lazy(client->dev, sgt->sgl, sgt->nents, dir,
+			dma_buf);
+	if (ret != sgt->nents) {
+		DRM_ERROR("dma map sg failed\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+
+static void msm_smmu_unmap_dma_buf(struct msm_mmu *mmu, struct sg_table *sgt,
+			struct dma_buf *dma_buf, int dir)
+{
+	struct msm_smmu *smmu = to_msm_smmu(mmu);
+	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+
+	msm_dma_unmap_sg(client->dev, sgt->sgl, sgt->nents, dir, dma_buf);
+}
+
+static const struct msm_mmu_funcs funcs = {
+	.attach = msm_smmu_attach,
+	.detach = msm_smmu_detach,
+	.map = msm_smmu_map,
+	.map_sg = msm_smmu_map_sg,
+	.unmap_sg = msm_smmu_unmap_sg,
+	.unmap = msm_smmu_unmap,
+	.map_dma_buf = msm_smmu_map_dma_buf,
+	.unmap_dma_buf = msm_smmu_unmap_dma_buf,
+	.destroy = msm_smmu_destroy,
+};
+
+static struct msm_smmu_domain msm_smmu_domains[MSM_SMMU_DOMAIN_MAX] = {
+	[MSM_SMMU_DOMAIN_UNSECURE] = {
+		.label = "mdp_ns",
+		.va_start = SZ_128K,
+		.va_size = SZ_4G - SZ_128K,
+		.secure = false,
+	},
+	[MSM_SMMU_DOMAIN_SECURE] = {
+		.label = "mdp_s",
+		.va_start = 0,
+		.va_size = SZ_4G,
+		.secure = true,
+	},
+	[MSM_SMMU_DOMAIN_NRT_UNSECURE] = {
+		.label = "rot_ns",
+		.va_start = SZ_128K,
+		.va_size = SZ_4G - SZ_128K,
+		.secure = false,
+	},
+	[MSM_SMMU_DOMAIN_NRT_SECURE] = {
+		.label = "rot_s",
+		.va_start = 0,
+		.va_size = SZ_4G,
+		.secure = true,
+	},
+};
+
+static const struct of_device_id msm_smmu_dt_match[] = {
+	{ .compatible = "qcom,smmu_mdp_unsec",
+		.data = &msm_smmu_domains[MSM_SMMU_DOMAIN_UNSECURE] },
+	{ .compatible = "qcom,smmu_mdp_sec",
+		.data = &msm_smmu_domains[MSM_SMMU_DOMAIN_SECURE] },
+	{ .compatible = "qcom,smmu_rot_unsec",
+		.data = &msm_smmu_domains[MSM_SMMU_DOMAIN_NRT_UNSECURE] },
+	{ .compatible = "qcom,smmu_rot_sec",
+		.data = &msm_smmu_domains[MSM_SMMU_DOMAIN_NRT_SECURE] },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_smmu_dt_match);
+
+static struct device *msm_smmu_device_create(struct device *dev,
+		enum msm_mmu_domain_type domain,
+		struct msm_smmu *smmu)
+{
+	struct device_node *child;
+	struct platform_device *pdev;
+	int i;
+	const char *compat = NULL;
+
+	for (i = 0; i < ARRAY_SIZE(msm_smmu_dt_match); i++) {
+		if (msm_smmu_dt_match[i].data == &msm_smmu_domains[domain]) {
+			compat = msm_smmu_dt_match[i].compatible;
+			break;
+		}
+	}
+
+	if (!compat) {
+		DRM_ERROR("unable to find matching domain for %d\n", domain);
+		return ERR_PTR(-ENOENT);
+	}
+	DRM_INFO("found domain %d compat: %s\n", domain, compat);
+
+	if (domain == MSM_SMMU_DOMAIN_UNSECURE) {
+		int rc;
+
+		smmu->client = devm_kzalloc(dev,
+				sizeof(struct msm_smmu_client), GFP_KERNEL);
+		if (!smmu->client)
+			return ERR_PTR(-ENOMEM);
+
+		smmu->client->dev = dev;
+
+		rc = _msm_smmu_create_mapping(msm_smmu_to_client(smmu),
+			msm_smmu_dt_match[i].data);
+		if (rc) {
+			devm_kfree(dev, smmu->client);
+			smmu->client = NULL;
+			return ERR_PTR(rc);
+		}
+
+		return NULL;
+	}
+
+	child = of_find_compatible_node(dev->of_node, NULL, compat);
+	if (!child) {
+		DRM_ERROR("unable to find compatible node for %s\n", compat);
+		return ERR_PTR(-ENODEV);
+	}
+
+	pdev = of_platform_device_create(child, NULL, dev);
+	if (!pdev) {
+		DRM_ERROR("unable to create smmu platform dev for domain %d\n",
+				domain);
+		return ERR_PTR(-ENODEV);
+	}
+
+	smmu->client = platform_get_drvdata(pdev);
+
+	return &pdev->dev;
+}
+
+struct msm_mmu *msm_smmu_new(struct device *dev,
+		enum msm_mmu_domain_type domain)
+{
+	struct msm_smmu *smmu;
+	struct device *client_dev;
+
+	smmu = kzalloc(sizeof(*smmu), GFP_KERNEL);
+	if (!smmu)
+		return ERR_PTR(-ENOMEM);
+
+	client_dev = msm_smmu_device_create(dev, domain, smmu);
+	if (IS_ERR(client_dev)) {
+		kfree(smmu);
+		return (void *)client_dev ? : ERR_PTR(-ENODEV);
+	}
+
+	smmu->client_dev = client_dev;
+	msm_mmu_init(&smmu->base, dev, &funcs);
+
+	return &smmu->base;
+}
+
+static int _msm_smmu_create_mapping(struct msm_smmu_client *client,
+	const struct msm_smmu_domain *domain)
+{
+	int rc;
+
+	client->mmu_mapping = arm_iommu_create_mapping(&platform_bus_type,
+			domain->va_start, domain->va_size);
+	if (IS_ERR(client->mmu_mapping)) {
+		dev_err(client->dev,
+			"iommu create mapping failed for domain=%s\n",
+			domain->label);
+		return PTR_ERR(client->mmu_mapping);
+	}
+
+	if (domain->secure) {
+		int secure_vmid = VMID_CP_PIXEL;
+
+		rc = iommu_domain_set_attr(client->mmu_mapping->domain,
+				DOMAIN_ATTR_SECURE_VMID, &secure_vmid);
+		if (rc) {
+			dev_err(client->dev, "couldn't set secure pix vmid\n");
+			goto error;
+		}
+	}
+
+	DRM_INFO("Created domain %s [%zx,%zx] secure=%d\n",
+			domain->label, domain->va_start, domain->va_size,
+			domain->secure);
+
+	return 0;
+
+error:
+	arm_iommu_release_mapping(client->mmu_mapping);
+	return rc;
+}
+
+/**
+ * msm_smmu_probe()
+ * @pdev: platform device
+ *
+ * Each smmu context acts as a separate device and the context banks are
+ * configured with a VA range.
+ * Registers the clks as each context bank has its own clks, for which voting
+ * has to be done everytime before using that context bank.
+ */
+static int msm_smmu_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct msm_smmu_client *client;
+	const struct msm_smmu_domain *domain;
+	int rc;
+
+	match = of_match_device(msm_smmu_dt_match, &pdev->dev);
+	if (!match || !match->data) {
+		dev_err(&pdev->dev, "probe failed as match data is invalid\n");
+		return -EINVAL;
+	}
+
+	domain = match->data;
+	if (!domain) {
+		dev_err(&pdev->dev, "no matching device found\n");
+		return -EINVAL;
+	}
+
+	DRM_INFO("probing device %s\n", match->compatible);
+
+	client = devm_kzalloc(&pdev->dev, sizeof(*client), GFP_KERNEL);
+	if (!client)
+		return -ENOMEM;
+
+	client->dev = &pdev->dev;
+
+	rc = _msm_smmu_create_mapping(client, domain);
+	platform_set_drvdata(pdev, client);
+
+	return rc;
+}
+
+static int msm_smmu_remove(struct platform_device *pdev)
+{
+	struct msm_smmu_client *client;
+
+	client = platform_get_drvdata(pdev);
+	if (client->domain_attached) {
+		arm_iommu_detach_device(client->dev);
+		client->domain_attached = false;
+	}
+	arm_iommu_release_mapping(client->mmu_mapping);
+
+	return 0;
+}
+
+static struct platform_driver msm_smmu_driver = {
+	.probe = msm_smmu_probe,
+	.remove = msm_smmu_remove,
+	.driver = {
+		.name = "msmdrm_smmu",
+		.of_match_table = msm_smmu_dt_match,
+	},
+};
+
+static int __init msm_smmu_driver_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&msm_smmu_driver);
+	if (ret)
+		pr_err("mdss_smmu_register_driver() failed!\n");
+
+	return ret;
+}
+module_init(msm_smmu_driver_init);
+
+static void __exit msm_smmu_driver_cleanup(void)
+{
+	platform_driver_unregister(&msm_smmu_driver);
+}
+module_exit(msm_smmu_driver_cleanup);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MSM SMMU driver");
diff --git a/drivers/gpu/drm/msm/sde/sde_backlight.c b/drivers/gpu/drm/msm/sde/sde_backlight.c
new file mode 100644
index 0000000000000000000000000000000000000000..9034eeb944fef1bed345a79cde2af0bc13dbafc0
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_backlight.c
@@ -0,0 +1,103 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_connector.h"
+#include <linux/backlight.h>
+#include "dsi_drm.h"
+
+#define SDE_BRIGHT_TO_BL(out, v, bl_max, max_bright) do {\
+	out = (2 * (v) * (bl_max) + max_bright);\
+	do_div(out, 2 * max_bright);\
+} while (0)
+
+static int sde_backlight_device_update_status(struct backlight_device *bd)
+{
+	int brightness;
+	struct drm_connector *connector;
+	struct dsi_display *display;
+	struct sde_connector *c_conn;
+	int bl_lvl;
+
+	brightness = bd->props.brightness;
+
+	if ((bd->props.power != FB_BLANK_UNBLANK) ||
+			(bd->props.state & BL_CORE_FBBLANK) ||
+			(bd->props.state & BL_CORE_SUSPENDED))
+		brightness = 0;
+
+	connector = bl_get_data(bd);
+	c_conn = to_sde_connector(connector);
+	display = (struct dsi_display *) c_conn->display;
+	if (brightness > display->panel->bl_config.bl_max_level)
+		brightness = display->panel->bl_config.bl_max_level;
+
+	/* This maps UI brightness into driver backlight level with
+	 *        rounding
+	 */
+	SDE_BRIGHT_TO_BL(bl_lvl, brightness,
+			display->panel->bl_config.bl_max_level,
+			display->panel->bl_config.brightness_max_level);
+
+	if (!bl_lvl && brightness)
+		bl_lvl = 1;
+
+	if (c_conn->ops.set_backlight)
+		c_conn->ops.set_backlight(c_conn->display, bl_lvl);
+
+	return 0;
+}
+
+static int sde_backlight_device_get_brightness(struct backlight_device *bd)
+{
+	return 0;
+}
+
+static const struct backlight_ops sde_backlight_device_ops = {
+	.update_status = sde_backlight_device_update_status,
+	.get_brightness = sde_backlight_device_get_brightness,
+};
+
+int sde_backlight_setup(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+	struct backlight_device *bd;
+	struct backlight_properties props;
+	struct dsi_display *display;
+	struct dsi_backlight_config *bl_config;
+
+	if (!connector)
+		return -EINVAL;
+
+	c_conn = to_sde_connector(connector);
+	memset(&props, 0, sizeof(props));
+	props.type = BACKLIGHT_RAW;
+	props.power = FB_BLANK_UNBLANK;
+
+	switch (c_conn->connector_type) {
+	case DRM_MODE_CONNECTOR_DSI:
+		display = (struct dsi_display *) c_conn->display;
+		bl_config = &display->panel->bl_config;
+		props.max_brightness = bl_config->brightness_max_level;
+		props.brightness = bl_config->brightness_max_level;
+		bd = backlight_device_register("sde-backlight",
+				connector->kdev,
+				connector,
+				&sde_backlight_device_ops, &props);
+		if (IS_ERR(bd)) {
+			pr_err("Failed to register backlight: %ld\n",
+					    PTR_ERR(bd));
+			return -ENODEV;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_backlight.h b/drivers/gpu/drm/msm/sde/sde_backlight.h
new file mode 100644
index 0000000000000000000000000000000000000000..1ea130592302a8199ca133163eae8c386d9dde66
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_backlight.h
@@ -0,0 +1,18 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_BACKLIGHT_H_
+#define _SDE_BACKLIGHT_H_
+
+int sde_backlight_setup(struct drm_connector *connector);
+
+#endif /* _SDE_BACKLIGHT_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef74928179839359c02f38b35ac90019918933e6
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -0,0 +1,990 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt)	"%s: " fmt, __func__
+
+#include <drm/msm_drm_pp.h>
+#include "sde_color_processing.h"
+#include "sde_kms.h"
+#include "sde_crtc.h"
+#include "sde_hw_dspp.h"
+#include "sde_hw_lm.h"
+
+struct sde_cp_node {
+	u32 property_id;
+	u32 prop_flags;
+	u32 feature;
+	void *blob_ptr;
+	uint64_t prop_val;
+	const struct sde_pp_blk *pp_blk;
+	struct list_head feature_list;
+	struct list_head active_list;
+	struct list_head dirty_list;
+	bool is_dspp_feature;
+};
+
+struct sde_cp_prop_attach {
+	struct drm_crtc *crtc;
+	struct drm_property *prop;
+	struct sde_cp_node *prop_node;
+	u32 feature;
+	uint64_t val;
+};
+
+static void dspp_pcc_install_property(struct drm_crtc *crtc);
+
+static void dspp_hsic_install_property(struct drm_crtc *crtc);
+
+static void dspp_ad_install_property(struct drm_crtc *crtc);
+
+static void dspp_vlut_install_property(struct drm_crtc *crtc);
+
+typedef void (*dspp_prop_install_func_t)(struct drm_crtc *crtc);
+
+static dspp_prop_install_func_t dspp_prop_install_func[SDE_DSPP_MAX];
+
+#define setup_dspp_prop_install_funcs(func) \
+do { \
+	func[SDE_DSPP_PCC] = dspp_pcc_install_property; \
+	func[SDE_DSPP_HSIC] = dspp_hsic_install_property; \
+	func[SDE_DSPP_AD] = dspp_ad_install_property; \
+	func[SDE_DSPP_VLUT] = dspp_vlut_install_property; \
+} while (0)
+
+typedef void (*lm_prop_install_func_t)(struct drm_crtc *crtc);
+
+static lm_prop_install_func_t lm_prop_install_func[SDE_MIXER_MAX];
+
+static void lm_gc_install_property(struct drm_crtc *crtc);
+
+#define setup_lm_prop_install_funcs(func) \
+	(func[SDE_MIXER_GC] = lm_gc_install_property)
+
+enum {
+	/* Append new DSPP features before SDE_CP_CRTC_DSPP_MAX */
+	/* DSPP Features start */
+	SDE_CP_CRTC_DSPP_IGC,
+	SDE_CP_CRTC_DSPP_PCC,
+	SDE_CP_CRTC_DSPP_GC,
+	SDE_CP_CRTC_DSPP_HUE,
+	SDE_CP_CRTC_DSPP_SAT,
+	SDE_CP_CRTC_DSPP_VAL,
+	SDE_CP_CRTC_DSPP_CONT,
+	SDE_CP_CRTC_DSPP_MEMCOLOR,
+	SDE_CP_CRTC_DSPP_SIXZONE,
+	SDE_CP_CRTC_DSPP_GAMUT,
+	SDE_CP_CRTC_DSPP_DITHER,
+	SDE_CP_CRTC_DSPP_HIST,
+	SDE_CP_CRTC_DSPP_AD,
+	SDE_CP_CRTC_DSPP_VLUT,
+	SDE_CP_CRTC_DSPP_MAX,
+	/* DSPP features end */
+
+	/* Append new LM features before SDE_CP_CRTC_MAX_FEATURES */
+	/* LM feature start*/
+	SDE_CP_CRTC_LM_GC,
+	/* LM feature end*/
+
+	SDE_CP_CRTC_MAX_FEATURES,
+};
+
+#define INIT_PROP_ATTACH(p, crtc, prop, node, feature, val) \
+	do { \
+		(p)->crtc = crtc; \
+		(p)->prop = prop; \
+		(p)->prop_node = node; \
+		(p)->feature = feature; \
+		(p)->val = val; \
+	} while (0)
+
+static void sde_cp_get_hw_payload(struct sde_cp_node *prop_node,
+				  struct sde_hw_cp_cfg *hw_cfg,
+				  bool *feature_enabled)
+{
+
+	struct drm_property_blob *blob = NULL;
+
+	memset(hw_cfg, 0, sizeof(*hw_cfg));
+	*feature_enabled = false;
+
+	blob = prop_node->blob_ptr;
+	if (prop_node->prop_flags & DRM_MODE_PROP_BLOB) {
+		if (blob) {
+			hw_cfg->len = blob->length;
+			hw_cfg->payload = blob->data;
+			*feature_enabled = true;
+		}
+	} else if (prop_node->prop_flags & DRM_MODE_PROP_RANGE) {
+		/* Check if local blob is Set */
+		if (!blob) {
+			hw_cfg->len = sizeof(prop_node->prop_val);
+			if (prop_node->prop_val)
+				hw_cfg->payload = &prop_node->prop_val;
+		} else {
+			hw_cfg->len = (prop_node->prop_val) ? blob->length :
+					0;
+			hw_cfg->payload = (prop_node->prop_val) ? blob->data
+						: NULL;
+		}
+		if (prop_node->prop_val)
+			*feature_enabled = true;
+	} else {
+		DRM_ERROR("property type is not supported\n");
+	}
+}
+
+static int sde_cp_disable_crtc_blob_property(struct sde_cp_node *prop_node)
+{
+	struct drm_property_blob *blob = prop_node->blob_ptr;
+
+	if (!blob)
+		return -EINVAL;
+	drm_property_unreference_blob(blob);
+	prop_node->blob_ptr = NULL;
+	return 0;
+}
+
+static int sde_cp_create_local_blob(struct drm_crtc *crtc, u32 feature, int len)
+{
+	int ret = -EINVAL;
+	bool found = false;
+	struct sde_cp_node *prop_node = NULL;
+	struct drm_property_blob *blob_ptr;
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+
+	list_for_each_entry(prop_node, &sde_crtc->feature_list, feature_list) {
+		if (prop_node->feature == feature) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found || prop_node->prop_flags & DRM_MODE_PROP_BLOB) {
+		DRM_ERROR("local blob create failed prop found %d flags %d\n",
+		       found, prop_node->prop_flags);
+		return ret;
+	}
+
+	blob_ptr = drm_property_create_blob(crtc->dev, len, NULL);
+	ret = (IS_ERR_OR_NULL(blob_ptr)) ? PTR_ERR(blob_ptr) : 0;
+	if (!ret)
+		prop_node->blob_ptr = blob_ptr;
+
+	return ret;
+}
+
+static void sde_cp_destroy_local_blob(struct sde_cp_node *prop_node)
+{
+	if (!(prop_node->prop_flags & DRM_MODE_PROP_BLOB) &&
+		prop_node->blob_ptr)
+		drm_property_unreference_blob(prop_node->blob_ptr);
+}
+
+static int sde_cp_handle_range_property(struct sde_cp_node *prop_node,
+					uint64_t val)
+{
+	int ret = 0;
+	struct drm_property_blob *blob_ptr = prop_node->blob_ptr;
+
+	if (!blob_ptr) {
+		prop_node->prop_val = val;
+		return 0;
+	}
+
+	if (!val) {
+		prop_node->prop_val = 0;
+		return 0;
+	}
+
+	ret = copy_from_user(blob_ptr->data, (void *)val, blob_ptr->length);
+	if (ret) {
+		DRM_ERROR("failed to get the property info ret %d", ret);
+		ret = -EFAULT;
+	} else {
+		prop_node->prop_val = val;
+	}
+
+	return ret;
+}
+
+static int sde_cp_disable_crtc_property(struct drm_crtc *crtc,
+					 struct drm_property *property,
+					 struct sde_cp_node *prop_node)
+{
+	int ret = -EINVAL;
+
+	if (property->flags & DRM_MODE_PROP_BLOB)
+		ret = sde_cp_disable_crtc_blob_property(prop_node);
+	else if (property->flags & DRM_MODE_PROP_RANGE)
+		ret = sde_cp_handle_range_property(prop_node, 0);
+	return ret;
+}
+
+static int sde_cp_enable_crtc_blob_property(struct drm_crtc *crtc,
+					       struct sde_cp_node *prop_node,
+					       uint64_t val)
+{
+	struct drm_property_blob *blob = NULL;
+
+	/**
+	 * For non-blob based properties add support to create a blob
+	 * using the val and store the blob_ptr in prop_node.
+	 */
+	blob = drm_property_lookup_blob(crtc->dev, val);
+	if (!blob) {
+		DRM_ERROR("invalid blob id %lld\n", val);
+		return -EINVAL;
+	}
+	/* Release refernce to existing payload of the property */
+	if (prop_node->blob_ptr)
+		drm_property_unreference_blob(prop_node->blob_ptr);
+
+	prop_node->blob_ptr = blob;
+	return 0;
+}
+
+static int sde_cp_enable_crtc_property(struct drm_crtc *crtc,
+				       struct drm_property *property,
+				       struct sde_cp_node *prop_node,
+				       uint64_t val)
+{
+	int ret = -EINVAL;
+
+	if (property->flags & DRM_MODE_PROP_BLOB)
+		ret = sde_cp_enable_crtc_blob_property(crtc, prop_node, val);
+	else if (property->flags & DRM_MODE_PROP_RANGE)
+		ret = sde_cp_handle_range_property(prop_node, val);
+	return ret;
+}
+
+static struct sde_kms *get_kms(struct drm_crtc *crtc)
+{
+	struct msm_drm_private *priv = crtc->dev->dev_private;
+
+	return to_sde_kms(priv->kms);
+}
+
+static void sde_cp_crtc_prop_attach(struct sde_cp_prop_attach *prop_attach)
+{
+
+	struct sde_crtc *sde_crtc = to_sde_crtc(prop_attach->crtc);
+
+	drm_object_attach_property(&prop_attach->crtc->base,
+				   prop_attach->prop, prop_attach->val);
+
+	INIT_LIST_HEAD(&prop_attach->prop_node->active_list);
+	INIT_LIST_HEAD(&prop_attach->prop_node->dirty_list);
+
+	prop_attach->prop_node->property_id = prop_attach->prop->base.id;
+	prop_attach->prop_node->prop_flags = prop_attach->prop->flags;
+	prop_attach->prop_node->feature = prop_attach->feature;
+
+	if (prop_attach->feature < SDE_CP_CRTC_DSPP_MAX)
+		prop_attach->prop_node->is_dspp_feature = true;
+	else
+		prop_attach->prop_node->is_dspp_feature = false;
+
+	list_add(&prop_attach->prop_node->feature_list,
+		 &sde_crtc->feature_list);
+}
+
+void sde_cp_crtc_init(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = NULL;
+
+	if (!crtc) {
+		DRM_ERROR("invalid crtc %pK\n", crtc);
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+		return;
+	}
+
+	INIT_LIST_HEAD(&sde_crtc->active_list);
+	INIT_LIST_HEAD(&sde_crtc->dirty_list);
+	INIT_LIST_HEAD(&sde_crtc->feature_list);
+}
+
+static void sde_cp_crtc_install_immutable_property(struct drm_crtc *crtc,
+						   char *name,
+						   u32 feature)
+{
+	struct drm_property *prop;
+	struct sde_cp_node *prop_node = NULL;
+	struct msm_drm_private *priv;
+	struct sde_cp_prop_attach prop_attach;
+	uint64_t val = 0;
+
+	if (feature >=  SDE_CP_CRTC_MAX_FEATURES) {
+		DRM_ERROR("invalid feature %d max %d\n", feature,
+		       SDE_CP_CRTC_MAX_FEATURES);
+		return;
+	}
+
+	prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
+	if (!prop_node)
+		return;
+
+	priv = crtc->dev->dev_private;
+	prop = priv->cp_property[feature];
+
+	if (!prop) {
+		prop = drm_property_create(crtc->dev, DRM_MODE_PROP_IMMUTABLE,
+					   name, 0);
+		if (!prop) {
+			DRM_ERROR("property create failed: %s\n", name);
+			kfree(prop_node);
+			return;
+		}
+		priv->cp_property[feature] = prop;
+	}
+
+	INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
+				feature, val);
+	sde_cp_crtc_prop_attach(&prop_attach);
+}
+
+static void sde_cp_crtc_install_range_property(struct drm_crtc *crtc,
+					     char *name,
+					     u32 feature,
+					     uint64_t min, uint64_t max,
+					     uint64_t val)
+{
+	struct drm_property *prop;
+	struct sde_cp_node *prop_node = NULL;
+	struct msm_drm_private *priv;
+	struct sde_cp_prop_attach prop_attach;
+
+	if (feature >=  SDE_CP_CRTC_MAX_FEATURES) {
+		DRM_ERROR("invalid feature %d max %d\n", feature,
+			  SDE_CP_CRTC_MAX_FEATURES);
+		return;
+	}
+
+	prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
+	if (!prop_node)
+		return;
+
+	priv = crtc->dev->dev_private;
+	prop = priv->cp_property[feature];
+
+	if (!prop) {
+		prop = drm_property_create_range(crtc->dev, 0, name, min, max);
+		if (!prop) {
+			DRM_ERROR("property create failed: %s\n", name);
+			kfree(prop_node);
+			return;
+		}
+		priv->cp_property[feature] = prop;
+	}
+
+	INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
+				feature, val);
+
+	sde_cp_crtc_prop_attach(&prop_attach);
+}
+
+static void sde_cp_crtc_create_blob_property(struct drm_crtc *crtc, char *name,
+					     u32 feature)
+{
+	struct drm_property *prop;
+	struct sde_cp_node *prop_node = NULL;
+	struct msm_drm_private *priv;
+	uint64_t val = 0;
+	struct sde_cp_prop_attach prop_attach;
+
+	if (feature >=  SDE_CP_CRTC_MAX_FEATURES) {
+		DRM_ERROR("invalid feature %d max %d\n", feature,
+		       SDE_CP_CRTC_MAX_FEATURES);
+		return;
+	}
+
+	prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
+	if (!prop_node)
+		return;
+
+	priv = crtc->dev->dev_private;
+	prop = priv->cp_property[feature];
+
+	if (!prop) {
+		prop = drm_property_create(crtc->dev,
+					   DRM_MODE_PROP_BLOB, name, 0);
+		if (!prop) {
+			DRM_ERROR("property create failed: %s\n", name);
+			kfree(prop_node);
+			return;
+		}
+		priv->cp_property[feature] = prop;
+	}
+
+	INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
+				feature, val);
+
+	sde_cp_crtc_prop_attach(&prop_attach);
+}
+
+static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node,
+				   struct sde_crtc *sde_crtc)
+{
+	struct sde_hw_cp_cfg hw_cfg;
+	struct sde_hw_mixer *hw_lm;
+	struct sde_hw_dspp *hw_dspp;
+	u32 num_mixers = sde_crtc->num_mixers;
+	int i = 0;
+	bool feature_enabled = false;
+	int ret = 0;
+
+	sde_cp_get_hw_payload(prop_node, &hw_cfg, &feature_enabled);
+
+	for (i = 0; i < num_mixers && !ret; i++) {
+		hw_lm = sde_crtc->mixers[i].hw_lm;
+		hw_dspp = sde_crtc->mixers[i].hw_dspp;
+
+		switch (prop_node->feature) {
+		case SDE_CP_CRTC_DSPP_VLUT:
+			if (!hw_dspp || !hw_dspp->ops.setup_vlut) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_vlut(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_PCC:
+			if (!hw_dspp || !hw_dspp->ops.setup_pcc) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_pcc(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_IGC:
+			if (!hw_dspp || !hw_dspp->ops.setup_igc) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_igc(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_GC:
+			if (!hw_dspp || !hw_dspp->ops.setup_gc) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_gc(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_HUE:
+			if (!hw_dspp || !hw_dspp->ops.setup_hue) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_hue(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_SAT:
+			if (!hw_dspp || !hw_dspp->ops.setup_sat) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_sat(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_VAL:
+			if (!hw_dspp || !hw_dspp->ops.setup_val) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_val(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_CONT:
+			if (!hw_dspp || !hw_dspp->ops.setup_cont) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_cont(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_MEMCOLOR:
+			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor)
+				ret = -EINVAL;
+				continue;
+			hw_dspp->ops.setup_pa_memcolor(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_SIXZONE:
+			if (!hw_dspp || !hw_dspp->ops.setup_sixzone) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_sixzone(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_DSPP_GAMUT:
+			if (!hw_dspp || !hw_dspp->ops.setup_gamut) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_dspp->ops.setup_gamut(hw_dspp, &hw_cfg);
+			break;
+		case SDE_CP_CRTC_LM_GC:
+			if (!hw_lm || !hw_lm->ops.setup_gc) {
+				ret = -EINVAL;
+				continue;
+			}
+			hw_lm->ops.setup_gc(hw_lm, &hw_cfg);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+	}
+
+	if (ret) {
+		DRM_ERROR("failed to %s feature %d\n",
+			((feature_enabled) ? "enable" : "disable"),
+			prop_node->feature);
+		return;
+	}
+
+	if (feature_enabled) {
+		DRM_DEBUG_DRIVER("Add feature to active list %d\n",
+				 prop_node->property_id);
+		list_add_tail(&prop_node->active_list, &sde_crtc->active_list);
+	} else {
+		DRM_DEBUG_DRIVER("remove feature from active list %d\n",
+			 prop_node->property_id);
+		list_del_init(&prop_node->active_list);
+	}
+	/* Programming of feature done remove from dirty list */
+	list_del_init(&prop_node->dirty_list);
+}
+
+void sde_cp_crtc_apply_properties(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = NULL;
+	bool set_dspp_flush = false, set_lm_flush = false;
+	struct sde_cp_node *prop_node = NULL, *n = NULL;
+	struct sde_hw_ctl *ctl;
+	uint32_t flush_mask = 0;
+	u32 num_mixers = 0, i = 0;
+
+	if (!crtc || !crtc->dev) {
+		DRM_ERROR("invalid crtc %pK dev %pK\n", crtc,
+			  (crtc ? crtc->dev : NULL));
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+		return;
+	}
+
+	num_mixers = sde_crtc->num_mixers;
+	if (!num_mixers) {
+		DRM_DEBUG_DRIVER("no mixers for this crtc\n");
+		return;
+	}
+
+	/* Check if dirty list is empty for early return */
+	if (list_empty(&sde_crtc->dirty_list)) {
+		DRM_DEBUG_DRIVER("Dirty list is empty\n");
+		return;
+	}
+
+	list_for_each_entry_safe(prop_node, n, &sde_crtc->dirty_list,
+							dirty_list) {
+		sde_cp_crtc_setfeature(prop_node, sde_crtc);
+		/* Set the flush flag to true */
+		if (prop_node->is_dspp_feature)
+			set_dspp_flush = true;
+		else
+			set_lm_flush = true;
+	}
+
+	for (i = 0; i < num_mixers; i++) {
+		ctl = sde_crtc->mixers[i].hw_ctl;
+		if (!ctl)
+			continue;
+		if (set_dspp_flush && ctl->ops.get_bitmask_dspp
+				&& sde_crtc->mixers[i].hw_dspp)
+			ctl->ops.get_bitmask_dspp(ctl,
+					&flush_mask,
+					sde_crtc->mixers[i].hw_dspp->idx);
+			ctl->ops.update_pending_flush(ctl, flush_mask);
+		if (set_lm_flush && ctl->ops.get_bitmask_mixer
+				&& sde_crtc->mixers[i].hw_lm)
+			flush_mask = ctl->ops.get_bitmask_mixer(ctl,
+					sde_crtc->mixers[i].hw_lm->idx);
+			ctl->ops.update_pending_flush(ctl, flush_mask);
+	}
+}
+
+void sde_cp_crtc_install_properties(struct drm_crtc *crtc)
+{
+	struct sde_kms *kms = NULL;
+	struct sde_crtc *sde_crtc = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	unsigned long features = 0;
+	int i = 0;
+	struct msm_drm_private *priv;
+
+	if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
+		DRM_ERROR("invalid crtc %pK dev %pK\n",
+		       crtc, ((crtc) ? crtc->dev : NULL));
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("sde_crtc %pK\n", sde_crtc);
+		return;
+	}
+
+	kms = get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		DRM_ERROR("invalid sde kms %pK catalog %pK sde_crtc %pK\n",
+		 kms, ((kms) ? kms->catalog : NULL), sde_crtc);
+		return;
+	}
+
+	/**
+	 * Function can be called during the atomic_check with test_only flag
+	 * and actual commit. Allocate properties only if feature list is
+	 * empty during the atomic_check with test_only flag.
+	 */
+	if (!list_empty(&sde_crtc->feature_list))
+		return;
+
+	catalog = kms->catalog;
+	priv = crtc->dev->dev_private;
+	/**
+	 * DSPP/LM properties are global to all the CRTCS.
+	 * Properties are created for first CRTC and re-used for later
+	 * crtcs.
+	 */
+	if (!priv->cp_property) {
+		priv->cp_property = kzalloc((sizeof(priv->cp_property) *
+				SDE_CP_CRTC_MAX_FEATURES), GFP_KERNEL);
+		setup_dspp_prop_install_funcs(dspp_prop_install_func);
+		setup_lm_prop_install_funcs(lm_prop_install_func);
+	}
+	if (!priv->cp_property)
+		return;
+
+	if (!catalog->dspp_count)
+		goto lm_property;
+
+	/* Check for all the DSPP properties and attach it to CRTC */
+	features = catalog->dspp[0].features;
+	for (i = 0; i < SDE_DSPP_MAX; i++) {
+		if (!test_bit(i, &features))
+			continue;
+		if (dspp_prop_install_func[i])
+			dspp_prop_install_func[i](crtc);
+	}
+
+lm_property:
+	if (!catalog->mixer_count)
+		return;
+
+	/* Check for all the LM properties and attach it to CRTC */
+	features = catalog->mixer[0].features;
+	for (i = 0; i < SDE_MIXER_MAX; i++) {
+		if (!test_bit(i, &features))
+			continue;
+		if (lm_prop_install_func[i])
+			lm_prop_install_func[i](crtc);
+	}
+}
+
+int sde_cp_crtc_set_property(struct drm_crtc *crtc,
+				struct drm_property *property,
+				uint64_t val)
+{
+	struct sde_cp_node *prop_node = NULL;
+	struct sde_crtc *sde_crtc = NULL;
+	int ret = 0, i = 0, dspp_cnt, lm_cnt;
+	u8 found = 0;
+
+	if (!crtc || !property) {
+		DRM_ERROR("invalid crtc %pK property %pK\n", crtc, property);
+		return -EINVAL;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+		return -EINVAL;
+	}
+
+	list_for_each_entry(prop_node, &sde_crtc->feature_list, feature_list) {
+		if (property->base.id == prop_node->property_id) {
+			found = 1;
+			break;
+		}
+	}
+
+	if (!found)
+		return 0;
+	/**
+	 * sde_crtc is virtual ensure that hardware has been attached to the
+	 * crtc. Check LM and dspp counts based on whether feature is a
+	 * dspp/lm feature.
+	 */
+	if (!sde_crtc->num_mixers ||
+	    sde_crtc->num_mixers > ARRAY_SIZE(sde_crtc->mixers)) {
+		DRM_ERROR("Invalid mixer config act cnt %d max cnt %ld\n",
+			sde_crtc->num_mixers, ARRAY_SIZE(sde_crtc->mixers));
+		return -EINVAL;
+	}
+
+	dspp_cnt = 0;
+	lm_cnt = 0;
+	for (i = 0; i < sde_crtc->num_mixers; i++) {
+		if (sde_crtc->mixers[i].hw_dspp)
+			dspp_cnt++;
+		if (sde_crtc->mixers[i].hw_lm)
+			lm_cnt++;
+	}
+
+	if (prop_node->is_dspp_feature && dspp_cnt < sde_crtc->num_mixers) {
+		DRM_ERROR("invalid dspp cnt %d mixer cnt %d\n", dspp_cnt,
+			sde_crtc->num_mixers);
+		return -EINVAL;
+	} else if (lm_cnt < sde_crtc->num_mixers) {
+		DRM_ERROR("invalid lm cnt %d mixer cnt %d\n", lm_cnt,
+			sde_crtc->num_mixers);
+		return -EINVAL;
+	}
+	/* remove the property from dirty list */
+	list_del_init(&prop_node->dirty_list);
+
+	if (!val)
+		ret = sde_cp_disable_crtc_property(crtc, property, prop_node);
+	else
+		ret = sde_cp_enable_crtc_property(crtc, property,
+						  prop_node, val);
+
+	if (!ret) {
+		/* remove the property from active list */
+		list_del_init(&prop_node->active_list);
+		/* Mark the feature as dirty */
+		list_add_tail(&prop_node->dirty_list, &sde_crtc->dirty_list);
+	}
+	return ret;
+}
+
+int sde_cp_crtc_get_property(struct drm_crtc *crtc,
+			     struct drm_property *property, uint64_t *val)
+{
+	struct sde_cp_node *prop_node = NULL;
+	struct sde_crtc *sde_crtc = NULL;
+
+	if (!crtc || !property || !val) {
+		DRM_ERROR("invalid crtc %pK property %pK val %pK\n",
+			  crtc, property, val);
+		return -EINVAL;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+		return -EINVAL;
+	}
+	/* Return 0 if property is not supported */
+	*val = 0;
+	list_for_each_entry(prop_node, &sde_crtc->feature_list, feature_list) {
+		if (property->base.id == prop_node->property_id) {
+			*val = prop_node->prop_val;
+			break;
+		}
+	}
+	return 0;
+}
+
+void sde_cp_crtc_destroy_properties(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = NULL;
+	struct sde_cp_node *prop_node = NULL, *n = NULL;
+
+	if (!crtc) {
+		DRM_ERROR("invalid crtc %pK\n", crtc);
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+		return;
+	}
+
+	list_for_each_entry_safe(prop_node, n, &sde_crtc->feature_list,
+				 feature_list) {
+		if (prop_node->prop_flags & DRM_MODE_PROP_BLOB
+		    && prop_node->blob_ptr)
+			drm_property_unreference_blob(prop_node->blob_ptr);
+
+		list_del_init(&prop_node->active_list);
+		list_del_init(&prop_node->dirty_list);
+		list_del_init(&prop_node->feature_list);
+		sde_cp_destroy_local_blob(prop_node);
+		kfree(prop_node);
+	}
+
+	INIT_LIST_HEAD(&sde_crtc->active_list);
+	INIT_LIST_HEAD(&sde_crtc->dirty_list);
+	INIT_LIST_HEAD(&sde_crtc->feature_list);
+}
+
+void sde_cp_crtc_suspend(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = NULL;
+	struct sde_cp_node *prop_node = NULL, *n = NULL;
+
+	if (!crtc) {
+		DRM_ERROR("crtc %pK\n", crtc);
+		return;
+	}
+	sde_crtc = to_sde_crtc(crtc);
+	if (!sde_crtc) {
+		DRM_ERROR("sde_crtc %pK\n", sde_crtc);
+		return;
+	}
+
+	list_for_each_entry_safe(prop_node, n, &sde_crtc->active_list,
+				 active_list) {
+		list_add_tail(&prop_node->dirty_list, &sde_crtc->dirty_list);
+		list_del_init(&prop_node->active_list);
+	}
+}
+
+void sde_cp_crtc_resume(struct drm_crtc *crtc)
+{
+	/* placeholder for operations needed during resume */
+}
+
+static void dspp_pcc_install_property(struct drm_crtc *crtc)
+{
+	char feature_name[256];
+	struct sde_kms *kms = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	u32 version;
+
+	kms = get_kms(crtc);
+	catalog = kms->catalog;
+
+	version = catalog->dspp[0].sblk->pcc.version >> 16;
+	snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+		"SDE_DSPP_PCC_V", version);
+	switch (version) {
+	case 1:
+		sde_cp_crtc_create_blob_property(crtc, feature_name,
+					SDE_CP_CRTC_DSPP_PCC);
+		break;
+	default:
+		DRM_ERROR("version %d not supported\n", version);
+		break;
+	}
+}
+
+static void dspp_hsic_install_property(struct drm_crtc *crtc)
+{
+	char feature_name[256];
+	struct sde_kms *kms = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	u32 version;
+
+	kms = get_kms(crtc);
+	catalog = kms->catalog;
+	version = catalog->dspp[0].sblk->hsic.version >> 16;
+	switch (version) {
+	case 1:
+		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+			"SDE_DSPP_HUE_V", version);
+		sde_cp_crtc_install_range_property(crtc, feature_name,
+			SDE_CP_CRTC_DSPP_HUE, 0, U32_MAX, 0);
+		break;
+	default:
+		DRM_ERROR("version %d not supported\n", version);
+		break;
+	}
+}
+
+static void dspp_vlut_install_property(struct drm_crtc *crtc)
+{
+	char feature_name[256];
+	struct sde_kms *kms = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	u32 version;
+
+	kms = get_kms(crtc);
+	catalog = kms->catalog;
+	version = catalog->dspp[0].sblk->vlut.version >> 16;
+	snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+		"SDE_DSPP_VLUT_V", version);
+	switch (version) {
+	case 1:
+		sde_cp_crtc_install_range_property(crtc, feature_name,
+			SDE_CP_CRTC_DSPP_VLUT, 0, U64_MAX, 0);
+		sde_cp_create_local_blob(crtc,
+			SDE_CP_CRTC_DSPP_VLUT,
+			sizeof(struct drm_msm_pa_vlut));
+		break;
+	default:
+		DRM_ERROR("version %d not supported\n", version);
+		break;
+	}
+}
+
+static void dspp_ad_install_property(struct drm_crtc *crtc)
+{
+	char feature_name[256];
+	struct sde_kms *kms = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	u32 version;
+
+	kms = get_kms(crtc);
+	catalog = kms->catalog;
+	version = catalog->dspp[0].sblk->ad.version >> 16;
+	snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+		"SDE_DSPP_AD_V", version);
+	switch (version) {
+	case 3:
+		sde_cp_crtc_install_immutable_property(crtc,
+			feature_name, SDE_CP_CRTC_DSPP_AD);
+		break;
+	default:
+		DRM_ERROR("version %d not supported\n", version);
+		break;
+	}
+}
+
+static void lm_gc_install_property(struct drm_crtc *crtc)
+{
+	char feature_name[256];
+	struct sde_kms *kms = NULL;
+	struct sde_mdss_cfg *catalog = NULL;
+	u32 version;
+
+	kms = get_kms(crtc);
+	catalog = kms->catalog;
+	version = catalog->mixer[0].sblk->gc.version >> 16;
+	snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+		 "SDE_LM_GC_V", version);
+	switch (version) {
+	case 1:
+		sde_cp_crtc_create_blob_property(crtc, feature_name,
+			SDE_CP_CRTC_LM_GC);
+		break;
+	default:
+		DRM_ERROR("version %d not supported\n", version);
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h
new file mode 100644
index 0000000000000000000000000000000000000000..bf954ec6a8e7b8e319403ebed92170fe8309683f
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SDE_COLOR_PROCESSING_H
+#define _SDE_COLOR_PROCESSING_H
+#include <drm/drm_crtc.h>
+
+/*
+ * PA MEMORY COLOR types
+ * @MEMCOLOR_SKIN          Skin memory color type
+ * @MEMCOLOR_SKY           Sky memory color type
+ * @MEMCOLOR_FOLIAGE       Foliage memory color type
+ */
+enum sde_memcolor_type {
+	MEMCOLOR_SKIN = 0,
+	MEMCOLOR_SKY,
+	MEMCOLOR_FOLIAGE
+};
+
+/**
+ * sde_cp_crtc_init(): Initialize color processing lists for a crtc.
+ *                     Should be called during crtc initialization.
+ * @crtc:  Pointer to sde_crtc.
+ */
+void sde_cp_crtc_init(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_install_properties(): Installs the color processing
+ *                                properties for a crtc.
+ *                                Should be called during crtc initialization.
+ * @crtc:  Pointer to crtc.
+ */
+void sde_cp_crtc_install_properties(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_destroy_properties: Destroys color processing
+ *                                            properties for a crtc.
+ * should be called during crtc de-initialization.
+ * @crtc:  Pointer to crtc.
+ */
+void sde_cp_crtc_destroy_properties(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_set_property: Set a color processing property
+ *                                      for a crtc.
+ *                                      Should be during atomic set property.
+ * @crtc: Pointer to crtc.
+ * @property: Property that needs to enabled/disabled.
+ * @val: Value of property.
+ */
+int sde_cp_crtc_set_property(struct drm_crtc *crtc,
+				struct drm_property *property, uint64_t val);
+
+/**
+ * sde_cp_crtc_apply_properties: Enable/disable properties
+ *                               for a crtc.
+ *                               Should be called during atomic commit call.
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_apply_properties(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_get_property: Get value of color processing property
+ *                                      for a crtc.
+ *                                      Should be during atomic get property.
+ * @crtc: Pointer to crtc.
+ * @property: Property that needs to enabled/disabled.
+ * @val: Value of property.
+ *
+ */
+int sde_cp_crtc_get_property(struct drm_crtc *crtc,
+				struct drm_property *property, uint64_t *val);
+
+/**
+ * sde_cp_crtc_suspend: Suspend the crtc features
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_suspend(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_resume: Resume the crtc features
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_resume(struct drm_crtc *crtc);
+#endif /*_SDE_COLOR_PROCESSING_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c
new file mode 100644
index 0000000000000000000000000000000000000000..ac9997c238cda441b6fa292d7807009543b6ba45
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_connector.c
@@ -0,0 +1,624 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"sde-drm:[%s] " fmt, __func__
+#include "msm_drv.h"
+
+#include "sde_kms.h"
+#include "sde_connector.h"
+#include "sde_backlight.h"
+
+static const struct drm_prop_enum_list e_topology_name[] = {
+	{SDE_RM_TOPOLOGY_UNKNOWN,	"sde_unknown"},
+	{SDE_RM_TOPOLOGY_SINGLEPIPE,	"sde_singlepipe"},
+	{SDE_RM_TOPOLOGY_DUALPIPE,	"sde_dualpipe"},
+	{SDE_RM_TOPOLOGY_PPSPLIT,	"sde_ppsplit"},
+	{SDE_RM_TOPOLOGY_DUALPIPEMERGE,	"sde_dualpipemerge"}
+};
+static const struct drm_prop_enum_list e_topology_control[] = {
+	{SDE_RM_TOPCTL_RESERVE_LOCK,	"reserve_lock"},
+	{SDE_RM_TOPCTL_RESERVE_CLEAR,	"reserve_clear"},
+	{SDE_RM_TOPCTL_DSPP,		"dspp"},
+	{SDE_RM_TOPCTL_FORCE_TILING,	"force_tiling"},
+	{SDE_RM_TOPCTL_PPSPLIT,		"ppsplit"}
+};
+
+int sde_connector_get_info(struct drm_connector *connector,
+		struct msm_display_info *info)
+{
+	struct sde_connector *c_conn;
+
+	if (!connector || !info) {
+		SDE_ERROR("invalid argument(s), conn %pK, info %pK\n",
+				connector, info);
+		return -EINVAL;
+	}
+
+	c_conn = to_sde_connector(connector);
+
+	if (!c_conn->display || !c_conn->ops.get_info) {
+		SDE_ERROR("display info not supported for %pK\n",
+				c_conn->display);
+		return -EINVAL;
+	}
+
+	return c_conn->ops.get_info(info, c_conn->display);
+}
+
+static void sde_connector_destroy(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return;
+	}
+
+	c_conn = to_sde_connector(connector);
+
+	if (c_conn->blob_caps)
+		drm_property_unreference_blob(c_conn->blob_caps);
+	msm_property_destroy(&c_conn->property_info);
+
+	drm_connector_unregister(connector);
+	sde_fence_deinit(&c_conn->retire_fence);
+	drm_connector_cleanup(connector);
+	kfree(c_conn);
+}
+
+/**
+ * _sde_connector_destroy_fb - clean up connector state's out_fb buffer
+ * @c_conn: Pointer to sde connector structure
+ * @c_state: Pointer to sde connector state structure
+ */
+static void _sde_connector_destroy_fb(struct sde_connector *c_conn,
+		struct sde_connector_state *c_state)
+{
+	if (!c_state || !c_state->out_fb) {
+		SDE_ERROR("invalid state %pK\n", c_state);
+		return;
+	}
+
+	msm_framebuffer_cleanup(c_state->out_fb,
+			c_state->mmu_id);
+	drm_framebuffer_unreference(c_state->out_fb);
+	c_state->out_fb = NULL;
+
+	if (c_conn) {
+		c_state->property_values[CONNECTOR_PROP_OUT_FB] =
+			msm_property_get_default(&c_conn->property_info,
+					CONNECTOR_PROP_OUT_FB);
+	} else {
+		c_state->property_values[CONNECTOR_PROP_OUT_FB] = ~0;
+	}
+}
+
+static void sde_connector_atomic_destroy_state(struct drm_connector *connector,
+		struct drm_connector_state *state)
+{
+	struct sde_connector *c_conn = NULL;
+	struct sde_connector_state *c_state = NULL;
+
+	if (!state) {
+		SDE_ERROR("invalid state\n");
+		return;
+	}
+
+	/*
+	 * The base DRM framework currently always passes in a NULL
+	 * connector pointer. This is not correct, but attempt to
+	 * handle that case as much as possible.
+	 */
+	if (connector)
+		c_conn = to_sde_connector(connector);
+	c_state = to_sde_connector_state(state);
+
+	if (c_state->out_fb)
+		_sde_connector_destroy_fb(c_conn, c_state);
+
+	if (!c_conn) {
+		kfree(c_state);
+	} else {
+		/* destroy value helper */
+		msm_property_destroy_state(&c_conn->property_info, c_state,
+				c_state->property_values, 0);
+	}
+}
+
+static void sde_connector_atomic_reset(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+	struct sde_connector_state *c_state;
+
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return;
+	}
+
+	c_conn = to_sde_connector(connector);
+
+	if (connector->state) {
+		sde_connector_atomic_destroy_state(connector, connector->state);
+		connector->state = 0;
+	}
+
+	c_state = msm_property_alloc_state(&c_conn->property_info);
+	if (!c_state) {
+		SDE_ERROR("state alloc failed\n");
+		return;
+	}
+
+	/* reset value helper, zero out state structure and reset properties */
+	msm_property_reset_state(&c_conn->property_info, c_state,
+			c_state->property_values, 0);
+
+	c_state->base.connector = connector;
+	connector->state = &c_state->base;
+}
+
+static struct drm_connector_state *
+sde_connector_atomic_duplicate_state(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+	struct sde_connector_state *c_state, *c_oldstate;
+	int rc;
+
+	if (!connector || !connector->state) {
+		SDE_ERROR("invalid connector %pK\n", connector);
+		return NULL;
+	}
+
+	c_conn = to_sde_connector(connector);
+	c_oldstate = to_sde_connector_state(connector->state);
+	c_state = msm_property_alloc_state(&c_conn->property_info);
+	if (!c_state) {
+		SDE_ERROR("state alloc failed\n");
+		return NULL;
+	}
+
+	/* duplicate value helper */
+	msm_property_duplicate_state(&c_conn->property_info,
+			c_oldstate, c_state, c_state->property_values, 0);
+
+	/* additional handling for drm framebuffer objects */
+	if (c_state->out_fb) {
+		drm_framebuffer_reference(c_state->out_fb);
+		rc = msm_framebuffer_prepare(c_state->out_fb,
+				c_state->mmu_id);
+		if (rc)
+			SDE_ERROR("failed to prepare fb, %d\n", rc);
+	}
+
+	return &c_state->base;
+}
+
+static int sde_connector_atomic_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		struct drm_property *property,
+		uint64_t val)
+{
+	struct sde_connector *c_conn;
+	struct sde_connector_state *c_state;
+	int idx, rc;
+
+	if (!connector || !state || !property) {
+		SDE_ERROR("invalid argument(s), conn %pK, state %pK, prp %pK\n",
+				connector, state, property);
+		return -EINVAL;
+	}
+
+	c_conn = to_sde_connector(connector);
+	c_state = to_sde_connector_state(state);
+
+	/* generic property handling */
+	rc = msm_property_atomic_set(&c_conn->property_info,
+			c_state->property_values, 0, property, val);
+	if (rc)
+		goto end;
+
+	/* connector-specific property handling */
+	idx = msm_property_index(&c_conn->property_info, property);
+
+	if (idx == CONNECTOR_PROP_OUT_FB) {
+		/* clear old fb, if present */
+		if (c_state->out_fb)
+			_sde_connector_destroy_fb(c_conn, c_state);
+
+		/* convert fb val to drm framebuffer and prepare it */
+		c_state->out_fb =
+			drm_framebuffer_lookup(connector->dev, val);
+		if (!c_state->out_fb) {
+			SDE_ERROR("failed to look up fb %lld\n", val);
+			rc = -EFAULT;
+		} else {
+			if (c_state->out_fb->flags & DRM_MODE_FB_SECURE)
+				c_state->mmu_id =
+				c_conn->mmu_id[SDE_IOMMU_DOMAIN_SECURE];
+			else
+				c_state->mmu_id =
+				c_conn->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE];
+
+			rc = msm_framebuffer_prepare(c_state->out_fb,
+					c_state->mmu_id);
+			if (rc)
+				SDE_ERROR("prep fb failed, %d\n", rc);
+		}
+	}
+
+	if (idx == CONNECTOR_PROP_TOPOLOGY_CONTROL) {
+		rc = sde_rm_check_property_topctl(val);
+		if (rc)
+			SDE_ERROR("invalid topology_control: 0x%llX\n", val);
+	}
+
+	/* check for custom property handling */
+	if (!rc && c_conn->ops.set_property) {
+		rc = c_conn->ops.set_property(connector,
+				state,
+				idx,
+				val,
+				c_conn->display);
+
+		/* potentially clean up out_fb if rc != 0 */
+		if ((idx == CONNECTOR_PROP_OUT_FB) && rc)
+			_sde_connector_destroy_fb(c_conn, c_state);
+	}
+end:
+	return rc;
+}
+
+static int sde_connector_set_property(struct drm_connector *connector,
+		struct drm_property *property,
+		uint64_t val)
+{
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return -EINVAL;
+	}
+
+	return sde_connector_atomic_set_property(connector,
+			connector->state, property, val);
+}
+
+static int sde_connector_atomic_get_property(struct drm_connector *connector,
+		const struct drm_connector_state *state,
+		struct drm_property *property,
+		uint64_t *val)
+{
+	struct sde_connector *c_conn;
+	struct sde_connector_state *c_state;
+	int idx, rc = -EINVAL;
+
+	if (!connector || !state) {
+		SDE_ERROR("invalid argument(s), conn %pK, state %pK\n",
+				connector, state);
+		return -EINVAL;
+	}
+
+	c_conn = to_sde_connector(connector);
+	c_state = to_sde_connector_state(state);
+
+	idx = msm_property_index(&c_conn->property_info, property);
+	if (idx == CONNECTOR_PROP_RETIRE_FENCE)
+		/*
+		 * Set a fence offset if not a virtual connector, so that the
+		 * fence signals after one additional commit rather than at the
+		 * end of the current one.
+		 */
+		rc = sde_fence_create(&c_conn->retire_fence, val,
+			c_conn->connector_type != DRM_MODE_CONNECTOR_VIRTUAL);
+	else
+		/* get cached property value */
+		rc = msm_property_atomic_get(&c_conn->property_info,
+				c_state->property_values, 0, property, val);
+
+	/* allow for custom override */
+	if (c_conn->ops.get_property)
+		rc = c_conn->ops.get_property(connector,
+				(struct drm_connector_state *)state,
+				idx,
+				val,
+				c_conn->display);
+	return rc;
+}
+
+void sde_connector_prepare_fence(struct drm_connector *connector)
+{
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return;
+	}
+
+	sde_fence_prepare(&to_sde_connector(connector)->retire_fence);
+}
+
+void sde_connector_complete_commit(struct drm_connector *connector)
+{
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return;
+	}
+
+	/* signal connector's retire fence */
+	sde_fence_signal(&to_sde_connector(connector)->retire_fence, 0);
+}
+
+static enum drm_connector_status
+sde_connector_detect(struct drm_connector *connector, bool force)
+{
+	enum drm_connector_status status = connector_status_unknown;
+	struct sde_connector *c_conn;
+
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return status;
+	}
+
+	c_conn = to_sde_connector(connector);
+
+	if (c_conn->ops.detect)
+		status = c_conn->ops.detect(connector,
+				force,
+				c_conn->display);
+
+	return status;
+}
+
+static const struct drm_connector_funcs sde_connector_ops = {
+	.dpms =                   drm_atomic_helper_connector_dpms,
+	.reset =                  sde_connector_atomic_reset,
+	.detect =                 sde_connector_detect,
+	.destroy =                sde_connector_destroy,
+	.fill_modes =             drm_helper_probe_single_connector_modes,
+	.atomic_duplicate_state = sde_connector_atomic_duplicate_state,
+	.atomic_destroy_state =   sde_connector_atomic_destroy_state,
+	.atomic_set_property =    sde_connector_atomic_set_property,
+	.atomic_get_property =    sde_connector_atomic_get_property,
+	.set_property =           sde_connector_set_property,
+};
+
+static int sde_connector_get_modes(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return 0;
+	}
+
+	c_conn = to_sde_connector(connector);
+	if (!c_conn->ops.get_modes) {
+		SDE_DEBUG("missing get_modes callback\n");
+		return 0;
+	}
+
+	return c_conn->ops.get_modes(connector, c_conn->display);
+}
+
+static enum drm_mode_status
+sde_connector_mode_valid(struct drm_connector *connector,
+		struct drm_display_mode *mode)
+{
+	struct sde_connector *c_conn;
+
+	if (!connector || !mode) {
+		SDE_ERROR("invalid argument(s), conn %pK, mode %pK\n",
+				connector, mode);
+		return MODE_ERROR;
+	}
+
+	c_conn = to_sde_connector(connector);
+
+	if (c_conn->ops.mode_valid)
+		return c_conn->ops.mode_valid(connector, mode, c_conn->display);
+
+	/* assume all modes okay by default */
+	return MODE_OK;
+}
+
+static struct drm_encoder *
+sde_connector_best_encoder(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn = to_sde_connector(connector);
+
+	if (!connector) {
+		SDE_ERROR("invalid connector\n");
+		return NULL;
+	}
+
+	/*
+	 * This is true for now, revisit this code when multiple encoders are
+	 * supported.
+	 */
+	return c_conn->encoder;
+}
+
+static const struct drm_connector_helper_funcs sde_connector_helper_ops = {
+	.get_modes =    sde_connector_get_modes,
+	.mode_valid =   sde_connector_mode_valid,
+	.best_encoder = sde_connector_best_encoder,
+};
+
+struct drm_connector *sde_connector_init(struct drm_device *dev,
+		struct drm_encoder *encoder,
+		struct drm_panel *panel,
+		void *display,
+		const struct sde_connector_ops *ops,
+		int connector_poll,
+		int connector_type)
+{
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+	struct sde_kms_info *info;
+	struct sde_connector *c_conn = NULL;
+	int rc;
+
+	if (!dev || !dev->dev_private || !encoder) {
+		SDE_ERROR("invalid argument(s), dev %pK, enc %pK\n",
+				dev, encoder);
+		return ERR_PTR(-EINVAL);
+	}
+
+	priv = dev->dev_private;
+	if (!priv->kms) {
+		SDE_ERROR("invalid kms reference\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	c_conn = kzalloc(sizeof(*c_conn), GFP_KERNEL);
+	if (!c_conn) {
+		SDE_ERROR("failed to alloc sde connector\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	rc = drm_connector_init(dev,
+			&c_conn->base,
+			&sde_connector_ops,
+			connector_type);
+	if (rc)
+		goto error_free_conn;
+
+	c_conn->connector_type = connector_type;
+	c_conn->encoder = encoder;
+	c_conn->panel = panel;
+	c_conn->display = display;
+
+	/* cache mmu_id's for later */
+	sde_kms = to_sde_kms(priv->kms);
+	if (sde_kms->vbif[VBIF_NRT]) {
+		c_conn->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE];
+		c_conn->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE];
+	} else {
+		c_conn->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
+		c_conn->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE];
+	}
+
+	if (ops)
+		c_conn->ops = *ops;
+
+	c_conn->base.helper_private = &sde_connector_helper_ops;
+	c_conn->base.polled = connector_poll;
+	c_conn->base.interlace_allowed = 0;
+	c_conn->base.doublescan_allowed = 0;
+
+	snprintf(c_conn->name,
+			SDE_CONNECTOR_NAME_SIZE,
+			"conn%u",
+			c_conn->base.base.id);
+
+	rc = sde_fence_init(&c_conn->retire_fence, c_conn->name,
+			c_conn->base.base.id);
+	if (rc) {
+		SDE_ERROR("failed to init fence, %d\n", rc);
+		goto error_cleanup_conn;
+	}
+
+	rc = drm_connector_register(&c_conn->base);
+	if (rc) {
+		SDE_ERROR("failed to register drm connector, %d\n", rc);
+		goto error_cleanup_fence;
+	}
+
+	rc = drm_mode_connector_attach_encoder(&c_conn->base, encoder);
+	if (rc) {
+		SDE_ERROR("failed to attach encoder to connector, %d\n", rc);
+		goto error_unregister_conn;
+	}
+
+	if (c_conn->ops.set_backlight) {
+		rc = sde_backlight_setup(&c_conn->base);
+		if (rc) {
+			pr_err("failed to setup backlight, rc=%d\n", rc);
+			goto error_unregister_conn;
+		}
+	}
+
+	/* create properties */
+	msm_property_init(&c_conn->property_info, &c_conn->base.base, dev,
+			priv->conn_property, c_conn->property_data,
+			CONNECTOR_PROP_COUNT, CONNECTOR_PROP_BLOBCOUNT,
+			sizeof(struct sde_connector_state));
+
+	if (c_conn->ops.post_init) {
+		info = kmalloc(sizeof(*info), GFP_KERNEL);
+		if (!info) {
+			SDE_ERROR("failed to allocate info buffer\n");
+			rc = -ENOMEM;
+			goto error_unregister_conn;
+		}
+
+		sde_kms_info_reset(info);
+		rc = c_conn->ops.post_init(&c_conn->base, info, display);
+		if (rc) {
+			SDE_ERROR("post-init failed, %d\n", rc);
+			kfree(info);
+			goto error_unregister_conn;
+		}
+
+		msm_property_install_blob(&c_conn->property_info,
+				"capabilities",
+				DRM_MODE_PROP_IMMUTABLE,
+				CONNECTOR_PROP_SDE_INFO);
+
+		msm_property_set_blob(&c_conn->property_info,
+				&c_conn->blob_caps,
+				SDE_KMS_INFO_DATA(info),
+				SDE_KMS_INFO_DATALEN(info),
+				CONNECTOR_PROP_SDE_INFO);
+		kfree(info);
+	}
+
+	msm_property_install_range(&c_conn->property_info, "RETIRE_FENCE",
+			0x0, 0, INR_OPEN_MAX, 0, CONNECTOR_PROP_RETIRE_FENCE);
+
+	/* enum/bitmask properties */
+	msm_property_install_enum(&c_conn->property_info, "topology_name",
+			DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
+			ARRAY_SIZE(e_topology_name),
+			CONNECTOR_PROP_TOPOLOGY_NAME);
+	msm_property_install_enum(&c_conn->property_info, "topology_control",
+			0, 1, e_topology_control,
+			ARRAY_SIZE(e_topology_control),
+			CONNECTOR_PROP_TOPOLOGY_CONTROL);
+
+	rc = msm_property_install_get_status(&c_conn->property_info);
+	if (rc) {
+		SDE_ERROR("failed to create one or more properties\n");
+		goto error_destroy_property;
+	}
+
+	SDE_DEBUG("connector %d attach encoder %d\n",
+			c_conn->base.base.id, encoder->base.id);
+
+	priv->connectors[priv->num_connectors++] = &c_conn->base;
+
+	return &c_conn->base;
+
+error_destroy_property:
+	if (c_conn->blob_caps)
+		drm_property_unreference_blob(c_conn->blob_caps);
+	msm_property_destroy(&c_conn->property_info);
+error_unregister_conn:
+	drm_connector_unregister(&c_conn->base);
+error_cleanup_fence:
+	sde_fence_deinit(&c_conn->retire_fence);
+error_cleanup_conn:
+	drm_connector_cleanup(&c_conn->base);
+error_free_conn:
+	kfree(c_conn);
+
+	return ERR_PTR(rc);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h
new file mode 100644
index 0000000000000000000000000000000000000000..9580282291db129b8f9bb0108b3b577594da3c0a
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_connector.h
@@ -0,0 +1,298 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_CONNECTOR_H_
+#define _SDE_CONNECTOR_H_
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_panel.h>
+
+#include "msm_drv.h"
+#include "msm_prop.h"
+#include "sde_kms.h"
+#include "sde_fence.h"
+
+#define SDE_CONNECTOR_NAME_SIZE	16
+
+struct sde_connector;
+struct sde_connector_state;
+
+/**
+ * struct sde_connector_ops - callback functions for generic sde connector
+ * Individual callbacks documented below.
+ */
+struct sde_connector_ops {
+	/**
+	 * post_init - perform additional initialization steps
+	 * @connector: Pointer to drm connector structure
+	 * @info: Pointer to sde connector info structure
+	 * @display: Pointer to private display handle
+	 * Returns: Zero on success
+	 */
+	int (*post_init)(struct drm_connector *connector,
+			void *info,
+			void *display);
+
+	/**
+	 * detect - determine if connector is connected
+	 * @connector: Pointer to drm connector structure
+	 * @force: Force detect setting from drm framework
+	 * @display: Pointer to private display handle
+	 * Returns: Connector 'is connected' status
+	 */
+	enum drm_connector_status (*detect)(struct drm_connector *connector,
+			bool force,
+			void *display);
+
+	/**
+	 * get_modes - add drm modes via drm_mode_probed_add()
+	 * @connector: Pointer to drm connector structure
+	 * @display: Pointer to private display handle
+	 * Returns: Number of modes added
+	 */
+	int (*get_modes)(struct drm_connector *connector,
+			void *display);
+
+	/**
+	 * mode_valid - determine if specified mode is valid
+	 * @connector: Pointer to drm connector structure
+	 * @mode: Pointer to drm mode structure
+	 * @display: Pointer to private display handle
+	 * Returns: Validity status for specified mode
+	 */
+	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
+			struct drm_display_mode *mode,
+			void *display);
+
+	/**
+	 * set_property - set property value
+	 * @connector: Pointer to drm connector structure
+	 * @state: Pointer to drm connector state structure
+	 * @property_index: DRM property index
+	 * @value: Incoming property value
+	 * @display: Pointer to private display structure
+	 * Returns: Zero on success
+	 */
+	int (*set_property)(struct drm_connector *connector,
+			struct drm_connector_state *state,
+			int property_index,
+			uint64_t value,
+			void *display);
+
+	/**
+	 * get_property - get property value
+	 * @connector: Pointer to drm connector structure
+	 * @state: Pointer to drm connector state structure
+	 * @property_index: DRM property index
+	 * @value: Pointer to variable for accepting property value
+	 * @display: Pointer to private display structure
+	 * Returns: Zero on success
+	 */
+	int (*get_property)(struct drm_connector *connector,
+			struct drm_connector_state *state,
+			int property_index,
+			uint64_t *value,
+			void *display);
+
+	/**
+	 * get_info - get display information
+	 * @info: Pointer to msm display info structure
+	 * @display: Pointer to private display structure
+	 * Returns: Zero on success
+	 */
+	int (*get_info)(struct msm_display_info *info, void *display);
+
+	int (*set_backlight)(void *display, u32 bl_lvl);
+};
+
+/**
+ * struct sde_connector - local sde connector structure
+ * @base: Base drm connector structure
+ * @connector_type: Set to one of DRM_MODE_CONNECTOR_ types
+ * @encoder: Pointer to preferred drm encoder
+ * @panel: Pointer to drm panel, if present
+ * @display: Pointer to private display data structure
+ * @mmu_secure: MMU id for secure buffers
+ * @mmu_unsecure: MMU id for unsecure buffers
+ * @name: ASCII name of connector
+ * @retire_fence: Retire fence reference
+ * @ops: Local callback function pointer table
+ * @property_info: Private structure for generic property handling
+ * @property_data: Array of private data for generic property handling
+ * @blob_caps: Pointer to blob structure for 'capabilities' property
+ */
+struct sde_connector {
+	struct drm_connector base;
+
+	int connector_type;
+
+	struct drm_encoder *encoder;
+	struct drm_panel *panel;
+	void *display;
+
+	int mmu_id[SDE_IOMMU_DOMAIN_MAX];
+
+	char name[SDE_CONNECTOR_NAME_SIZE];
+
+	struct sde_fence retire_fence;
+	struct sde_connector_ops ops;
+
+	struct msm_property_info property_info;
+	struct msm_property_data property_data[CONNECTOR_PROP_COUNT];
+	struct drm_property_blob *blob_caps;
+};
+
+/**
+ * to_sde_connector - convert drm_connector pointer to sde connector pointer
+ * @X: Pointer to drm_connector structure
+ * Returns: Pointer to sde_connector structure
+ */
+#define to_sde_connector(x)     container_of((x), struct sde_connector, base)
+
+/**
+ * sde_connector_get_display - get sde connector's private display pointer
+ * @C: Pointer to drm connector structure
+ * Returns: Pointer to associated private display structure
+ */
+#define sde_connector_get_display(C) \
+	((C) ? to_sde_connector((C))->display : 0)
+
+/**
+ * sde_connector_get_panel - get sde connector's private panel pointer
+ * @C: Pointer to drm connector structure
+ * Returns: Pointer to associated private display structure
+ */
+#define sde_connector_get_panel(C) \
+	((C) ? to_sde_connector((C))->panel : 0)
+
+/**
+ * sde_connector_get_encoder - get sde connector's private encoder pointer
+ * @C: Pointer to drm connector structure
+ * Returns: Pointer to associated private encoder structure
+ */
+#define sde_connector_get_encoder(C) \
+	((C) ? to_sde_connector((C))->encoder : 0)
+
+/**
+ * sde_connector_get_propinfo - get sde connector's property info pointer
+ * @C: Pointer to drm connector structure
+ * Returns: Pointer to associated private property info structure
+ */
+#define sde_connector_get_propinfo(C) \
+	((C) ? &to_sde_connector((C))->property_info : 0)
+
+/**
+ * struct sde_connector_state - private connector status structure
+ * @base: Base drm connector structure
+ * @out_fb: Pointer to output frame buffer, if applicable
+ * @mmu_id: MMU ID for accessing frame buffer objects, if applicable
+ * @property_values: Local cache of current connector property values
+ */
+struct sde_connector_state {
+	struct drm_connector_state base;
+	struct drm_framebuffer *out_fb;
+	int mmu_id;
+	uint64_t property_values[CONNECTOR_PROP_COUNT];
+};
+
+/**
+ * to_sde_connector_state - convert drm_connector_state pointer to
+ *                          sde connector state pointer
+ * @X: Pointer to drm_connector_state structure
+ * Returns: Pointer to sde_connector_state structure
+ */
+#define to_sde_connector_state(x) \
+	container_of((x), struct sde_connector_state, base)
+
+/**
+ * sde_connector_get_property - query integer value of connector property
+ * @S: Pointer to drm connector state
+ * @X: Property index, from enum msm_mdp_connector_property
+ * Returns: Integer value of requested property
+ */
+#define sde_connector_get_property(S, X) \
+	((S) && ((X) < CONNECTOR_PROP_COUNT) ? \
+	 (to_sde_connector_state((S))->property_values[(X)]) : 0)
+
+/**
+ * sde_connector_get_property_values - retrieve property values cache
+ * @S: Pointer to drm connector state
+ * Returns: Integer value of requested property
+ */
+#define sde_connector_get_property_values(S) \
+	((S) ? (to_sde_connector_state((S))->property_values) : 0)
+
+/**
+ * sde_connector_get_out_fb - query out_fb value from sde connector state
+ * @S: Pointer to drm connector state
+ * Returns: Output fb associated with specified connector state
+ */
+#define sde_connector_get_out_fb(S) \
+	((S) ? to_sde_connector_state((S))->out_fb : 0)
+
+/**
+ * sde_connector_get_topology_name - helper accessor to retrieve topology_name
+ * @connector: pointer to drm connector
+ * Returns: value of the CONNECTOR_PROP_TOPOLOGY_NAME property or 0
+ */
+static inline uint64_t sde_connector_get_topology_name(
+		struct drm_connector *connector)
+{
+	if (!connector || !connector->state)
+		return 0;
+	return sde_connector_get_property(connector->state,
+			CONNECTOR_PROP_TOPOLOGY_NAME);
+}
+
+/**
+ * sde_connector_init - create drm connector object for a given display
+ * @dev: Pointer to drm device struct
+ * @encoder: Pointer to associated encoder
+ * @panel: Pointer to associated panel, can be NULL
+ * @display: Pointer to associated display object
+ * @ops: Pointer to callback operations function table
+ * @connector_poll: Set to appropriate DRM_CONNECTOR_POLL_ setting
+ * @connector_type: Set to appropriate DRM_MODE_CONNECTOR_ type
+ * Returns: Pointer to newly created drm connector struct
+ */
+struct drm_connector *sde_connector_init(struct drm_device *dev,
+		struct drm_encoder *encoder,
+		struct drm_panel *panel,
+		void *display,
+		const struct sde_connector_ops *ops,
+		int connector_poll,
+		int connector_type);
+
+/**
+ * sde_connector_prepare_fence - prepare fence support for current commit
+ * @connector: Pointer to drm connector object
+ */
+void sde_connector_prepare_fence(struct drm_connector *connector);
+
+/**
+ * sde_connector_complete_commit - signal completion of current commit
+ * @connector: Pointer to drm connector object
+ */
+void sde_connector_complete_commit(struct drm_connector *connector);
+
+/**
+ * sde_connector_get_info - query display specific information
+ * @connector: Pointer to drm connector object
+ * @info: Pointer to msm display information structure
+ * Returns: Zero on success
+ */
+int sde_connector_get_info(struct drm_connector *connector,
+		struct msm_display_info *info);
+
+#endif /* _SDE_CONNECTOR_H_ */
+
diff --git a/drivers/gpu/drm/msm/sde/sde_core_irq.c b/drivers/gpu/drm/msm/sde/sde_core_irq.c
new file mode 100644
index 0000000000000000000000000000000000000000..b2853e874d92f1276e0df2d204e0fc260a551460
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_irq.c
@@ -0,0 +1,460 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/debugfs.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/kthread.h>
+
+#include "sde_core_irq.h"
+#include "sde_power_handle.h"
+
+/**
+ * sde_core_irq_callback_handler - dispatch core interrupts
+ * @arg:		private data of callback handler
+ * @irq_idx:		interrupt index
+ */
+static void sde_core_irq_callback_handler(void *arg, int irq_idx)
+{
+	struct sde_kms *sde_kms = arg;
+	struct sde_irq *irq_obj = &sde_kms->irq_obj;
+	struct sde_irq_callback *cb;
+	unsigned long irq_flags;
+
+	SDE_DEBUG("irq_idx=%d\n", irq_idx);
+
+	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
+		SDE_ERROR("irq_idx=%d has no registered callback\n", irq_idx);
+
+	atomic_inc(&irq_obj->irq_counts[irq_idx]);
+
+	/*
+	 * Perform registered function callback
+	 */
+	spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
+	list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)
+		if (cb->func)
+			cb->func(cb->arg, irq_idx);
+	spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
+
+	/*
+	 * Clear pending interrupt status in HW.
+	 * NOTE: sde_core_irq_callback_handler is protected by top-level
+	 *       spinlock, so it is safe to clear any interrupt status here.
+	 */
+	sde_kms->hw_intr->ops.clear_interrupt_status(
+			sde_kms->hw_intr,
+			irq_idx);
+}
+
+int sde_core_irq_idx_lookup(struct sde_kms *sde_kms,
+		enum sde_intr_type intr_type, u32 instance_idx)
+{
+	if (!sde_kms || !sde_kms->hw_intr ||
+			!sde_kms->hw_intr->ops.irq_idx_lookup)
+		return -EINVAL;
+
+	return sde_kms->hw_intr->ops.irq_idx_lookup(intr_type,
+			instance_idx);
+}
+
+/**
+ * _sde_core_irq_enable - enable core interrupt given by the index
+ * @sde_kms:		Pointer to sde kms context
+ * @irq_idx:		interrupt index
+ */
+static int _sde_core_irq_enable(struct sde_kms *sde_kms, int irq_idx)
+{
+	unsigned long irq_flags;
+	int ret = 0;
+
+	if (!sde_kms || !sde_kms->hw_intr ||
+			!sde_kms->irq_obj.enable_counts ||
+			!sde_kms->irq_obj.irq_counts) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
+		SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
+			atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
+
+	spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
+	SDE_EVT32(irq_idx,
+			atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
+	if (atomic_inc_return(&sde_kms->irq_obj.enable_counts[irq_idx]) == 1) {
+		ret = sde_kms->hw_intr->ops.enable_irq(
+				sde_kms->hw_intr,
+				irq_idx);
+		if (ret)
+			SDE_ERROR("Fail to enable IRQ for irq_idx:%d\n",
+					irq_idx);
+
+		SDE_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
+
+		/* empty callback list but interrupt is enabled */
+		if (list_empty(&sde_kms->irq_obj.irq_cb_tbl[irq_idx]))
+			SDE_ERROR("irq_idx=%d enabled with no callback\n",
+					irq_idx);
+	}
+	spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
+
+	return ret;
+}
+
+int sde_core_irq_enable(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count)
+{
+	int i;
+	int ret = 0;
+
+	if (!sde_kms || !irq_idxs || !irq_count) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; (i < irq_count) && !ret; i++)
+		ret = _sde_core_irq_enable(sde_kms, irq_idxs[i]);
+
+	return ret;
+}
+
+/**
+ * _sde_core_irq_disable - disable core interrupt given by the index
+ * @sde_kms:		Pointer to sde kms context
+ * @irq_idx:		interrupt index
+ */
+static int _sde_core_irq_disable(struct sde_kms *sde_kms, int irq_idx)
+{
+	unsigned long irq_flags;
+	int ret = 0;
+
+	if (!sde_kms || !sde_kms->hw_intr || !sde_kms->irq_obj.enable_counts) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
+		SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
+			atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
+
+	spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
+	SDE_EVT32(irq_idx,
+			atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
+	if (atomic_dec_return(&sde_kms->irq_obj.enable_counts[irq_idx]) == 0) {
+		ret = sde_kms->hw_intr->ops.disable_irq(
+				sde_kms->hw_intr,
+				irq_idx);
+		if (ret)
+			SDE_ERROR("Fail to disable IRQ for irq_idx:%d\n",
+					irq_idx);
+		SDE_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
+	}
+	spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
+
+	return ret;
+}
+
+int sde_core_irq_disable(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count)
+{
+	int i;
+	int ret = 0;
+
+	if (!sde_kms || !irq_idxs || !irq_count) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; (i < irq_count) && !ret; i++)
+		ret = _sde_core_irq_disable(sde_kms, irq_idxs[i]);
+
+	return ret;
+}
+
+u32 sde_core_irq_read(struct sde_kms *sde_kms, int irq_idx, bool clear)
+{
+	if (!sde_kms || !sde_kms->hw_intr ||
+			!sde_kms->hw_intr->ops.get_interrupt_status)
+		return 0;
+
+	return sde_kms->hw_intr->ops.get_interrupt_status(sde_kms->hw_intr,
+			irq_idx, clear);
+}
+
+int sde_core_irq_register_callback(struct sde_kms *sde_kms, int irq_idx,
+		struct sde_irq_callback *register_irq_cb)
+{
+	unsigned long irq_flags;
+
+	if (!sde_kms || !register_irq_cb || !register_irq_cb->func ||
+			!sde_kms->irq_obj.irq_cb_tbl) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
+		SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
+
+	spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
+	SDE_EVT32(irq_idx, register_irq_cb);
+	list_del_init(&register_irq_cb->list);
+	list_add_tail(&register_irq_cb->list,
+			&sde_kms->irq_obj.irq_cb_tbl[irq_idx]);
+	spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
+
+	return 0;
+}
+
+int sde_core_irq_unregister_callback(struct sde_kms *sde_kms, int irq_idx,
+		struct sde_irq_callback *register_irq_cb)
+{
+	unsigned long irq_flags;
+
+	if (!sde_kms || !register_irq_cb || !register_irq_cb->func ||
+			!sde_kms->irq_obj.irq_cb_tbl) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
+		SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
+
+	spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
+	SDE_EVT32(irq_idx, register_irq_cb);
+	list_del_init(&register_irq_cb->list);
+	/* empty callback list but interrupt is still enabled */
+	if (list_empty(&sde_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
+			atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]))
+		SDE_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);
+	spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
+
+	return 0;
+}
+
+static void sde_clear_all_irqs(struct sde_kms *sde_kms)
+{
+	if (!sde_kms || !sde_kms->hw_intr ||
+			!sde_kms->hw_intr->ops.clear_all_irqs)
+		return;
+
+	sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
+}
+
+static void sde_disable_all_irqs(struct sde_kms *sde_kms)
+{
+	if (!sde_kms || !sde_kms->hw_intr ||
+			!sde_kms->hw_intr->ops.disable_all_irqs)
+		return;
+
+	sde_kms->hw_intr->ops.disable_all_irqs(sde_kms->hw_intr);
+}
+
+#ifdef CONFIG_DEBUG_FS
+#define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix)				\
+static int __prefix ## _open(struct inode *inode, struct file *file)	\
+{									\
+	return single_open(file, __prefix ## _show, inode->i_private);	\
+}									\
+static const struct file_operations __prefix ## _fops = {		\
+	.owner = THIS_MODULE,						\
+	.open = __prefix ## _open,					\
+	.release = single_release,					\
+	.read = seq_read,						\
+	.llseek = seq_lseek,						\
+}
+
+static int sde_debugfs_core_irq_show(struct seq_file *s, void *v)
+{
+	struct sde_irq *irq_obj = s->private;
+	struct sde_irq_callback *cb;
+	unsigned long irq_flags;
+	int i, irq_count, enable_count, cb_count;
+
+	if (!irq_obj || !irq_obj->enable_counts || !irq_obj->irq_cb_tbl) {
+		SDE_ERROR("invalid parameters\n");
+		return 0;
+	}
+
+	for (i = 0; i < irq_obj->total_irqs; i++) {
+		spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
+		cb_count = 0;
+		irq_count = atomic_read(&irq_obj->irq_counts[i]);
+		enable_count = atomic_read(&irq_obj->enable_counts[i]);
+		list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
+			cb_count++;
+		spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
+
+		if (irq_count || enable_count || cb_count)
+			seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",
+					i, irq_count, enable_count, cb_count);
+	}
+
+	return 0;
+}
+
+DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_debugfs_core_irq);
+
+static int sde_debugfs_core_irq_init(struct sde_kms *sde_kms,
+		struct dentry *parent)
+{
+	sde_kms->irq_obj.debugfs_file = debugfs_create_file("core_irq", 0644,
+			parent, &sde_kms->irq_obj,
+			&sde_debugfs_core_irq_fops);
+
+	return 0;
+}
+
+static void sde_debugfs_core_irq_destroy(struct sde_kms *sde_kms)
+{
+	debugfs_remove(sde_kms->irq_obj.debugfs_file);
+	sde_kms->irq_obj.debugfs_file = NULL;
+}
+
+#else
+static int sde_debugfs_core_irq_init(struct sde_kms *sde_kms,
+		struct dentry *parent)
+{
+	return 0;
+}
+
+static void sde_debugfs_core_irq_destroy(struct sde_kms *sde_kms)
+{
+}
+#endif
+
+void sde_core_irq_preinstall(struct sde_kms *sde_kms)
+{
+	struct msm_drm_private *priv;
+	int i;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde_kms\n");
+		return;
+	} else if (!sde_kms->dev) {
+		SDE_ERROR("invalid drm device\n");
+		return;
+	} else if (!sde_kms->dev->dev_private) {
+		SDE_ERROR("invalid device private\n");
+		return;
+	}
+	priv = sde_kms->dev->dev_private;
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+	sde_clear_all_irqs(sde_kms);
+	sde_disable_all_irqs(sde_kms);
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+
+	spin_lock_init(&sde_kms->irq_obj.cb_lock);
+
+	/* Create irq callbacks for all possible irq_idx */
+	sde_kms->irq_obj.total_irqs = sde_kms->hw_intr->irq_idx_tbl_size;
+	sde_kms->irq_obj.irq_cb_tbl = kcalloc(sde_kms->irq_obj.total_irqs,
+			sizeof(struct list_head), GFP_KERNEL);
+	sde_kms->irq_obj.enable_counts = kcalloc(sde_kms->irq_obj.total_irqs,
+			sizeof(atomic_t), GFP_KERNEL);
+	sde_kms->irq_obj.irq_counts = kcalloc(sde_kms->irq_obj.total_irqs,
+			sizeof(atomic_t), GFP_KERNEL);
+	for (i = 0; i < sde_kms->irq_obj.total_irqs; i++) {
+		INIT_LIST_HEAD(&sde_kms->irq_obj.irq_cb_tbl[i]);
+		atomic_set(&sde_kms->irq_obj.enable_counts[i], 0);
+		atomic_set(&sde_kms->irq_obj.irq_counts[i], 0);
+	}
+
+	sde_debugfs_core_irq_init(sde_kms, sde_kms->debugfs_root);
+}
+
+int sde_core_irq_postinstall(struct sde_kms *sde_kms)
+{
+	return 0;
+}
+
+void sde_core_irq_uninstall(struct sde_kms *sde_kms)
+{
+	struct msm_drm_private *priv;
+	int i;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde_kms\n");
+		return;
+	} else if (!sde_kms->dev) {
+		SDE_ERROR("invalid drm device\n");
+		return;
+	} else if (!sde_kms->dev->dev_private) {
+		SDE_ERROR("invalid device private\n");
+		return;
+	}
+	priv = sde_kms->dev->dev_private;
+
+	sde_debugfs_core_irq_destroy(sde_kms);
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+	for (i = 0; i < sde_kms->irq_obj.total_irqs; i++)
+		if (atomic_read(&sde_kms->irq_obj.enable_counts[i]) ||
+				!list_empty(&sde_kms->irq_obj.irq_cb_tbl[i]))
+			SDE_ERROR("irq_idx=%d still enabled/registered\n", i);
+
+	sde_clear_all_irqs(sde_kms);
+	sde_disable_all_irqs(sde_kms);
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+
+	kfree(sde_kms->irq_obj.irq_cb_tbl);
+	kfree(sde_kms->irq_obj.enable_counts);
+	kfree(sde_kms->irq_obj.irq_counts);
+	sde_kms->irq_obj.irq_cb_tbl = NULL;
+	sde_kms->irq_obj.enable_counts = NULL;
+	sde_kms->irq_obj.irq_counts = NULL;
+	sde_kms->irq_obj.total_irqs = 0;
+}
+
+irqreturn_t sde_core_irq(struct sde_kms *sde_kms)
+{
+	/*
+	 * Read interrupt status from all sources. Interrupt status are
+	 * stored within hw_intr.
+	 * Function will also clear the interrupt status after reading.
+	 * Individual interrupt status bit will only get stored if it
+	 * is enabled.
+	 */
+	sde_kms->hw_intr->ops.get_interrupt_statuses(sde_kms->hw_intr);
+
+	/*
+	 * Dispatch to HW driver to handle interrupt lookup that is being
+	 * fired. When matching interrupt is located, HW driver will call to
+	 * sde_core_irq_callback_handler with the irq_idx from the lookup table.
+	 * sde_core_irq_callback_handler will perform the registered function
+	 * callback, and do the interrupt status clearing once the registered
+	 * callback is finished.
+	 */
+	sde_kms->hw_intr->ops.dispatch_irqs(
+			sde_kms->hw_intr,
+			sde_core_irq_callback_handler,
+			sde_kms);
+
+	return IRQ_HANDLED;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_core_irq.h b/drivers/gpu/drm/msm/sde/sde_core_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..92642e73daa87fcc1f7d4473625396c1af8d7161
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_irq.h
@@ -0,0 +1,138 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_CORE_IRQ_H__
+#define __SDE_CORE_IRQ_H__
+
+#include "sde_kms.h"
+#include "sde_hw_interrupts.h"
+
+/**
+ * sde_core_irq_preinstall - perform pre-installation of core IRQ handler
+ * @sde_kms:		SDE handle
+ * @return:		none
+ */
+void sde_core_irq_preinstall(struct sde_kms *sde_kms);
+
+/**
+ * sde_core_irq_postinstall - perform post-installation of core IRQ handler
+ * @sde_kms:		SDE handle
+ * @return:		0 if success; error code otherwise
+ */
+int sde_core_irq_postinstall(struct sde_kms *sde_kms);
+
+/**
+ * sde_core_irq_uninstall - uninstall core IRQ handler
+ * @sde_kms:		SDE handle
+ * @return:		none
+ */
+void sde_core_irq_uninstall(struct sde_kms *sde_kms);
+
+/**
+ * sde_core_irq - core IRQ handler
+ * @sde_kms:		SDE handle
+ * @return:		interrupt handling status
+ */
+irqreturn_t sde_core_irq(struct sde_kms *sde_kms);
+
+/**
+ * sde_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW
+ *                      interrupt mapping table.
+ * @sde_kms:		SDE handle
+ * @intr_type:		SDE HW interrupt type for lookup
+ * @instance_idx:	SDE HW block instance defined in sde_hw_mdss.h
+ * @return:		irq_idx or -EINVAL when fail to lookup
+ */
+int sde_core_irq_idx_lookup(
+		struct sde_kms *sde_kms,
+		enum sde_intr_type intr_type,
+		uint32_t instance_idx);
+
+/**
+ * sde_core_irq_enable - IRQ helper function for enabling one or more IRQs
+ * @sde_kms:		SDE handle
+ * @irq_idxs:		Array of irq index
+ * @irq_count:		Number of irq_idx provided in the array
+ * @return:		0 for success enabling IRQ, otherwise failure
+ *
+ * This function increments count on each enable and decrements on each
+ * disable.  Interrupts is enabled if count is 0 before increment.
+ */
+int sde_core_irq_enable(
+		struct sde_kms *sde_kms,
+		int *irq_idxs,
+		uint32_t irq_count);
+
+/**
+ * sde_core_irq_disable - IRQ helper function for disabling one of more IRQs
+ * @sde_kms:		SDE handle
+ * @irq_idxs:		Array of irq index
+ * @irq_count:		Number of irq_idx provided in the array
+ * @return:		0 for success disabling IRQ, otherwise failure
+ *
+ * This function increments count on each enable and decrements on each
+ * disable.  Interrupts is disabled if count is 0 after decrement.
+ */
+int sde_core_irq_disable(
+		struct sde_kms *sde_kms,
+		int *irq_idxs,
+		uint32_t irq_count);
+
+/**
+ * sde_core_irq_read - IRQ helper function for reading IRQ status
+ * @sde_kms:		SDE handle
+ * @irq_idx:		irq index
+ * @clear:		True to clear the irq after read
+ * @return:		non-zero if irq detected; otherwise no irq detected
+ */
+u32 sde_core_irq_read(
+		struct sde_kms *sde_kms,
+		int irq_idx,
+		bool clear);
+
+/**
+ * sde_core_irq_register_callback - For registering callback function on IRQ
+ *                             interrupt
+ * @sde_kms:		SDE handle
+ * @irq_idx:		irq index
+ * @irq_cb:		IRQ callback structure, containing callback function
+ *			and argument. Passing NULL for irq_cb will unregister
+ *			the callback for the given irq_idx
+ *			This must exist until un-registration.
+ * @return:		0 for success registering callback, otherwise failure
+ *
+ * This function supports registration of multiple callbacks for each interrupt.
+ */
+int sde_core_irq_register_callback(
+		struct sde_kms *sde_kms,
+		int irq_idx,
+		struct sde_irq_callback *irq_cb);
+
+/**
+ * sde_core_irq_unregister_callback - For unregistering callback function on IRQ
+ *                             interrupt
+ * @sde_kms:		SDE handle
+ * @irq_idx:		irq index
+ * @irq_cb:		IRQ callback structure, containing callback function
+ *			and argument. Passing NULL for irq_cb will unregister
+ *			the callback for the given irq_idx
+ *			This must match with registration.
+ * @return:		0 for success registering callback, otherwise failure
+ *
+ * This function supports registration of multiple callbacks for each interrupt.
+ */
+int sde_core_irq_unregister_callback(
+		struct sde_kms *sde_kms,
+		int irq_idx,
+		struct sde_irq_callback *irq_cb);
+
+#endif /* __SDE_CORE_IRQ_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ba644d5519db520b0a5dc33a746632ece130f27
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -0,0 +1,610 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/debugfs.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/sort.h>
+#include <linux/clk.h>
+#include <linux/bitmap.h>
+
+#include "msm_prop.h"
+
+#include "sde_kms.h"
+#include "sde_fence.h"
+#include "sde_formats.h"
+#include "sde_hw_sspp.h"
+#include "sde_trace.h"
+#include "sde_crtc.h"
+#include "sde_plane.h"
+#include "sde_encoder.h"
+#include "sde_wb.h"
+#include "sde_core_perf.h"
+#include "sde_trace.h"
+
+static struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
+{
+	struct msm_drm_private *priv;
+
+	if (!crtc->dev || !crtc->dev->dev_private) {
+		SDE_ERROR("invalid device\n");
+		return NULL;
+	}
+
+	priv = crtc->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid kms\n");
+		return NULL;
+	}
+
+	return to_sde_kms(priv->kms);
+}
+
+static bool _sde_core_perf_crtc_is_power_on(struct drm_crtc *crtc)
+{
+	return sde_crtc_is_enabled(crtc);
+}
+
+static bool _sde_core_video_mode_intf_connected(struct drm_crtc *crtc)
+{
+	struct drm_crtc *tmp_crtc;
+
+	if (!crtc)
+		return 0;
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if ((sde_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) &&
+				_sde_core_perf_crtc_is_power_on(tmp_crtc)) {
+			SDE_DEBUG("video interface connected crtc:%d\n",
+				tmp_crtc->base.id);
+			return true;
+		}
+	}
+
+	return false;
+}
+
+int sde_core_perf_crtc_check(struct drm_crtc *crtc,
+		struct drm_crtc_state *state)
+{
+	u32 bw, threshold;
+	u64 bw_sum_of_intfs = 0;
+	bool is_video_mode;
+	struct sde_crtc_state *sde_cstate;
+	struct drm_crtc *tmp_crtc;
+	struct sde_kms *kms;
+
+	if (!crtc || !state) {
+		SDE_ERROR("invalid crtc\n");
+		return -EINVAL;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid parameters\n");
+		return 0;
+	}
+
+	/* we only need bandwidth check on real-time clients (interfaces) */
+	if (sde_crtc_is_wb(crtc))
+		return 0;
+
+	sde_cstate = to_sde_crtc_state(state);
+
+	bw_sum_of_intfs = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if (_sde_core_perf_crtc_is_power_on(tmp_crtc) &&
+				sde_crtc_is_rt(tmp_crtc) && tmp_crtc != crtc) {
+			struct sde_crtc_state *tmp_cstate =
+					to_sde_crtc_state(tmp_crtc->state);
+
+			bw_sum_of_intfs += tmp_cstate->cur_perf.bw_ctl;
+		}
+	}
+
+	/* convert bandwidth to kb */
+	bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
+	SDE_DEBUG("calculated bandwidth=%uk\n", bw);
+
+	is_video_mode = sde_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO;
+	threshold = (is_video_mode ||
+		_sde_core_video_mode_intf_connected(crtc)) ?
+		kms->catalog->perf.max_bw_low : kms->catalog->perf.max_bw_high;
+
+	SDE_DEBUG("final threshold bw limit = %d\n", threshold);
+
+	if (!threshold) {
+		sde_cstate->cur_perf.bw_ctl = 0;
+		SDE_ERROR("no bandwidth limits specified\n");
+		return -E2BIG;
+	} else if (bw > threshold) {
+		sde_cstate->cur_perf.bw_ctl = 0;
+		SDE_DEBUG("exceeds bandwidth: %ukb > %ukb\n", bw, threshold);
+		return -E2BIG;
+	}
+
+	return 0;
+}
+
+static void _sde_core_perf_calc_crtc(struct sde_kms *kms,
+		struct drm_crtc *crtc,
+		struct sde_core_perf_params *perf)
+{
+	struct sde_crtc_state *sde_cstate;
+
+	sde_cstate = to_sde_crtc_state(crtc->state);
+	memset(perf, 0, sizeof(struct sde_core_perf_params));
+
+	perf->bw_ctl = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+	perf->max_per_pipe_ib =
+			sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_IB);
+	perf->core_clk_rate =
+			sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_CLK);
+
+	SDE_DEBUG("crtc=%d clk_rate=%u ib=%llu ab=%llu\n",
+			crtc->base.id, perf->core_clk_rate,
+			perf->max_per_pipe_ib, perf->bw_ctl);
+}
+
+static u64 _sde_core_perf_crtc_calc_client_vote(struct sde_kms *kms,
+		struct drm_crtc *crtc, struct sde_core_perf_params *perf,
+		bool nrt_client, u32 core_clk)
+{
+	u64 bw_sum_of_intfs = 0;
+	struct drm_crtc *tmp_crtc;
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if (_sde_core_perf_crtc_is_power_on(crtc) &&
+		    /* RealTime clients */
+		    ((!nrt_client) ||
+		    /* Non-RealTime clients */
+		    (nrt_client && sde_crtc_is_nrt(tmp_crtc)))) {
+			struct sde_crtc_state *sde_cstate =
+					to_sde_crtc_state(tmp_crtc->state);
+
+			perf->max_per_pipe_ib = max(perf->max_per_pipe_ib,
+				sde_cstate->cur_perf.max_per_pipe_ib);
+
+			bw_sum_of_intfs += sde_cstate->cur_perf.bw_ctl;
+
+			SDE_DEBUG("crtc=%d bw=%llu\n",
+				tmp_crtc->base.id,
+				sde_cstate->cur_perf.bw_ctl);
+		}
+	}
+
+	return bw_sum_of_intfs;
+}
+
+static void _sde_core_perf_crtc_update_client_vote(struct sde_kms *kms,
+	struct sde_core_perf_params *params, bool nrt_client, u64 bw_vote)
+{
+	struct msm_drm_private *priv = kms->dev->dev_private;
+	u64 bus_ab_quota, bus_ib_quota;
+
+	bus_ab_quota = max(bw_vote, kms->perf.perf_tune.min_bus_vote);
+	bus_ib_quota = params->max_per_pipe_ib;
+
+	SDE_ATRACE_INT("bus_quota", bus_ib_quota);
+	sde_power_data_bus_set_quota(&priv->phandle, kms->core_client,
+		nrt_client ? SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT :
+				SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT,
+		bus_ab_quota, bus_ib_quota);
+	SDE_DEBUG("client:%s ab=%llu ib=%llu\n", nrt_client ? "nrt" : "rt",
+		bus_ab_quota, bus_ib_quota);
+}
+
+static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
+		struct drm_crtc *crtc, u32 core_clk)
+{
+	u64 bw_sum_of_rt_intfs = 0, bw_sum_of_nrt_intfs = 0;
+	struct sde_core_perf_params params = {0};
+
+	SDE_ATRACE_BEGIN(__func__);
+
+	/*
+	 * non-real time client
+	 */
+	if (sde_crtc_is_nrt(crtc)) {
+		bw_sum_of_nrt_intfs = _sde_core_perf_crtc_calc_client_vote(
+				kms, crtc, &params, true, core_clk);
+		_sde_core_perf_crtc_update_client_vote(kms, &params, true,
+			bw_sum_of_nrt_intfs);
+	}
+
+	/*
+	 * real time client
+	 */
+	if (!sde_crtc_is_nrt(crtc) ||
+		sde_crtc_is_wb(crtc)) {
+		bw_sum_of_rt_intfs = _sde_core_perf_crtc_calc_client_vote(kms,
+				crtc, &params, false, core_clk);
+		_sde_core_perf_crtc_update_client_vote(kms, &params, false,
+			bw_sum_of_rt_intfs);
+	}
+
+	SDE_ATRACE_END(__func__);
+}
+
+/**
+ * @sde_core_perf_crtc_release_bw() - request zero bandwidth
+ * @crtc - pointer to a crtc
+ *
+ * Function checks a state variable for the crtc, if all pending commit
+ * requests are done, meaning no more bandwidth is needed, release
+ * bandwidth request.
+ */
+void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
+{
+	struct drm_crtc *tmp_crtc;
+	struct sde_crtc_state *sde_cstate;
+	struct sde_kms *kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+
+	sde_cstate = to_sde_crtc_state(crtc->state);
+
+	/* only do this for command panel or writeback */
+	if ((sde_crtc_get_intf_mode(crtc) != INTF_MODE_CMD) &&
+			(sde_crtc_get_intf_mode(crtc) != INTF_MODE_WB_LINE))
+		return;
+
+	/*
+	 * If video interface present, cmd panel bandwidth cannot be
+	 * released.
+	 */
+	if (sde_crtc_get_intf_mode(crtc) == INTF_MODE_CMD)
+		drm_for_each_crtc(tmp_crtc, crtc->dev) {
+			if (_sde_core_perf_crtc_is_power_on(tmp_crtc) &&
+				sde_crtc_get_intf_mode(tmp_crtc) ==
+						INTF_MODE_VIDEO)
+				return;
+		}
+
+	/* Release the bandwidth */
+	if (kms->perf.enable_bw_release) {
+		trace_sde_cmd_release_bw(crtc->base.id);
+		sde_cstate->cur_perf.bw_ctl = 0;
+		sde_cstate->new_perf.bw_ctl = 0;
+		SDE_DEBUG("Release BW crtc=%d\n", crtc->base.id);
+		_sde_core_perf_crtc_update_bus(kms, crtc, 0);
+	}
+}
+
+static int _sde_core_select_clk_lvl(struct sde_kms *kms,
+			u32 clk_rate)
+{
+	return clk_round_rate(kms->perf.core_clk, clk_rate);
+}
+
+static u32 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms)
+{
+	u32 clk_rate = 0;
+	struct drm_crtc *crtc;
+	struct sde_crtc_state *sde_cstate;
+	int ncrtc = 0;
+
+	drm_for_each_crtc(crtc, kms->dev) {
+		if (_sde_core_perf_crtc_is_power_on(crtc)) {
+			sde_cstate = to_sde_crtc_state(crtc->state);
+			clk_rate = max(sde_cstate->cur_perf.core_clk_rate,
+							clk_rate);
+			clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
+		}
+		ncrtc++;
+	}
+	clk_rate = _sde_core_select_clk_lvl(kms, clk_rate);
+
+	SDE_DEBUG("clk:%u ncrtc:%d\n", clk_rate, ncrtc);
+
+	return clk_rate;
+}
+
+void sde_core_perf_crtc_update(struct drm_crtc *crtc,
+		int params_changed, bool stop_req)
+{
+	struct sde_core_perf_params *new, *old;
+	int update_bus = 0, update_clk = 0;
+	u32 clk_rate = 0;
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *sde_cstate;
+	int ret;
+	struct msm_drm_private *priv;
+	struct sde_kms *kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+	priv = kms->dev->dev_private;
+
+	sde_crtc = to_sde_crtc(crtc);
+	sde_cstate = to_sde_crtc_state(crtc->state);
+
+	SDE_DEBUG("crtc:%d stop_req:%d core_clk:%u\n",
+			crtc->base.id, stop_req, kms->perf.core_clk_rate);
+
+	SDE_ATRACE_BEGIN(__func__);
+
+	old = &sde_cstate->cur_perf;
+	new = &sde_cstate->new_perf;
+
+	if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {
+		if (params_changed)
+			_sde_core_perf_calc_crtc(kms, crtc, new);
+
+		/*
+		 * cases for bus bandwidth update.
+		 * 1. new bandwidth vote or writeback output vote
+		 *    are higher than current vote for update request.
+		 * 2. new bandwidth vote or writeback output vote are
+		 *    lower than current vote at end of commit or stop.
+		 */
+		if ((params_changed && ((new->bw_ctl > old->bw_ctl))) ||
+		    (!params_changed && ((new->bw_ctl < old->bw_ctl)))) {
+			SDE_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
+				crtc->base.id, params_changed, new->bw_ctl,
+				old->bw_ctl);
+			old->bw_ctl = new->bw_ctl;
+			old->max_per_pipe_ib = new->max_per_pipe_ib;
+			update_bus = 1;
+		}
+
+		if ((params_changed &&
+				(new->core_clk_rate > old->core_clk_rate)) ||
+				(!params_changed &&
+				(new->core_clk_rate < old->core_clk_rate))) {
+			old->core_clk_rate = new->core_clk_rate;
+			update_clk = 1;
+		}
+	} else {
+		SDE_DEBUG("crtc=%d disable\n", crtc->base.id);
+		memset(old, 0, sizeof(*old));
+		memset(new, 0, sizeof(*new));
+		update_bus = 1;
+		update_clk = 1;
+	}
+
+	/*
+	 * Calculate mdp clock before bandwidth calculation. If traffic shaper
+	 * is enabled and clock increased, the bandwidth calculation can
+	 * use the new clock for the rotator bw calculation.
+	 */
+	if (update_clk)
+		clk_rate = _sde_core_perf_get_core_clk_rate(kms);
+
+	if (update_bus)
+		_sde_core_perf_crtc_update_bus(kms, crtc, clk_rate);
+
+	/*
+	 * Update the clock after bandwidth vote to ensure
+	 * bandwidth is available before clock rate is increased.
+	 */
+	if (update_clk) {
+		SDE_ATRACE_INT(kms->perf.clk_name, clk_rate);
+		SDE_EVT32(kms->dev, stop_req, clk_rate);
+		ret = sde_power_clk_set_rate(&priv->phandle,
+				kms->perf.clk_name, clk_rate);
+		if (ret) {
+			SDE_ERROR("failed to set %s clock rate %u\n",
+					kms->perf.clk_name, clk_rate);
+			goto end;
+		}
+
+		kms->perf.core_clk_rate = clk_rate;
+		SDE_DEBUG("update clk rate = %d HZ\n", clk_rate);
+	}
+
+end:
+	SDE_ATRACE_END(__func__);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static ssize_t _sde_core_perf_mode_write(struct file *file,
+		    const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct sde_core_perf *perf = file->private_data;
+	struct sde_perf_cfg *cfg = &perf->catalog->perf;
+	int perf_mode = 0;
+	char buf[10];
+
+	if (!perf)
+		return -ENODEV;
+
+	if (count >= sizeof(buf))
+		return -EFAULT;
+
+	if (copy_from_user(buf, user_buf, count))
+		return -EFAULT;
+
+	buf[count] = 0;	/* end of string */
+
+	if (kstrtoint(buf, 0, &perf_mode))
+		return -EFAULT;
+
+	if (perf_mode) {
+		/* run the driver with max clk and BW vote */
+		perf->perf_tune.min_core_clk = perf->max_core_clk_rate;
+		perf->perf_tune.min_bus_vote =
+				(u64) cfg->max_bw_high * 1000;
+	} else {
+		/* reset the perf tune params to 0 */
+		perf->perf_tune.min_core_clk = 0;
+		perf->perf_tune.min_bus_vote = 0;
+	}
+	return count;
+}
+
+static ssize_t _sde_core_perf_mode_read(struct file *file,
+			char __user *buff, size_t count, loff_t *ppos)
+{
+	struct sde_core_perf *perf = file->private_data;
+	int len = 0;
+	char buf[40] = {'\0'};
+
+	if (!perf)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0;	/* the end */
+
+	len = snprintf(buf, sizeof(buf), "min_mdp_clk %lu min_bus_vote %llu\n",
+			perf->perf_tune.min_core_clk,
+			perf->perf_tune.min_bus_vote);
+	if (len < 0 || len >= sizeof(buf))
+		return 0;
+
+	if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
+		return -EFAULT;
+
+	*ppos += len;   /* increase offset */
+
+	return len;
+}
+
+static const struct file_operations sde_core_perf_mode_fops = {
+	.open = simple_open,
+	.read = _sde_core_perf_mode_read,
+	.write = _sde_core_perf_mode_write,
+};
+
+static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
+{
+	debugfs_remove_recursive(perf->debugfs_root);
+	perf->debugfs_root = NULL;
+}
+
+static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
+		struct dentry *parent)
+{
+	struct sde_mdss_cfg *catalog = perf->catalog;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	priv = perf->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid KMS reference\n");
+		return -EINVAL;
+	}
+
+	sde_kms = to_sde_kms(priv->kms);
+
+	perf->debugfs_root = debugfs_create_dir("core_perf", parent);
+	if (!perf->debugfs_root) {
+		SDE_ERROR("failed to create core perf debugfs\n");
+		return -EINVAL;
+	}
+
+	debugfs_create_u64("max_core_clk_rate", 0644, perf->debugfs_root,
+			&perf->max_core_clk_rate);
+	debugfs_create_u32("core_clk_rate", 0644, perf->debugfs_root,
+			&perf->core_clk_rate);
+	debugfs_create_u32("enable_bw_release", 0644, perf->debugfs_root,
+			(u32 *)&perf->enable_bw_release);
+	debugfs_create_u32("threshold_low", 0644, perf->debugfs_root,
+			(u32 *)&catalog->perf.max_bw_low);
+	debugfs_create_u32("threshold_high", 0644, perf->debugfs_root,
+			(u32 *)&catalog->perf.max_bw_high);
+	debugfs_create_file("perf_mode", 0644, perf->debugfs_root,
+			(u32 *)perf, &sde_core_perf_mode_fops);
+
+	return 0;
+}
+#else
+static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
+{
+}
+
+static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
+		struct dentry *parent)
+{
+	return 0;
+}
+#endif
+
+void sde_core_perf_destroy(struct sde_core_perf *perf)
+{
+	if (!perf) {
+		SDE_ERROR("invalid parameters\n");
+		return;
+	}
+
+	sde_debugfs_core_perf_destroy(perf);
+	perf->max_core_clk_rate = 0;
+	perf->core_clk = NULL;
+	mutex_destroy(&perf->perf_lock);
+	perf->clk_name = NULL;
+	perf->phandle = NULL;
+	perf->catalog = NULL;
+	perf->dev = NULL;
+}
+
+int sde_core_perf_init(struct sde_core_perf *perf,
+		struct drm_device *dev,
+		struct sde_mdss_cfg *catalog,
+		struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		char *clk_name,
+		struct dentry *debugfs_parent)
+{
+	if (!perf || !catalog || !phandle || !pclient ||
+			!clk_name || !debugfs_parent) {
+		SDE_ERROR("invalid parameters\n");
+		return -EINVAL;
+	}
+
+	perf->dev = dev;
+	perf->catalog = catalog;
+	perf->phandle = phandle;
+	perf->pclient = pclient;
+	perf->clk_name = clk_name;
+	mutex_init(&perf->perf_lock);
+
+	perf->core_clk = sde_power_clk_get_clk(phandle, clk_name);
+	if (!perf->core_clk) {
+		SDE_ERROR("invalid core clk\n");
+		goto err;
+	}
+
+	perf->max_core_clk_rate = sde_power_clk_get_max_rate(phandle, clk_name);
+	if (!perf->max_core_clk_rate) {
+		SDE_ERROR("invalid max core clk rate\n");
+		goto err;
+	}
+
+	sde_debugfs_core_perf_init(perf, debugfs_parent);
+
+	return 0;
+
+err:
+	sde_core_perf_destroy(perf);
+	return -ENODEV;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.h b/drivers/gpu/drm/msm/sde/sde_core_perf.h
new file mode 100644
index 0000000000000000000000000000000000000000..e5dd9b6e67045dff245dfd0b81ed8333212d1e8e
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.h
@@ -0,0 +1,124 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_CORE_PERF_H__
+#define __SDE_CORE_PERF_H__
+
+#include <linux/types.h>
+#include <linux/dcache.h>
+#include <linux/mutex.h>
+#include <drm/drm_crtc.h>
+
+#include "sde_hw_catalog.h"
+#include "sde_power_handle.h"
+
+/**
+ * struct sde_core_perf_params - definition of performance parameters
+ * @max_per_pipe_ib: maximum instantaneous bandwidth request
+ * @bw_ctl: arbitrated bandwidth request
+ * @core_clk_rate: core clock rate request
+ */
+struct sde_core_perf_params {
+	u64 max_per_pipe_ib;
+	u64 bw_ctl;
+	u32 core_clk_rate;
+};
+
+/**
+ * struct sde_core_perf_tune - definition of performance tuning control
+ * @min_core_clk: minimum core clock
+ * @min_bus_vote: minimum bus vote
+ */
+struct sde_core_perf_tune {
+	unsigned long min_core_clk;
+	u64 min_bus_vote;
+};
+
+/**
+ * struct sde_core_perf - definition of core performance context
+ * @dev: Pointer to drm device
+ * @debugfs_root: top level debug folder
+ * @perf_lock: serialization lock for this context
+ * @catalog: Pointer to catalog configuration
+ * @phandle: Pointer to power handler
+ * @pclient: Pointer to power client
+ * @clk_name: core clock name
+ * @core_clk: Pointer to core clock structure
+ * @core_clk_rate: current core clock rate
+ * @max_core_clk_rate: maximum allowable core clock rate
+ * @perf_tune: debug control for performance tuning
+ * @enable_bw_release: debug control for bandwidth release
+ */
+struct sde_core_perf {
+	struct drm_device *dev;
+	struct dentry *debugfs_root;
+	struct mutex perf_lock;
+	struct sde_mdss_cfg *catalog;
+	struct sde_power_handle *phandle;
+	struct sde_power_client *pclient;
+	char *clk_name;
+	struct clk *core_clk;
+	u32 core_clk_rate;
+	u64 max_core_clk_rate;
+	struct sde_core_perf_tune perf_tune;
+	u32 enable_bw_release;
+};
+
+/**
+ * sde_core_perf_crtc_check - validate performance of the given crtc state
+ * @crtc: Pointer to crtc
+ * @state: Pointer to new crtc state
+ * return: zero if success, or error code otherwise
+ */
+int sde_core_perf_crtc_check(struct drm_crtc *crtc,
+		struct drm_crtc_state *state);
+
+/**
+ * sde_core_perf_crtc_update - update performance of the given crtc
+ * @crtc: Pointer to crtc
+ * @params_changed: true if crtc parameters are modified
+ * @stop_req: true if this is a stop request
+ */
+void sde_core_perf_crtc_update(struct drm_crtc *crtc,
+		int params_changed, bool stop_req);
+
+/**
+ * sde_core_perf_crtc_release_bw - release bandwidth of the given crtc
+ * @crtc: Pointer to crtc
+ */
+void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc);
+
+/**
+ * sde_core_perf_destroy - destroy the given core performance context
+ * @perf: Pointer to core performance context
+ */
+void sde_core_perf_destroy(struct sde_core_perf *perf);
+
+/**
+ * sde_core_perf_init - initialize the given core performance context
+ * @perf: Pointer to core performance context
+ * @dev: Pointer to drm device
+ * @catalog: Pointer to catalog
+ * @phandle: Pointer to power handle
+ * @pclient: Pointer to power client
+ * @clk_name: core clock name
+ * @debugfs_parent: Pointer to parent debugfs
+ */
+int sde_core_perf_init(struct sde_core_perf *perf,
+		struct drm_device *dev,
+		struct sde_mdss_cfg *catalog,
+		struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		char *clk_name,
+		struct dentry *debugfs_parent);
+
+#endif /* __SDE_CORE_PERF_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..05e6da14cec0cfd06f883fab7580d91fcd788ab3
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -0,0 +1,1693 @@
+/*
+ * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/sort.h>
+#include <linux/debugfs.h>
+#include <linux/ktime.h>
+#include <uapi/drm/sde_drm.h>
+#include <drm/drm_mode.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_flip_work.h>
+
+#include "sde_kms.h"
+#include "sde_hw_lm.h"
+#include "sde_hw_ctl.h"
+#include "sde_crtc.h"
+#include "sde_plane.h"
+#include "sde_color_processing.h"
+#include "sde_encoder.h"
+#include "sde_connector.h"
+#include "sde_power_handle.h"
+#include "sde_core_perf.h"
+
+/* default input fence timeout, in ms */
+#define SDE_CRTC_INPUT_FENCE_TIMEOUT    2000
+
+/*
+ * The default input fence timeout is 2 seconds while max allowed
+ * range is 10 seconds. Any value above 10 seconds adds glitches beyond
+ * tolerance limit.
+ */
+#define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
+
+/* layer mixer index on sde_crtc */
+#define LEFT_MIXER 0
+#define RIGHT_MIXER 1
+
+static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
+{
+	struct msm_drm_private *priv = crtc->dev->dev_private;
+	return to_sde_kms(priv->kms);
+}
+
+static void sde_crtc_destroy(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+
+	SDE_DEBUG("\n");
+
+	if (!crtc)
+		return;
+
+	if (sde_crtc->blob_info)
+		drm_property_unreference_blob(sde_crtc->blob_info);
+	msm_property_destroy(&sde_crtc->property_info);
+	sde_cp_crtc_destroy_properties(crtc);
+
+	debugfs_remove_recursive(sde_crtc->debugfs_root);
+	mutex_destroy(&sde_crtc->crtc_lock);
+	sde_fence_deinit(&sde_crtc->output_fence);
+
+	drm_crtc_cleanup(crtc);
+	kfree(sde_crtc);
+}
+
+static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
+		const struct drm_display_mode *mode,
+		struct drm_display_mode *adjusted_mode)
+{
+	SDE_DEBUG("\n");
+
+	if (msm_is_mode_seamless(adjusted_mode) &&
+		(!crtc->enabled || crtc->state->active_changed)) {
+		SDE_ERROR("crtc state prevents seamless transition\n");
+		return false;
+	}
+
+	return true;
+}
+
+static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
+	struct sde_plane_state *pstate, struct sde_format *format)
+{
+	uint32_t blend_op, fg_alpha, bg_alpha;
+	uint32_t blend_type;
+	struct sde_hw_mixer *lm = mixer->hw_lm;
+
+	/* default to opaque blending */
+	fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
+	bg_alpha = 0xFF - fg_alpha;
+	blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
+	blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
+
+	SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
+
+	switch (blend_type) {
+
+	case SDE_DRM_BLEND_OP_OPAQUE:
+		blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
+			SDE_BLEND_BG_ALPHA_BG_CONST;
+		break;
+
+	case SDE_DRM_BLEND_OP_PREMULTIPLIED:
+		if (format->alpha_enable) {
+			blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
+				SDE_BLEND_BG_ALPHA_FG_PIXEL;
+			if (fg_alpha != 0xff) {
+				bg_alpha = fg_alpha;
+				blend_op |= SDE_BLEND_BG_MOD_ALPHA |
+					SDE_BLEND_BG_INV_MOD_ALPHA;
+			} else {
+				blend_op |= SDE_BLEND_BG_INV_ALPHA;
+			}
+		}
+		break;
+
+	case SDE_DRM_BLEND_OP_COVERAGE:
+		if (format->alpha_enable) {
+			blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
+				SDE_BLEND_BG_ALPHA_FG_PIXEL;
+			if (fg_alpha != 0xff) {
+				bg_alpha = fg_alpha;
+				blend_op |= SDE_BLEND_FG_MOD_ALPHA |
+					SDE_BLEND_FG_INV_MOD_ALPHA |
+					SDE_BLEND_BG_MOD_ALPHA |
+					SDE_BLEND_BG_INV_MOD_ALPHA;
+			} else {
+				blend_op |= SDE_BLEND_BG_INV_ALPHA;
+			}
+		}
+		break;
+	default:
+		/* do nothing */
+		break;
+	}
+
+	lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
+						bg_alpha, blend_op);
+	SDE_DEBUG("format 0x%x, alpha_enable %u fg alpha:0x%x bg alpha:0x%x \"\
+		 blend_op:0x%x\n", format->base.pixel_format,
+		format->alpha_enable, fg_alpha, bg_alpha, blend_op);
+}
+
+static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
+	struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer)
+{
+	struct drm_plane *plane;
+
+	struct sde_plane_state *pstate = NULL;
+	struct sde_format *format;
+	struct sde_hw_ctl *ctl = mixer->hw_ctl;
+	struct sde_hw_stage_cfg *stage_cfg = &sde_crtc->stage_cfg;
+
+	u32 flush_mask = 0, crtc_split_width;
+	uint32_t lm_idx = LEFT_MIXER, idx;
+	bool bg_alpha_enable[CRTC_DUAL_MIXERS] = {false};
+	bool lm_right = false;
+	int left_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0};
+	int right_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0};
+
+	crtc_split_width = get_crtc_split_width(crtc);
+
+	drm_atomic_crtc_for_each_plane(plane, crtc) {
+
+		pstate = to_sde_plane_state(plane->state);
+
+		flush_mask = ctl->ops.get_bitmask_sspp(ctl,
+							sde_plane_pipe(plane));
+
+		/* always stage plane on either left or right lm */
+		if (plane->state->crtc_x >= crtc_split_width) {
+			lm_idx = RIGHT_MIXER;
+			idx = right_crtc_zpos_cnt[pstate->stage]++;
+		} else {
+			lm_idx = LEFT_MIXER;
+			idx = left_crtc_zpos_cnt[pstate->stage]++;
+		}
+
+		/* stage plane on right LM if it crosses the boundary */
+		lm_right = (lm_idx == LEFT_MIXER) &&
+		   (plane->state->crtc_x + plane->state->crtc_w >
+							crtc_split_width);
+
+		stage_cfg->stage[lm_idx][pstate->stage][idx] =
+							sde_plane_pipe(plane);
+		mixer[lm_idx].flush_mask |= flush_mask;
+
+		SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
+				crtc->base.id,
+				pstate->stage,
+				plane->base.id,
+				sde_plane_pipe(plane) - SSPP_VIG0,
+				plane->state->fb ?
+				plane->state->fb->base.id : -1);
+
+		format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
+
+		/* blend config update */
+		if (pstate->stage != SDE_STAGE_BASE) {
+			_sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate,
+								format);
+
+			if (bg_alpha_enable[lm_idx] && !format->alpha_enable)
+				mixer[lm_idx].mixer_op_mode = 0;
+			else
+				mixer[lm_idx].mixer_op_mode |=
+					1 << pstate->stage;
+		} else if (format->alpha_enable) {
+			bg_alpha_enable[lm_idx] = true;
+		}
+
+		if (lm_right) {
+			idx = right_crtc_zpos_cnt[pstate->stage]++;
+			stage_cfg->stage[RIGHT_MIXER][pstate->stage][idx] =
+							sde_plane_pipe(plane);
+			mixer[RIGHT_MIXER].flush_mask |= flush_mask;
+
+			/* blend config update */
+			if (pstate->stage != SDE_STAGE_BASE) {
+				_sde_crtc_setup_blend_cfg(mixer + RIGHT_MIXER,
+							pstate, format);
+
+				if (bg_alpha_enable[RIGHT_MIXER] &&
+						!format->alpha_enable)
+					mixer[RIGHT_MIXER].mixer_op_mode = 0;
+				else
+					mixer[RIGHT_MIXER].mixer_op_mode |=
+						1 << pstate->stage;
+			} else if (format->alpha_enable) {
+				bg_alpha_enable[RIGHT_MIXER] = true;
+			}
+		}
+	}
+}
+
+/**
+ * _sde_crtc_blend_setup - configure crtc mixers
+ * @crtc: Pointer to drm crtc structure
+ */
+static void _sde_crtc_blend_setup(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	struct sde_crtc_mixer *mixer = sde_crtc->mixers;
+	struct sde_hw_ctl *ctl;
+	struct sde_hw_mixer *lm;
+
+	int i;
+
+	SDE_DEBUG("%s\n", sde_crtc->name);
+
+	if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
+		SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
+		return;
+	}
+
+	for (i = 0; i < sde_crtc->num_mixers; i++) {
+		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
+			SDE_ERROR("invalid lm or ctl assigned to mixer\n");
+			return;
+		}
+		mixer[i].mixer_op_mode = 0;
+		mixer[i].flush_mask = 0;
+		if (mixer[i].hw_ctl->ops.clear_all_blendstages)
+			mixer[i].hw_ctl->ops.clear_all_blendstages(
+					mixer[i].hw_ctl);
+	}
+
+	/* initialize stage cfg */
+	memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
+
+	_sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer);
+
+	for (i = 0; i < sde_crtc->num_mixers; i++) {
+		ctl = mixer[i].hw_ctl;
+		lm = mixer[i].hw_lm;
+
+		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
+
+		mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl,
+			mixer[i].hw_lm->idx);
+
+		/* stage config flush mask */
+		ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
+
+		SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
+			mixer[i].hw_lm->idx - LM_0,
+			mixer[i].mixer_op_mode,
+			ctl->idx - CTL_0,
+			mixer[i].flush_mask);
+
+		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
+			&sde_crtc->stage_cfg, i);
+	}
+}
+
+void sde_crtc_prepare_commit(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_state)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+	struct drm_connector *conn;
+
+	if (!crtc || !crtc->state) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	cstate = to_sde_crtc_state(crtc->state);
+	SDE_EVT32(DRMID(crtc));
+
+	/* identify connectors attached to this crtc */
+	cstate->is_rt = false;
+	cstate->num_connectors = 0;
+
+	drm_for_each_connector(conn, crtc->dev)
+		if (conn->state && conn->state->crtc == crtc &&
+				cstate->num_connectors < MAX_CONNECTORS) {
+			cstate->connectors[cstate->num_connectors++] = conn;
+			sde_connector_prepare_fence(conn);
+
+			if (conn->connector_type != DRM_MODE_CONNECTOR_VIRTUAL)
+				cstate->is_rt = true;
+		}
+
+	if (cstate->num_connectors > 0 && cstate->connectors[0]->encoder)
+		cstate->intf_mode = sde_encoder_get_intf_mode(
+				cstate->connectors[0]->encoder);
+	else
+		cstate->intf_mode = INTF_MODE_NONE;
+
+	/* prepare main output fence */
+	sde_fence_prepare(&sde_crtc->output_fence);
+}
+
+bool sde_crtc_is_rt(struct drm_crtc *crtc)
+{
+	if (!crtc || !crtc->state) {
+		SDE_ERROR("invalid crtc or state\n");
+		return true;
+	}
+	return to_sde_crtc_state(crtc->state)->is_rt;
+}
+
+/* if file!=NULL, this is preclose potential cancel-flip path */
+static void _sde_crtc_complete_flip(struct drm_crtc *crtc,
+		struct drm_file *file)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	struct drm_device *dev = crtc->dev;
+	struct drm_pending_vblank_event *event;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	event = sde_crtc->event;
+	if (event) {
+		/* if regular vblank case (!file) or if cancel-flip from
+		 * preclose on file that requested flip, then send the
+		 * event:
+		 */
+		if (!file || (event->base.file_priv == file)) {
+			sde_crtc->event = NULL;
+			DRM_DEBUG_VBL("%s: send event: %pK\n",
+						sde_crtc->name, event);
+			SDE_EVT32(DRMID(crtc));
+			drm_crtc_send_vblank_event(crtc, event);
+		}
+	}
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+}
+
+static void sde_crtc_vblank_cb(void *data)
+{
+	struct drm_crtc *crtc = (struct drm_crtc *)data;
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+
+	/* keep statistics on vblank callback - with auto reset via debugfs */
+	if (ktime_equal(sde_crtc->vblank_cb_time, ktime_set(0, 0)))
+		sde_crtc->vblank_cb_time = ktime_get();
+	else
+		sde_crtc->vblank_cb_count++;
+
+	drm_crtc_handle_vblank(crtc);
+	DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
+	SDE_EVT32_IRQ(DRMID(crtc));
+}
+
+static void sde_crtc_frame_event_work(struct kthread_work *work)
+{
+	struct msm_drm_private *priv;
+	struct sde_crtc_frame_event *fevent;
+	struct drm_crtc *crtc;
+	struct sde_crtc *sde_crtc;
+	struct sde_kms *sde_kms;
+	unsigned long flags;
+
+	if (!work) {
+		SDE_ERROR("invalid work handle\n");
+		return;
+	}
+
+	fevent = container_of(work, struct sde_crtc_frame_event, work);
+	if (!fevent->crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	crtc = fevent->crtc;
+	sde_crtc = to_sde_crtc(crtc);
+
+	sde_kms = _sde_crtc_get_kms(crtc);
+	if (!sde_kms) {
+		SDE_ERROR("invalid kms handle\n");
+		return;
+	}
+	priv = sde_kms->dev->dev_private;
+
+	SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
+			ktime_to_ns(fevent->ts));
+
+	if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE ||
+			fevent->event == SDE_ENCODER_FRAME_EVENT_ERROR) {
+
+		if (atomic_read(&sde_crtc->frame_pending) < 1) {
+			/* this should not happen */
+			SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
+					crtc->base.id,
+					ktime_to_ns(fevent->ts),
+					atomic_read(&sde_crtc->frame_pending));
+			SDE_EVT32(DRMID(crtc), fevent->event, 0);
+		} else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
+			/* release bandwidth and other resources */
+			SDE_DEBUG("crtc%d ts:%lld last pending\n",
+					crtc->base.id,
+					ktime_to_ns(fevent->ts));
+			SDE_EVT32(DRMID(crtc), fevent->event, 1);
+			sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+					sde_kms->core_client, false);
+			sde_core_perf_crtc_release_bw(crtc);
+		} else {
+			SDE_EVT32(DRMID(crtc), fevent->event, 2);
+		}
+	} else {
+		SDE_ERROR("crtc%d ts:%lld unknown event %u\n", crtc->base.id,
+				ktime_to_ns(fevent->ts),
+				fevent->event);
+		SDE_EVT32(DRMID(crtc), fevent->event, 3);
+	}
+
+	spin_lock_irqsave(&sde_crtc->spin_lock, flags);
+	list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
+	spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+}
+
+static void sde_crtc_frame_event_cb(void *data, u32 event)
+{
+	struct drm_crtc *crtc = (struct drm_crtc *)data;
+	struct sde_crtc *sde_crtc;
+	struct msm_drm_private *priv;
+	struct sde_crtc_frame_event *fevent;
+	unsigned long flags;
+	int pipe_id;
+
+	if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
+		SDE_ERROR("invalid parameters\n");
+		return;
+	}
+	sde_crtc = to_sde_crtc(crtc);
+	priv = crtc->dev->dev_private;
+	pipe_id = drm_crtc_index(crtc);
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+
+	SDE_EVT32(DRMID(crtc), event);
+
+	spin_lock_irqsave(&sde_crtc->spin_lock, flags);
+	fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
+			struct sde_crtc_frame_event, list);
+	if (fevent)
+		list_del_init(&fevent->list);
+	spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+
+	if (!fevent) {
+		SDE_ERROR("crtc%d event %d overflow\n",
+				crtc->base.id, event);
+		SDE_EVT32(DRMID(crtc), event);
+		return;
+	}
+
+	fevent->event = event;
+	fevent->crtc = crtc;
+	fevent->ts = ktime_get();
+	queue_kthread_work(&priv->disp_thread[pipe_id].worker, &fevent->work);
+}
+
+void sde_crtc_complete_commit(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_state)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+	int i;
+
+	if (!crtc || !crtc->state) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	cstate = to_sde_crtc_state(crtc->state);
+	SDE_EVT32(DRMID(crtc));
+
+	/* signal output fence(s) at end of commit */
+	sde_fence_signal(&sde_crtc->output_fence, 0);
+
+	for (i = 0; i < cstate->num_connectors; ++i)
+		sde_connector_complete_commit(cstate->connectors[i]);
+}
+
+/**
+ * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
+ * @cstate: Pointer to sde crtc state
+ */
+static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
+{
+	if (!cstate) {
+		SDE_ERROR("invalid cstate\n");
+		return;
+	}
+	cstate->input_fence_timeout_ns =
+		sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
+	cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
+}
+
+/**
+ * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
+ * @crtc: Pointer to CRTC object
+ */
+static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
+{
+	struct drm_plane *plane = NULL;
+	uint32_t wait_ms = 1;
+	ktime_t kt_end, kt_wait;
+
+	SDE_DEBUG("\n");
+
+	if (!crtc || !crtc->state) {
+		SDE_ERROR("invalid crtc/state %pK\n", crtc);
+		return;
+	}
+
+	/* use monotonic timer to limit total fence wait time */
+	kt_end = ktime_add_ns(ktime_get(),
+		to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
+
+	/*
+	 * Wait for fences sequentially, as all of them need to be signalled
+	 * before we can proceed.
+	 *
+	 * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
+	 * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
+	 * that each plane can check its fence status and react appropriately
+	 * if its fence has timed out.
+	 */
+	drm_atomic_crtc_for_each_plane(plane, crtc) {
+		if (wait_ms) {
+			/* determine updated wait time */
+			kt_wait = ktime_sub(kt_end, ktime_get());
+			if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
+				wait_ms = ktime_to_ms(kt_wait);
+			else
+				wait_ms = 0;
+		}
+		sde_plane_wait_input_fence(plane, wait_ms);
+	}
+}
+
+static void _sde_crtc_setup_mixer_for_encoder(
+		struct drm_crtc *crtc,
+		struct drm_encoder *enc)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
+	struct sde_rm *rm = &sde_kms->rm;
+	struct sde_crtc_mixer *mixer;
+	struct sde_hw_ctl *last_valid_ctl = NULL;
+	int i;
+	struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter;
+
+	sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
+	sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
+	sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
+
+	/* Set up all the mixers and ctls reserved by this encoder */
+	for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
+		mixer = &sde_crtc->mixers[i];
+
+		if (!sde_rm_get_hw(rm, &lm_iter))
+			break;
+		mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
+
+		/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
+		if (!sde_rm_get_hw(rm, &ctl_iter)) {
+			SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
+					mixer->hw_lm->idx - LM_0);
+			mixer->hw_ctl = last_valid_ctl;
+		} else {
+			mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
+			last_valid_ctl = mixer->hw_ctl;
+		}
+
+		/* Shouldn't happen, mixers are always >= ctls */
+		if (!mixer->hw_ctl) {
+			SDE_ERROR("no valid ctls found for lm %d\n",
+					mixer->hw_lm->idx - LM_0);
+			return;
+		}
+
+		/* Dspp may be null */
+		(void) sde_rm_get_hw(rm, &dspp_iter);
+		mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
+
+		mixer->encoder = enc;
+
+		sde_crtc->num_mixers++;
+		SDE_DEBUG("setup mixer %d: lm %d\n",
+				i, mixer->hw_lm->idx - LM_0);
+		SDE_DEBUG("setup mixer %d: ctl %d\n",
+				i, mixer->hw_ctl->idx - CTL_0);
+	}
+}
+
+static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	struct drm_encoder *enc;
+
+	sde_crtc->num_mixers = 0;
+	memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
+
+	mutex_lock(&sde_crtc->crtc_lock);
+	/* Check for mixers on all encoders attached to this crtc */
+	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
+		if (enc->crtc != crtc)
+			continue;
+
+		_sde_crtc_setup_mixer_for_encoder(crtc, enc);
+	}
+	mutex_unlock(&sde_crtc->crtc_lock);
+}
+
+static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_state)
+{
+	struct sde_crtc *sde_crtc;
+	struct drm_device *dev;
+	unsigned long flags;
+	u32 i;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	if (!crtc->state->enable) {
+		SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
+				crtc->base.id, crtc->state->enable);
+		return;
+	}
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+
+	sde_crtc = to_sde_crtc(crtc);
+	dev = crtc->dev;
+
+	if (!sde_crtc->num_mixers)
+		_sde_crtc_setup_mixers(crtc);
+
+	if (sde_crtc->event) {
+		WARN_ON(sde_crtc->event);
+	} else {
+		spin_lock_irqsave(&dev->event_lock, flags);
+		sde_crtc->event = crtc->state->event;
+		spin_unlock_irqrestore(&dev->event_lock, flags);
+	}
+
+	/* Reset flush mask from previous commit */
+	for (i = 0; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
+		struct sde_hw_ctl *ctl = sde_crtc->mixers[i].hw_ctl;
+
+		if (ctl)
+			ctl->ops.clear_pending_flush(ctl);
+	}
+
+	/*
+	 * If no mixers have been allocated in sde_crtc_atomic_check(),
+	 * it means we are trying to flush a CRTC whose state is disabled:
+	 * nothing else needs to be done.
+	 */
+	if (unlikely(!sde_crtc->num_mixers))
+		return;
+
+	_sde_crtc_blend_setup(crtc);
+	sde_cp_crtc_apply_properties(crtc);
+
+	/*
+	 * PP_DONE irq is only used by command mode for now.
+	 * It is better to request pending before FLUSH and START trigger
+	 * to make sure no pp_done irq missed.
+	 * This is safe because no pp_done will happen before SW trigger
+	 * in command mode.
+	 */
+}
+
+static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_crtc_state)
+{
+	struct sde_crtc *sde_crtc;
+	struct drm_device *dev;
+	struct drm_plane *plane;
+	unsigned long flags;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	if (!crtc->state->enable) {
+		SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
+				crtc->base.id, crtc->state->enable);
+		return;
+	}
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+
+	sde_crtc = to_sde_crtc(crtc);
+
+	dev = crtc->dev;
+
+	if (sde_crtc->event) {
+		SDE_DEBUG("already received sde_crtc->event\n");
+	} else {
+		spin_lock_irqsave(&dev->event_lock, flags);
+		sde_crtc->event = crtc->state->event;
+		spin_unlock_irqrestore(&dev->event_lock, flags);
+	}
+
+	/*
+	 * If no mixers has been allocated in sde_crtc_atomic_check(),
+	 * it means we are trying to flush a CRTC whose state is disabled:
+	 * nothing else needs to be done.
+	 */
+	if (unlikely(!sde_crtc->num_mixers))
+		return;
+
+	/* wait for acquire fences before anything else is done */
+	_sde_crtc_wait_for_fences(crtc);
+
+	/* update performance setting before crtc kickoff */
+	sde_core_perf_crtc_update(crtc, 1, false);
+
+	/*
+	 * Final plane updates: Give each plane a chance to complete all
+	 *                      required writes/flushing before crtc's "flush
+	 *                      everything" call below.
+	 */
+	drm_atomic_crtc_for_each_plane(plane, crtc)
+		sde_plane_flush(plane);
+
+	/* Kickoff will be scheduled by outer layer */
+}
+
+/**
+ * sde_crtc_destroy_state - state destroy hook
+ * @crtc: drm CRTC
+ * @state: CRTC state object to release
+ */
+static void sde_crtc_destroy_state(struct drm_crtc *crtc,
+		struct drm_crtc_state *state)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+
+	if (!crtc || !state) {
+		SDE_ERROR("invalid argument(s)\n");
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	cstate = to_sde_crtc_state(state);
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+
+	__drm_atomic_helper_crtc_destroy_state(crtc, state);
+
+	/* destroy value helper */
+	msm_property_destroy_state(&sde_crtc->property_info, cstate,
+			cstate->property_values, cstate->property_blobs);
+}
+
+void sde_crtc_commit_kickoff(struct drm_crtc *crtc)
+{
+	struct drm_encoder *encoder;
+	struct drm_device *dev;
+	struct sde_crtc *sde_crtc;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid argument\n");
+		return;
+	}
+	dev = crtc->dev;
+	sde_crtc = to_sde_crtc(crtc);
+	sde_kms = _sde_crtc_get_kms(crtc);
+	priv = sde_kms->dev->dev_private;
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc != crtc)
+			continue;
+
+		/*
+		 * Encoder will flush/start now, unless it has a tx pending.
+		 * If so, it may delay and flush at an irq event (e.g. ppdone)
+		 */
+		sde_encoder_prepare_for_kickoff(encoder);
+	}
+
+	if (atomic_read(&sde_crtc->frame_pending) > 2) {
+		/* framework allows only 1 outstanding + current */
+		SDE_ERROR("crtc%d invalid frame pending\n",
+				crtc->base.id);
+		SDE_EVT32(DRMID(crtc), 0);
+		return;
+	} else if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
+		/* acquire bandwidth and other resources */
+		SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
+		SDE_EVT32(DRMID(crtc), 1);
+		sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+				sde_kms->core_client, true);
+	} else {
+		SDE_DEBUG("crtc%d commit\n", crtc->base.id);
+		SDE_EVT32(DRMID(crtc), 2);
+	}
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc != crtc)
+			continue;
+
+		sde_encoder_kickoff(encoder);
+	}
+}
+
+/**
+ * sde_crtc_duplicate_state - state duplicate hook
+ * @crtc: Pointer to drm crtc structure
+ * @Returns: Pointer to new drm_crtc_state structure
+ */
+static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate, *old_cstate;
+
+	if (!crtc || !crtc->state) {
+		SDE_ERROR("invalid argument(s)\n");
+		return NULL;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	old_cstate = to_sde_crtc_state(crtc->state);
+	cstate = msm_property_alloc_state(&sde_crtc->property_info);
+	if (!cstate) {
+		SDE_ERROR("failed to allocate state\n");
+		return NULL;
+	}
+
+	/* duplicate value helper */
+	msm_property_duplicate_state(&sde_crtc->property_info,
+			old_cstate, cstate,
+			cstate->property_values, cstate->property_blobs);
+
+	/* duplicate base helper */
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
+
+	return &cstate->base;
+}
+
+/**
+ * sde_crtc_reset - reset hook for CRTCs
+ * Resets the atomic state for @crtc by freeing the state pointer (which might
+ * be NULL, e.g. at driver load time) and allocating a new empty state object.
+ * @crtc: Pointer to drm crtc structure
+ */
+static void sde_crtc_reset(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	/* remove previous state, if present */
+	if (crtc->state) {
+		sde_crtc_destroy_state(crtc, crtc->state);
+		crtc->state = 0;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	cstate = msm_property_alloc_state(&sde_crtc->property_info);
+	if (!cstate) {
+		SDE_ERROR("failed to allocate state\n");
+		return;
+	}
+
+	/* reset value helper */
+	msm_property_reset_state(&sde_crtc->property_info, cstate,
+			cstate->property_values, cstate->property_blobs);
+
+	_sde_crtc_set_input_fence_timeout(cstate);
+
+	cstate->base.crtc = crtc;
+	crtc->state = &cstate->base;
+}
+
+static void sde_crtc_disable(struct drm_crtc *crtc)
+{
+	struct msm_drm_private *priv;
+	struct sde_crtc *sde_crtc;
+	struct drm_encoder *encoder;
+	struct sde_kms *sde_kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+	sde_crtc = to_sde_crtc(crtc);
+	sde_kms = _sde_crtc_get_kms(crtc);
+	priv = sde_kms->dev->dev_private;
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+
+	mutex_lock(&sde_crtc->crtc_lock);
+	SDE_EVT32(DRMID(crtc));
+
+	if (atomic_read(&sde_crtc->vblank_refcount)) {
+		SDE_ERROR("crtc%d invalid vblank refcount\n",
+				crtc->base.id);
+		SDE_EVT32(DRMID(crtc));
+		drm_for_each_encoder(encoder, crtc->dev) {
+			if (encoder->crtc != crtc)
+				continue;
+			sde_encoder_register_vblank_callback(encoder, NULL,
+						NULL);
+		}
+		atomic_set(&sde_crtc->vblank_refcount, 0);
+	}
+
+	if (atomic_read(&sde_crtc->frame_pending)) {
+		/* release bandwidth and other resources */
+		SDE_ERROR("crtc%d invalid frame pending\n",
+				crtc->base.id);
+		SDE_EVT32(DRMID(crtc));
+		sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+				sde_kms->core_client, false);
+		sde_core_perf_crtc_release_bw(crtc);
+		atomic_set(&sde_crtc->frame_pending, 0);
+	}
+
+	sde_core_perf_crtc_update(crtc, 0, true);
+
+	drm_for_each_encoder(encoder, crtc->dev) {
+		if (encoder->crtc != crtc)
+			continue;
+		sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
+	}
+
+	memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
+	sde_crtc->num_mixers = 0;
+	mutex_unlock(&sde_crtc->crtc_lock);
+}
+
+static void sde_crtc_enable(struct drm_crtc *crtc)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_mixer *mixer;
+	struct sde_hw_mixer *lm;
+	struct drm_display_mode *mode;
+	struct sde_hw_mixer_cfg cfg;
+	struct drm_encoder *encoder;
+	int i;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	SDE_DEBUG("crtc%d\n", crtc->base.id);
+	SDE_EVT32(DRMID(crtc));
+
+	sde_crtc = to_sde_crtc(crtc);
+	mixer = sde_crtc->mixers;
+
+	if (WARN_ON(!crtc->state))
+		return;
+
+	mode = &crtc->state->adjusted_mode;
+
+	drm_mode_debug_printmodeline(mode);
+
+	drm_for_each_encoder(encoder, crtc->dev) {
+		if (encoder->crtc != crtc)
+			continue;
+		sde_encoder_register_frame_event_callback(encoder,
+				sde_crtc_frame_event_cb, (void *)crtc);
+	}
+
+	for (i = 0; i < sde_crtc->num_mixers; i++) {
+		lm = mixer[i].hw_lm;
+		cfg.out_width = sde_crtc_mixer_width(sde_crtc, mode);
+		cfg.out_height = mode->vdisplay;
+		cfg.right_mixer = (i == 0) ? false : true;
+		cfg.flags = 0;
+		lm->ops.setup_mixer_out(lm, &cfg);
+	}
+}
+
+struct plane_state {
+	struct sde_plane_state *sde_pstate;
+	struct drm_plane_state *drm_pstate;
+
+	int stage;
+};
+
+static int pstate_cmp(const void *a, const void *b)
+{
+	struct plane_state *pa = (struct plane_state *)a;
+	struct plane_state *pb = (struct plane_state *)b;
+	int rc = 0;
+	int pa_zpos, pb_zpos;
+
+	pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
+	pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
+
+	if (pa_zpos != pb_zpos)
+		rc = pa_zpos - pb_zpos;
+	else
+		rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
+
+	return rc;
+}
+
+static int sde_crtc_atomic_check(struct drm_crtc *crtc,
+		struct drm_crtc_state *state)
+{
+	struct sde_crtc *sde_crtc;
+	struct plane_state pstates[SDE_STAGE_MAX * 2];
+
+	struct drm_plane_state *pstate;
+	struct drm_plane *plane;
+	struct drm_display_mode *mode;
+
+	int cnt = 0, rc = 0, mixer_width, i, z_pos;
+	int left_crtc_zpos_cnt[SDE_STAGE_MAX] = {0};
+	int right_crtc_zpos_cnt[SDE_STAGE_MAX] = {0};
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return -EINVAL;
+	}
+
+	if (!state->enable || !state->active) {
+		SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
+				crtc->base.id, state->enable, state->active);
+		return 0;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	mode = &state->adjusted_mode;
+	SDE_DEBUG("%s: check", sde_crtc->name);
+
+	mixer_width = sde_crtc_mixer_width(sde_crtc, mode);
+
+	 /* get plane state for all drm planes associated with crtc state */
+	drm_atomic_crtc_state_for_each_plane(plane, state) {
+		pstate = drm_atomic_get_plane_state(state->state, plane);
+		if (IS_ERR_OR_NULL(pstate)) {
+			rc = PTR_ERR(pstate);
+			SDE_ERROR("%s: failed to get plane%d state, %d\n",
+					sde_crtc->name, plane->base.id, rc);
+			goto end;
+		}
+		if (cnt >= ARRAY_SIZE(pstates))
+			continue;
+
+		pstates[cnt].sde_pstate = to_sde_plane_state(pstate);
+		pstates[cnt].drm_pstate = pstate;
+		pstates[cnt].stage = sde_plane_get_property(
+				pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
+		cnt++;
+
+		if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
+				mode->vdisplay) ||
+		    CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
+				mode->hdisplay)) {
+			SDE_ERROR("invalid vertical/horizontal destination\n");
+			SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
+				pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
+				pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
+			rc = -E2BIG;
+			goto end;
+		}
+	}
+
+	if (!sde_is_custom_client()) {
+		int stage_old = pstates[0].stage;
+
+		/* assign mixer stages based on sorted zpos property */
+		sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
+		z_pos = 0;
+		for (i = 0; i < cnt; i++) {
+			if (stage_old != pstates[i].stage)
+				++z_pos;
+			stage_old = pstates[i].stage;
+			pstates[i].stage = z_pos;
+		}
+	}
+
+	for (i = 0; i < cnt; i++) {
+		z_pos = pstates[i].stage;
+
+		/* verify z_pos setting before using it */
+		if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
+			SDE_ERROR("> %d plane stages assigned\n",
+					SDE_STAGE_MAX - SDE_STAGE_0);
+			rc = -EINVAL;
+			goto end;
+		} else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
+			if (left_crtc_zpos_cnt[z_pos] == 2) {
+				SDE_ERROR("> 2 plane @ stage%d on left\n",
+					z_pos);
+				rc = -EINVAL;
+				goto end;
+			}
+			left_crtc_zpos_cnt[z_pos]++;
+		} else {
+			if (right_crtc_zpos_cnt[z_pos] == 2) {
+				SDE_ERROR("> 2 plane @ stage%d on right\n",
+					z_pos);
+				rc = -EINVAL;
+				goto end;
+			}
+			right_crtc_zpos_cnt[z_pos]++;
+		}
+		pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
+		SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
+	}
+
+	rc = sde_core_perf_crtc_check(crtc, state);
+	if (rc) {
+		SDE_ERROR("crtc%d failed performance check %d\n",
+				crtc->base.id, rc);
+		goto end;
+	}
+
+end:
+	return rc;
+}
+
+int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	struct drm_encoder *encoder;
+	struct drm_device *dev = crtc->dev;
+
+	if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) {
+		SDE_DEBUG("crtc%d vblank enable\n", crtc->base.id);
+	} else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) {
+		SDE_ERROR("crtc%d invalid vblank disable\n", crtc->base.id);
+		return -EINVAL;
+	} else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) {
+		SDE_DEBUG("crtc%d vblank disable\n", crtc->base.id);
+	} else {
+		SDE_DEBUG("crtc%d vblank %s refcount:%d\n",
+				crtc->base.id,
+				en ? "enable" : "disable",
+				atomic_read(&sde_crtc->vblank_refcount));
+		return 0;
+	}
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc != crtc)
+			continue;
+
+		SDE_EVT32(DRMID(crtc), en);
+
+		if (en)
+			sde_encoder_register_vblank_callback(encoder,
+					sde_crtc_vblank_cb, (void *)crtc);
+		else
+			sde_encoder_register_vblank_callback(encoder, NULL,
+					NULL);
+	}
+
+	return 0;
+}
+
+void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
+{
+	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+
+	SDE_DEBUG("%s: cancel: %p\n", sde_crtc->name, file);
+	_sde_crtc_complete_flip(crtc, file);
+}
+
+/**
+ * sde_crtc_install_properties - install all drm properties for crtc
+ * @crtc: Pointer to drm crtc structure
+ */
+static void sde_crtc_install_properties(struct drm_crtc *crtc,
+				struct sde_mdss_cfg *catalog)
+{
+	struct sde_crtc *sde_crtc;
+	struct drm_device *dev;
+	struct sde_kms_info *info;
+	struct sde_kms *sde_kms;
+
+	SDE_DEBUG("\n");
+
+	if (!crtc || !catalog) {
+		SDE_ERROR("invalid crtc or catalog\n");
+		return;
+	}
+
+	sde_crtc = to_sde_crtc(crtc);
+	dev = crtc->dev;
+	sde_kms = _sde_crtc_get_kms(crtc);
+
+	info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
+	if (!info) {
+		SDE_ERROR("failed to allocate info memory\n");
+		return;
+	}
+
+	/* range properties */
+	msm_property_install_range(&sde_crtc->property_info,
+		"input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT,
+		SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT);
+
+	msm_property_install_range(&sde_crtc->property_info, "output_fence",
+			0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE);
+
+	msm_property_install_range(&sde_crtc->property_info,
+			"output_fence_offset", 0x0, 0, 1, 0,
+			CRTC_PROP_OUTPUT_FENCE_OFFSET);
+
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_clk", 0x0, 0, U64_MAX,
+			sde_kms->perf.max_core_clk_rate,
+			CRTC_PROP_CORE_CLK);
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_ab", 0x0, 0, U64_MAX,
+			SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+			CRTC_PROP_CORE_AB);
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_ib", 0x0, 0, U64_MAX,
+			SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA,
+			CRTC_PROP_CORE_IB);
+
+	msm_property_install_blob(&sde_crtc->property_info, "capabilities",
+		DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
+	sde_kms_info_reset(info);
+
+	sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
+	sde_kms_info_add_keyint(info, "max_linewidth",
+			catalog->max_mixer_width);
+	sde_kms_info_add_keyint(info, "max_blendstages",
+			catalog->max_mixer_blendstages);
+	if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
+		sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
+	if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
+		sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
+	sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
+	if (catalog->perf.max_bw_low)
+		sde_kms_info_add_keyint(info, "max_bandwidth_low",
+				catalog->perf.max_bw_low);
+	if (catalog->perf.max_bw_high)
+		sde_kms_info_add_keyint(info, "max_bandwidth_high",
+				catalog->perf.max_bw_high);
+	if (sde_kms->perf.max_core_clk_rate)
+		sde_kms_info_add_keyint(info, "max_mdp_clk",
+				sde_kms->perf.max_core_clk_rate);
+	msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
+			info->data, info->len, CRTC_PROP_INFO);
+
+	kfree(info);
+}
+
+/**
+ * sde_crtc_atomic_set_property - atomically set a crtc drm property
+ * @crtc: Pointer to drm crtc structure
+ * @state: Pointer to drm crtc state structure
+ * @property: Pointer to targeted drm property
+ * @val: Updated property value
+ * @Returns: Zero on success
+ */
+static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
+		struct drm_crtc_state *state,
+		struct drm_property *property,
+		uint64_t val)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+	int idx, ret = -EINVAL;
+
+	if (!crtc || !state || !property) {
+		SDE_ERROR("invalid argument(s)\n");
+	} else {
+		sde_crtc = to_sde_crtc(crtc);
+		cstate = to_sde_crtc_state(state);
+		ret = msm_property_atomic_set(&sde_crtc->property_info,
+				cstate->property_values, cstate->property_blobs,
+				property, val);
+		if (!ret) {
+			idx = msm_property_index(&sde_crtc->property_info,
+					property);
+			if (idx == CRTC_PROP_INPUT_FENCE_TIMEOUT)
+				_sde_crtc_set_input_fence_timeout(cstate);
+		} else {
+			ret = sde_cp_crtc_set_property(crtc,
+					property, val);
+		}
+		if (ret)
+			DRM_ERROR("failed to set the property\n");
+	}
+
+	return ret;
+}
+
+/**
+ * sde_crtc_set_property - set a crtc drm property
+ * @crtc: Pointer to drm crtc structure
+ * @property: Pointer to targeted drm property
+ * @val: Updated property value
+ * @Returns: Zero on success
+ */
+static int sde_crtc_set_property(struct drm_crtc *crtc,
+		struct drm_property *property, uint64_t val)
+{
+	SDE_DEBUG("\n");
+
+	return sde_crtc_atomic_set_property(crtc, crtc->state, property, val);
+}
+
+/**
+ * sde_crtc_atomic_get_property - retrieve a crtc drm property
+ * @crtc: Pointer to drm crtc structure
+ * @state: Pointer to drm crtc state structure
+ * @property: Pointer to targeted drm property
+ * @val: Pointer to variable for receiving property value
+ * @Returns: Zero on success
+ */
+static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
+		const struct drm_crtc_state *state,
+		struct drm_property *property,
+		uint64_t *val)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *cstate;
+	int i, ret = -EINVAL;
+
+	if (!crtc || !state) {
+		SDE_ERROR("invalid argument(s)\n");
+	} else {
+		sde_crtc = to_sde_crtc(crtc);
+		cstate = to_sde_crtc_state(state);
+		i = msm_property_index(&sde_crtc->property_info, property);
+		if (i == CRTC_PROP_OUTPUT_FENCE) {
+			int offset = sde_crtc_get_property(cstate,
+					CRTC_PROP_OUTPUT_FENCE_OFFSET);
+
+			ret = sde_fence_create(
+					&sde_crtc->output_fence, val, offset);
+			if (ret)
+				SDE_ERROR("fence create failed\n");
+		} else {
+			ret = msm_property_atomic_get(&sde_crtc->property_info,
+					cstate->property_values,
+					cstate->property_blobs, property, val);
+			if (ret)
+				ret = sde_cp_crtc_get_property(crtc,
+					property, val);
+		}
+		if (ret)
+			DRM_ERROR("get property failed\n");
+	}
+	return ret;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int _sde_debugfs_status_show(struct seq_file *s, void *data)
+{
+	struct sde_crtc *sde_crtc;
+	struct sde_plane_state *pstate = NULL;
+	struct sde_crtc_mixer *m;
+
+	struct drm_crtc *crtc;
+	struct drm_plane *plane;
+	struct drm_display_mode *mode;
+	struct drm_framebuffer *fb;
+	struct drm_plane_state *state;
+
+	int i, out_width;
+
+	if (!s || !s->private)
+		return -EINVAL;
+
+	sde_crtc = s->private;
+	crtc = &sde_crtc->base;
+
+	mutex_lock(&sde_crtc->crtc_lock);
+	mode = &crtc->state->adjusted_mode;
+	out_width = sde_crtc_mixer_width(sde_crtc, mode);
+
+	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
+				mode->hdisplay, mode->vdisplay);
+
+	seq_puts(s, "\n");
+
+	for (i = 0; i < sde_crtc->num_mixers; ++i) {
+		m = &sde_crtc->mixers[i];
+		if (!m->hw_lm)
+			seq_printf(s, "\tmixer[%d] has no lm\n", i);
+		else if (!m->hw_ctl)
+			seq_printf(s, "\tmixer[%d] has no ctl\n", i);
+		else
+			seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
+				m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
+				out_width, mode->vdisplay);
+	}
+
+	seq_puts(s, "\n");
+
+	drm_atomic_crtc_for_each_plane(plane, crtc) {
+		pstate = to_sde_plane_state(plane->state);
+		state = plane->state;
+
+		if (!pstate || !state)
+			continue;
+
+		seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
+			pstate->stage);
+
+		if (plane->state->fb) {
+			fb = plane->state->fb;
+
+			seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u bpp:%d\n",
+				fb->base.id, (char *) &fb->pixel_format,
+				fb->width, fb->height, fb->bits_per_pixel);
+
+			seq_puts(s, "\t");
+			for (i = 0; i < ARRAY_SIZE(fb->modifier); i++)
+				seq_printf(s, "modifier[%d]:%8llu ", i,
+							fb->modifier[i]);
+			seq_puts(s, "\n");
+
+			seq_puts(s, "\t");
+			for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
+				seq_printf(s, "pitches[%d]:%8u ", i,
+							fb->pitches[i]);
+			seq_puts(s, "\n");
+
+			seq_puts(s, "\t");
+			for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
+				seq_printf(s, "offsets[%d]:%8u ", i,
+							fb->offsets[i]);
+			seq_puts(s, "\n");
+		}
+
+		seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
+			state->src_x, state->src_y, state->src_w, state->src_h);
+
+		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
+			state->crtc_x, state->crtc_y, state->crtc_w,
+			state->crtc_h);
+		seq_puts(s, "\n");
+	}
+
+	if (sde_crtc->vblank_cb_count) {
+		ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
+		s64 diff_ms = ktime_to_ms(diff);
+		s64 fps = diff_ms ? DIV_ROUND_CLOSEST(
+				sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
+
+		seq_printf(s,
+			"vblank fps:%lld count:%u total:%llums\n",
+				fps,
+				sde_crtc->vblank_cb_count,
+				ktime_to_ms(diff));
+
+		/* reset time & count for next measurement */
+		sde_crtc->vblank_cb_count = 0;
+		sde_crtc->vblank_cb_time = ktime_set(0, 0);
+	}
+
+	seq_printf(s, "vblank_refcount:%d\n",
+			atomic_read(&sde_crtc->vblank_refcount));
+
+	mutex_unlock(&sde_crtc->crtc_lock);
+
+	return 0;
+}
+
+static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, _sde_debugfs_status_show, inode->i_private);
+}
+#endif
+
+static void sde_crtc_suspend(struct drm_crtc *crtc)
+{
+	sde_cp_crtc_suspend(crtc);
+}
+
+static void sde_crtc_resume(struct drm_crtc *crtc)
+{
+	sde_cp_crtc_resume(crtc);
+}
+
+static const struct drm_crtc_funcs sde_crtc_funcs = {
+	.set_config = drm_atomic_helper_set_config,
+	.destroy = sde_crtc_destroy,
+	.page_flip = drm_atomic_helper_page_flip,
+	.set_property = sde_crtc_set_property,
+	.atomic_set_property = sde_crtc_atomic_set_property,
+	.atomic_get_property = sde_crtc_atomic_get_property,
+	.reset = sde_crtc_reset,
+	.atomic_duplicate_state = sde_crtc_duplicate_state,
+	.atomic_destroy_state = sde_crtc_destroy_state,
+	.save = sde_crtc_suspend,
+	.restore = sde_crtc_resume,
+};
+
+static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
+	.mode_fixup = sde_crtc_mode_fixup,
+	.disable = sde_crtc_disable,
+	.enable = sde_crtc_enable,
+	.atomic_check = sde_crtc_atomic_check,
+	.atomic_begin = sde_crtc_atomic_begin,
+	.atomic_flush = sde_crtc_atomic_flush,
+};
+
+#ifdef CONFIG_DEBUG_FS
+#define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix)				\
+static int __prefix ## _open(struct inode *inode, struct file *file)	\
+{									\
+	return single_open(file, __prefix ## _show, inode->i_private);	\
+}									\
+static const struct file_operations __prefix ## _fops = {		\
+	.owner = THIS_MODULE,						\
+	.open = __prefix ## _open,					\
+	.release = single_release,					\
+	.read = seq_read,						\
+	.llseek = seq_lseek,						\
+}
+
+static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
+{
+	struct drm_crtc *crtc = (struct drm_crtc *) s->private;
+	struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
+
+	seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
+	seq_printf(s, "is_rt: %d\n", cstate->is_rt);
+	seq_printf(s, "intf_mode: %d\n", cstate->intf_mode);
+	seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
+	seq_printf(s, "core_clk_rate: %u\n", cstate->cur_perf.core_clk_rate);
+	seq_printf(s, "max_per_pipe_ib: %llu\n",
+			cstate->cur_perf.max_per_pipe_ib);
+
+	return 0;
+}
+DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
+
+static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
+		struct sde_kms *sde_kms)
+{
+	static const struct file_operations debugfs_status_fops = {
+		.open =		_sde_debugfs_status_open,
+		.read =		seq_read,
+		.llseek =	seq_lseek,
+		.release =	single_release,
+	};
+
+	if (sde_crtc && sde_kms) {
+		sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
+				sde_debugfs_get_root(sde_kms));
+		if (sde_crtc->debugfs_root) {
+			/* don't error check these */
+			debugfs_create_file("status", S_IRUGO,
+					sde_crtc->debugfs_root,
+					sde_crtc, &debugfs_status_fops);
+			debugfs_create_file("state", S_IRUGO | S_IWUSR,
+					sde_crtc->debugfs_root,
+					&sde_crtc->base,
+					&sde_crtc_debugfs_state_fops);
+		}
+	}
+}
+#else
+static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
+		struct sde_kms *sde_kms)
+{
+}
+#endif
+
+/* initialize crtc */
+struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+{
+	struct drm_crtc *crtc = NULL;
+	struct sde_crtc *sde_crtc = NULL;
+	struct msm_drm_private *priv = NULL;
+	struct sde_kms *kms = NULL;
+	int i;
+
+	priv = dev->dev_private;
+	kms = to_sde_kms(priv->kms);
+
+	sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
+	if (!sde_crtc)
+		return ERR_PTR(-ENOMEM);
+
+	crtc = &sde_crtc->base;
+	crtc->dev = dev;
+	atomic_set(&sde_crtc->vblank_refcount, 0);
+
+	spin_lock_init(&sde_crtc->spin_lock);
+	atomic_set(&sde_crtc->frame_pending, 0);
+
+	INIT_LIST_HEAD(&sde_crtc->frame_event_list);
+	for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
+		INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
+		list_add(&sde_crtc->frame_events[i].list,
+				&sde_crtc->frame_event_list);
+		init_kthread_work(&sde_crtc->frame_events[i].work,
+				sde_crtc_frame_event_work);
+	}
+
+	drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs);
+
+	drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
+	plane->crtc = crtc;
+
+	/* save user friendly CRTC name for later */
+	snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
+
+	/* initialize output fence support */
+	mutex_init(&sde_crtc->crtc_lock);
+	sde_fence_init(&sde_crtc->output_fence, sde_crtc->name, crtc->base.id);
+
+	/* initialize debugfs support */
+	_sde_crtc_init_debugfs(sde_crtc, kms);
+
+	/* create CRTC properties */
+	msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
+			priv->crtc_property, sde_crtc->property_data,
+			CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
+			sizeof(struct sde_crtc_state));
+
+	sde_crtc_install_properties(crtc, kms->catalog);
+
+	/* Install color processing properties */
+	sde_cp_crtc_init(crtc);
+	sde_cp_crtc_install_properties(crtc);
+
+	SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
+	return crtc;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..25a93e882e6df0ea24175986e5a6a57ed601e627
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDE_CRTC_H_
+#define _SDE_CRTC_H_
+
+#include "drm_crtc.h"
+#include "msm_prop.h"
+#include "sde_fence.h"
+#include "sde_kms.h"
+#include "sde_core_perf.h"
+
+#define SDE_CRTC_NAME_SIZE	12
+
+/* define the maximum number of in-flight frame events */
+#define SDE_CRTC_FRAME_EVENT_SIZE	2
+
+/**
+ * struct sde_crtc_mixer: stores the map for each virtual pipeline in the CRTC
+ * @hw_lm:	LM HW Driver context
+ * @hw_ctl:	CTL Path HW driver context
+ * @hw_dspp:	DSPP HW driver context
+ * @encoder:	Encoder attached to this lm & ctl
+ * @mixer_op_mode: mixer blending operation mode
+ * @flush_mask:	mixer flush mask for ctl, mixer and pipe
+ */
+struct sde_crtc_mixer {
+	struct sde_hw_mixer *hw_lm;
+	struct sde_hw_ctl *hw_ctl;
+	struct sde_hw_dspp  *hw_dspp;
+	struct drm_encoder *encoder;
+	u32 mixer_op_mode;
+	u32 flush_mask;
+};
+
+/**
+ * struct sde_crtc_frame_event: stores crtc frame event for crtc processing
+ * @work:	base work structure
+ * @crtc:	Pointer to crtc handling this event
+ * @list:	event list
+ * @ts:		timestamp at queue entry
+ * @event:	event identifier
+ */
+struct sde_crtc_frame_event {
+	struct kthread_work work;
+	struct drm_crtc *crtc;
+	struct list_head list;
+	ktime_t ts;
+	u32 event;
+};
+
+/**
+ * struct sde_crtc - virtualized CRTC data structure
+ * @base          : Base drm crtc structure
+ * @name          : ASCII description of this crtc
+ * @num_ctls      : Number of ctl paths in use
+ * @num_mixers    : Number of mixers in use
+ * @mixer         : List of active mixers
+ * @event         : Pointer to last received drm vblank event. If there is a
+ *                  pending vblank event, this will be non-null.
+ * @vsync_count   : Running count of received vsync events
+ * @drm_requested_vblank : Whether vblanks have been enabled in the encoder
+ * @property_info : Opaque structure for generic property support
+ * @property_defaults : Array of default values for generic property support
+ * @stage_cfg     : H/w mixer stage configuration
+ * @debugfs_root  : Parent of debugfs node
+ * @vblank_cb_count : count of vblank callback since last reset
+ * @vblank_cb_time  : ktime at vblank count reset
+ * @vblank_refcount : reference count for vblank enable request
+ * @feature_list  : list of color processing features supported on a crtc
+ * @active_list   : list of color processing features are active
+ * @dirty_list    : list of color processing features are dirty
+ * @crtc_lock     : crtc lock around create, destroy and access.
+ * @frame_pending : Whether or not an update is pending
+ * @frame_events  : static allocation of in-flight frame events
+ * @frame_event_list : available frame event list
+ * @spin_lock     : spin lock for frame event, transaction status, etc...
+ */
+struct sde_crtc {
+	struct drm_crtc base;
+	char name[SDE_CRTC_NAME_SIZE];
+
+	/* HW Resources reserved for the crtc */
+	u32 num_ctls;
+	u32 num_mixers;
+	struct sde_crtc_mixer mixers[CRTC_DUAL_MIXERS];
+
+	struct drm_pending_vblank_event *event;
+	u32 vsync_count;
+
+	struct msm_property_info property_info;
+	struct msm_property_data property_data[CRTC_PROP_COUNT];
+	struct drm_property_blob *blob_info;
+
+	/* output fence support */
+	struct sde_fence output_fence;
+
+	struct sde_hw_stage_cfg stage_cfg;
+	struct dentry *debugfs_root;
+
+	u32 vblank_cb_count;
+	ktime_t vblank_cb_time;
+	atomic_t vblank_refcount;
+
+	struct list_head feature_list;
+	struct list_head active_list;
+	struct list_head dirty_list;
+
+	struct mutex crtc_lock;
+
+	atomic_t frame_pending;
+	struct sde_crtc_frame_event frame_events[SDE_CRTC_FRAME_EVENT_SIZE];
+	struct list_head frame_event_list;
+	spinlock_t spin_lock;
+};
+
+#define to_sde_crtc(x) container_of(x, struct sde_crtc, base)
+
+/**
+ * struct sde_crtc_state - sde container for atomic crtc state
+ * @base: Base drm crtc state structure
+ * @connectors    : Currently associated drm connectors
+ * @num_connectors: Number of associated drm connectors
+ * @is_rt         : Whether or not the current commit contains RT connectors
+ * @intf_mode     : Interface mode of the primary connector
+ * @property_values: Current crtc property values
+ * @input_fence_timeout_ns : Cached input fence timeout, in ns
+ * @property_blobs: Reference pointers for blob properties
+ */
+struct sde_crtc_state {
+	struct drm_crtc_state base;
+
+	struct drm_connector *connectors[MAX_CONNECTORS];
+	int num_connectors;
+	bool is_rt;
+	enum sde_intf_mode intf_mode;
+
+	uint64_t property_values[CRTC_PROP_COUNT];
+	uint64_t input_fence_timeout_ns;
+	struct drm_property_blob *property_blobs[CRTC_PROP_COUNT];
+
+	struct sde_core_perf_params cur_perf;
+	struct sde_core_perf_params new_perf;
+};
+
+#define to_sde_crtc_state(x) \
+	container_of(x, struct sde_crtc_state, base)
+
+/**
+ * sde_crtc_get_property - query integer value of crtc property
+ * @S: Pointer to crtc state
+ * @X: Property index, from enum msm_mdp_crtc_property
+ * Returns: Integer value of requested property
+ */
+#define sde_crtc_get_property(S, X) \
+	((S) && ((X) < CRTC_PROP_COUNT) ? ((S)->property_values[(X)]) : 0)
+
+static inline int sde_crtc_mixer_width(struct sde_crtc *sde_crtc,
+	struct drm_display_mode *mode)
+{
+	if (!sde_crtc || !mode)
+		return 0;
+
+	return  sde_crtc->num_mixers == CRTC_DUAL_MIXERS ?
+		mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay;
+}
+
+static inline uint32_t get_crtc_split_width(struct drm_crtc *crtc)
+{
+	struct drm_display_mode *mode;
+	struct sde_crtc *sde_crtc;
+
+	if (!crtc)
+		return 0;
+
+	sde_crtc = to_sde_crtc(crtc);
+	mode = &crtc->state->adjusted_mode;
+	return sde_crtc_mixer_width(sde_crtc, mode);
+}
+
+/**
+ * sde_crtc_vblank - enable or disable vblanks for this crtc
+ * @crtc: Pointer to drm crtc object
+ * @en: true to enable vblanks, false to disable
+ */
+int sde_crtc_vblank(struct drm_crtc *crtc, bool en);
+
+/**
+ * sde_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
+ * @crtc: Pointer to drm crtc object
+ */
+void sde_crtc_commit_kickoff(struct drm_crtc *crtc);
+
+/**
+ * sde_crtc_prepare_commit - callback to prepare for output fences
+ * @crtc: Pointer to drm crtc object
+ * @old_state: Pointer to drm crtc old state object
+ */
+void sde_crtc_prepare_commit(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_state);
+
+/**
+ * sde_crtc_complete_commit - callback signalling completion of current commit
+ * @crtc: Pointer to drm crtc object
+ * @old_state: Pointer to drm crtc old state object
+ */
+void sde_crtc_complete_commit(struct drm_crtc *crtc,
+		struct drm_crtc_state *old_state);
+
+/**
+ * sde_crtc_init - create a new crtc object
+ * @dev: sde device
+ * @plane: base plane
+ * @Return: new crtc object or error
+ */
+struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane);
+
+/**
+ * sde_crtc_cancel_pending_flip - complete flip for clients on lastclose
+ * @crtc: Pointer to drm crtc object
+ * @file: client to cancel's file handle
+ */
+void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
+
+/**
+ * sde_crtc_is_rt - query whether real time connectors are present on the crtc
+ * @crtc: Pointer to drm crtc structure
+ * Returns: True if a connector is present with real time constraints
+ */
+bool sde_crtc_is_rt(struct drm_crtc *crtc);
+
+/**
+ * sde_crtc_get_intf_mode - get interface mode of the given crtc
+ * @crtc: Pointert to crtc
+ */
+static inline enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc)
+{
+	struct sde_crtc_state *cstate =
+			crtc ? to_sde_crtc_state(crtc->state) : NULL;
+
+	return cstate ? cstate->intf_mode : INTF_MODE_NONE;
+}
+
+/**
+ * sde_core_perf_crtc_is_wb - check if writeback is primary output of this crtc
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_wb(struct drm_crtc *crtc)
+{
+	struct sde_crtc_state *cstate =
+			crtc ? to_sde_crtc_state(crtc->state) : NULL;
+
+	return cstate ? (cstate->intf_mode == INTF_MODE_WB_LINE) : false;
+}
+
+/**
+ * sde_crtc_is_nrt - check if primary output of this crtc is non-realtime client
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_nrt(struct drm_crtc *crtc)
+{
+	return sde_crtc_is_wb(crtc);
+}
+
+/**
+ * sde_crtc_is_enabled - check if sde crtc is enabled or not
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_enabled(struct drm_crtc *crtc)
+{
+	return crtc ? crtc->enabled : false;
+}
+
+#endif /* _SDE_CRTC_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
new file mode 100644
index 0000000000000000000000000000000000000000..8cffb03fdfbbdb3fa822a6d707fa826cadae322f
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -0,0 +1,1334 @@
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include "msm_drv.h"
+#include "sde_kms.h"
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_intf.h"
+#include "sde_hw_ctl.h"
+#include "sde_formats.h"
+#include "sde_encoder_phys.h"
+#include "sde_color_processing.h"
+
+#define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
+		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
+
+#define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
+		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
+
+/* timeout in frames waiting for frame done */
+#define SDE_ENCODER_FRAME_DONE_TIMEOUT	60
+
+/*
+ * Two to anticipate panels that can do cmd/vid dynamic switching
+ * plan is to create all possible physical encoder types, and switch between
+ * them at runtime
+ */
+#define NUM_PHYS_ENCODER_TYPES 2
+
+#define MAX_PHYS_ENCODERS_PER_VIRTUAL \
+	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
+
+#define MAX_CHANNELS_PER_ENC 2
+
+/**
+ * struct sde_encoder_virt - virtual encoder. Container of one or more physical
+ *	encoders. Virtual encoder manages one "logical" display. Physical
+ *	encoders manage one intf block, tied to a specific panel/sub-panel.
+ *	Virtual encoder defers as much as possible to the physical encoders.
+ *	Virtual encoder registers itself with the DRM Framework as the encoder.
+ * @base:		drm_encoder base class for registration with DRM
+ * @enc_spin_lock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
+ * @bus_scaling_client:	Client handle to the bus scaling interface
+ * @num_phys_encs:	Actual number of physical encoders contained.
+ * @phys_encs:		Container of physical encoders managed.
+ * @cur_master:		Pointer to the current master in this mode. Optimization
+ *			Only valid after enable. Cleared as disable.
+ * @hw_pp		Handle to the pingpong blocks used for the display. No.
+ *                      pingpong blocks can be different than num_phys_encs.
+ * @crtc_vblank_cb:	Callback into the upper layer / CRTC for
+ *			notification of the VBLANK
+ * @crtc_vblank_cb_data:	Data from upper layer for VBLANK notification
+ * @crtc_kickoff_cb:		Callback into CRTC that will flush & start
+ *				all CTL paths
+ * @crtc_kickoff_cb_data:	Opaque user data given to crtc_kickoff_cb
+ * @debugfs_root:		Debug file system root file node
+ * @enc_lock:			Lock around physical encoder create/destroy and
+				access.
+ * @frame_busy_mask:		Bitmask tracking which phys_enc we are still
+ *				busy processing current command.
+ *				Bit0 = phys_encs[0] etc.
+ * @crtc_frame_event_cb:	callback handler for frame event
+ * @crtc_frame_event_cb_data:	callback handler private data
+ * @crtc_frame_event:		callback event
+ * @frame_done_timeout:		frame done timeout in Hz
+ * @frame_done_timer:		watchdog timer for frame done event
+ */
+struct sde_encoder_virt {
+	struct drm_encoder base;
+	spinlock_t enc_spinlock;
+	uint32_t bus_scaling_client;
+
+	uint32_t display_num_of_h_tiles;
+
+	unsigned int num_phys_encs;
+	struct sde_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
+	struct sde_encoder_phys *cur_master;
+	struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+
+	void (*crtc_vblank_cb)(void *);
+	void *crtc_vblank_cb_data;
+
+	struct dentry *debugfs_root;
+	struct mutex enc_lock;
+	DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
+	void (*crtc_frame_event_cb)(void *, u32 event);
+	void *crtc_frame_event_cb_data;
+	u32 crtc_frame_event;
+
+	atomic_t frame_done_timeout;
+	struct timer_list frame_done_timer;
+};
+
+#define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
+
+void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
+		struct sde_encoder_hw_resources *hw_res,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	int i = 0;
+
+	if (!hw_res || !drm_enc || !conn_state) {
+		SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
+				drm_enc != 0, hw_res != 0, conn_state != 0);
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	/* Query resources used by phys encs, expected to be without overlap */
+	memset(hw_res, 0, sizeof(*hw_res));
+	hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.get_hw_resources)
+			phys->ops.get_hw_resources(phys, hw_res, conn_state);
+	}
+}
+
+void sde_encoder_destroy(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	int i = 0;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	mutex_lock(&sde_enc->enc_lock);
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.destroy) {
+			phys->ops.destroy(phys);
+			--sde_enc->num_phys_encs;
+			sde_enc->phys_encs[i] = NULL;
+		}
+	}
+
+	if (sde_enc->num_phys_encs)
+		SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
+				sde_enc->num_phys_encs);
+	sde_enc->num_phys_encs = 0;
+	mutex_unlock(&sde_enc->enc_lock);
+
+	drm_encoder_cleanup(drm_enc);
+	debugfs_remove_recursive(sde_enc->debugfs_root);
+	mutex_destroy(&sde_enc->enc_lock);
+
+	kfree(sde_enc);
+}
+
+void sde_encoder_helper_split_config(
+		struct sde_encoder_phys *phys_enc,
+		enum sde_intf interface)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct split_pipe_cfg cfg = { 0 };
+	struct sde_hw_mdp *hw_mdptop;
+	enum sde_rm_topology_name topology;
+
+	if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
+		SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(phys_enc->parent);
+	hw_mdptop = phys_enc->hw_mdptop;
+	cfg.en = phys_enc->split_role != ENC_ROLE_SOLO;
+	cfg.mode = phys_enc->intf_mode;
+	cfg.intf = interface;
+
+	if (cfg.en && phys_enc->ops.needs_single_flush &&
+			phys_enc->ops.needs_single_flush(phys_enc))
+		cfg.split_flush_en = true;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
+		cfg.pp_split_slave = cfg.intf;
+	else
+		cfg.pp_split_slave = INTF_MAX;
+
+	if (phys_enc->split_role != ENC_ROLE_SLAVE) {
+		/* master/solo encoder */
+		SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg.en);
+
+		if (hw_mdptop->ops.setup_split_pipe)
+			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
+	} else {
+		/*
+		 * slave encoder
+		 * - determine split index from master index,
+		 *   assume master is first pp
+		 */
+		cfg.pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
+		SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
+				cfg.pp_split_index);
+
+		if (hw_mdptop->ops.setup_pp_split)
+			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
+	}
+}
+
+static int sde_encoder_virt_atomic_check(
+		struct drm_encoder *drm_enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+	const struct drm_display_mode *mode;
+	struct drm_display_mode *adj_mode;
+	int i = 0;
+	int ret = 0;
+
+	if (!drm_enc || !crtc_state || !conn_state) {
+		SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
+				drm_enc != 0, crtc_state != 0, conn_state != 0);
+		return -EINVAL;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	priv = drm_enc->dev->dev_private;
+	sde_kms = to_sde_kms(priv->kms);
+	mode = &crtc_state->mode;
+	adj_mode = &crtc_state->adjusted_mode;
+	SDE_EVT32(DRMID(drm_enc));
+
+	/* perform atomic check on the first physical encoder (master) */
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.atomic_check)
+			ret = phys->ops.atomic_check(phys, crtc_state,
+					conn_state);
+		else if (phys && phys->ops.mode_fixup)
+			if (!phys->ops.mode_fixup(phys, mode, adj_mode))
+				ret = -EINVAL;
+
+		if (ret) {
+			SDE_ERROR_ENC(sde_enc,
+					"mode unsupported, phys idx %d\n", i);
+			break;
+		}
+	}
+
+	/* Reserve dynamic resources now. Indicating AtomicTest phase */
+	if (!ret)
+		ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
+				conn_state, true);
+
+	if (!ret)
+		drm_mode_set_crtcinfo(adj_mode, 0);
+
+	SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
+
+	return ret;
+}
+
+static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
+				      struct drm_display_mode *mode,
+				      struct drm_display_mode *adj_mode)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+	struct list_head *connector_list;
+	struct drm_connector *conn = NULL, *conn_iter;
+	struct sde_rm_hw_iter pp_iter;
+	int i = 0, ret;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	priv = drm_enc->dev->dev_private;
+	sde_kms = to_sde_kms(priv->kms);
+	connector_list = &sde_kms->dev->mode_config.connector_list;
+
+	SDE_EVT32(DRMID(drm_enc));
+
+	list_for_each_entry(conn_iter, connector_list, head)
+		if (conn_iter->encoder == drm_enc)
+			conn = conn_iter;
+
+	if (!conn) {
+		SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
+		return;
+	} else if (!conn->state) {
+		SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
+		return;
+	}
+
+	/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
+	ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
+			conn->state, false);
+	if (ret) {
+		SDE_ERROR_ENC(sde_enc,
+				"failed to reserve hw resources, %d\n", ret);
+		return;
+	}
+
+	sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
+	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+		sde_enc->hw_pp[i] = NULL;
+		if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
+			break;
+		sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
+	}
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys) {
+			if (!sde_enc->hw_pp[i]) {
+				SDE_ERROR_ENC(sde_enc,
+				    "invalid pingpong block for the encoder\n");
+				return;
+			}
+			phys->hw_pp = sde_enc->hw_pp[i];
+			phys->connector = conn->state->connector;
+			if (phys->ops.mode_set)
+				phys->ops.mode_set(phys, mode, adj_mode);
+		}
+	}
+}
+
+static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+	int i = 0;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	} else if (!drm_enc->dev) {
+		SDE_ERROR("invalid dev\n");
+		return;
+	} else if (!drm_enc->dev->dev_private) {
+		SDE_ERROR("invalid dev_private\n");
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	priv = drm_enc->dev->dev_private;
+	sde_kms = to_sde_kms(priv->kms);
+
+	SDE_DEBUG_ENC(sde_enc, "\n");
+	SDE_EVT32(DRMID(drm_enc));
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+
+	sde_enc->cur_master = NULL;
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys) {
+			atomic_set(&phys->vsync_cnt, 0);
+			atomic_set(&phys->underrun_cnt, 0);
+
+			if (phys->ops.is_master && phys->ops.is_master(phys)) {
+				SDE_DEBUG_ENC(sde_enc,
+						"master is now idx %d\n", i);
+				sde_enc->cur_master = phys;
+			} else if (phys->ops.enable) {
+				phys->ops.enable(phys);
+			}
+		}
+	}
+
+	if (!sde_enc->cur_master)
+		SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
+	else if (sde_enc->cur_master->ops.enable)
+		sde_enc->cur_master->ops.enable(sde_enc->cur_master);
+}
+
+static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+	int i = 0;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	} else if (!drm_enc->dev) {
+		SDE_ERROR("invalid dev\n");
+		return;
+	} else if (!drm_enc->dev->dev_private) {
+		SDE_ERROR("invalid dev_private\n");
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	priv = drm_enc->dev->dev_private;
+	sde_kms = to_sde_kms(priv->kms);
+
+	SDE_EVT32(DRMID(drm_enc));
+
+	if (atomic_xchg(&sde_enc->frame_done_timeout, 0)) {
+		SDE_ERROR("enc%d timeout pending\n", drm_enc->base.id);
+		del_timer_sync(&sde_enc->frame_done_timer);
+	}
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys) {
+			if (phys->ops.disable && !phys->ops.is_master(phys))
+				phys->ops.disable(phys);
+			phys->connector = NULL;
+			atomic_set(&phys->vsync_cnt, 0);
+			atomic_set(&phys->underrun_cnt, 0);
+		}
+	}
+
+	if (sde_enc->cur_master && sde_enc->cur_master->ops.disable)
+		sde_enc->cur_master->ops.disable(sde_enc->cur_master);
+
+	sde_enc->cur_master = NULL;
+	SDE_DEBUG_ENC(sde_enc, "cleared master\n");
+
+	sde_rm_release(&sde_kms->rm, drm_enc);
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+}
+
+static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
+	.mode_set = sde_encoder_virt_mode_set,
+	.disable = sde_encoder_virt_disable,
+	.enable = sde_encoder_virt_enable,
+	.atomic_check = sde_encoder_virt_atomic_check,
+};
+
+static const struct drm_encoder_funcs sde_encoder_funcs = {
+		.destroy = sde_encoder_destroy,
+};
+
+static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
+		enum sde_intf_type type, u32 controller_id)
+{
+	int i = 0;
+
+	for (i = 0; i < catalog->intf_count; i++) {
+		if (catalog->intf[i].type == type
+		    && catalog->intf[i].controller_id == controller_id) {
+			return catalog->intf[i].id;
+		}
+	}
+
+	return INTF_MAX;
+}
+
+static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
+		enum sde_intf_type type, u32 controller_id)
+{
+	if (controller_id < catalog->wb_count)
+		return catalog->wb[controller_id].id;
+
+	return WB_MAX;
+}
+
+static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
+		struct sde_encoder_phys *phy_enc)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	unsigned long lock_flags;
+
+	if (!drm_enc || !phy_enc)
+		return;
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+
+	spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
+	if (sde_enc->crtc_vblank_cb)
+		sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
+	spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
+
+	atomic_inc(&phy_enc->vsync_cnt);
+}
+
+static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
+		struct sde_encoder_phys *phy_enc)
+{
+	if (!phy_enc)
+		return;
+
+	atomic_inc(&phy_enc->underrun_cnt);
+	SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
+}
+
+void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
+		void (*vbl_cb)(void *), void *vbl_data)
+{
+	struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
+	unsigned long lock_flags;
+	bool enable;
+	int i;
+
+	enable = vbl_cb ? true : false;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	SDE_DEBUG_ENC(sde_enc, "\n");
+	SDE_EVT32(DRMID(drm_enc), enable);
+
+	spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
+	sde_enc->crtc_vblank_cb = vbl_cb;
+	sde_enc->crtc_vblank_cb_data = vbl_data;
+	spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.control_vblank_irq)
+			phys->ops.control_vblank_irq(phys, enable);
+	}
+}
+
+void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
+		void (*frame_event_cb)(void *, u32 event),
+		void *frame_event_cb_data)
+{
+	struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
+	unsigned long lock_flags;
+	bool enable;
+
+	enable = frame_event_cb ? true : false;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	SDE_DEBUG_ENC(sde_enc, "\n");
+	SDE_EVT32(DRMID(drm_enc), enable, 0);
+
+	spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
+	sde_enc->crtc_frame_event_cb = frame_event_cb;
+	sde_enc->crtc_frame_event_cb_data = frame_event_cb_data;
+	spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
+}
+
+static void sde_encoder_frame_done_callback(
+		struct drm_encoder *drm_enc,
+		struct sde_encoder_phys *ready_phys, u32 event)
+{
+	struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
+	unsigned int i;
+
+	/* One of the physical encoders has become idle */
+	for (i = 0; i < sde_enc->num_phys_encs; i++)
+		if (sde_enc->phys_encs[i] == ready_phys) {
+			clear_bit(i, sde_enc->frame_busy_mask);
+			sde_enc->crtc_frame_event |= event;
+			SDE_EVT32(DRMID(drm_enc), i,
+					sde_enc->frame_busy_mask[0]);
+		}
+
+	if (!sde_enc->frame_busy_mask[0]) {
+		atomic_set(&sde_enc->frame_done_timeout, 0);
+		del_timer(&sde_enc->frame_done_timer);
+
+		if (sde_enc->crtc_frame_event_cb)
+			sde_enc->crtc_frame_event_cb(
+					sde_enc->crtc_frame_event_cb_data,
+					sde_enc->crtc_frame_event);
+	}
+}
+
+/**
+ * _sde_encoder_trigger_flush - trigger flush for a physical encoder
+ * drm_enc: Pointer to drm encoder structure
+ * phys: Pointer to physical encoder structure
+ * extra_flush_bits: Additional bit mask to include in flush trigger
+ */
+static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
+		struct sde_encoder_phys *phys, uint32_t extra_flush_bits)
+{
+	struct sde_hw_ctl *ctl;
+	int pending_kickoff_cnt;
+
+	if (!drm_enc || !phys) {
+		SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
+				drm_enc != 0, phys != 0);
+		return;
+	}
+
+	ctl = phys->hw_ctl;
+	if (!ctl || !ctl->ops.trigger_flush) {
+		SDE_ERROR("missing trigger cb\n");
+		return;
+	}
+
+	pending_kickoff_cnt = sde_encoder_phys_inc_pending(phys);
+	SDE_EVT32(DRMID(&to_sde_encoder_virt(drm_enc)->base),
+			phys->intf_idx, pending_kickoff_cnt);
+
+	if (extra_flush_bits && ctl->ops.update_pending_flush)
+		ctl->ops.update_pending_flush(ctl, extra_flush_bits);
+
+	ctl->ops.trigger_flush(ctl);
+	SDE_EVT32(DRMID(drm_enc), ctl->idx);
+}
+
+/**
+ * _sde_encoder_trigger_start - trigger start for a physical encoder
+ * phys: Pointer to physical encoder structure
+ */
+static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
+{
+	if (!phys) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
+		phys->ops.trigger_start(phys);
+}
+
+void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_hw_ctl *ctl;
+	int ctl_idx = -1;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	ctl = phys_enc->hw_ctl;
+	if (ctl && ctl->ops.trigger_start) {
+		ctl->ops.trigger_start(ctl);
+		ctl_idx = ctl->idx;
+	}
+
+	if (phys_enc && phys_enc->parent)
+		SDE_EVT32(DRMID(phys_enc->parent), ctl_idx);
+}
+
+int sde_encoder_helper_wait_event_timeout(
+		int32_t drm_id,
+		int32_t hw_id,
+		wait_queue_head_t *wq,
+		atomic_t *cnt,
+		s64 timeout_ms)
+{
+	int rc = 0;
+	s64 expected_time = ktime_to_ms(ktime_get()) + timeout_ms;
+	s64 jiffies = msecs_to_jiffies(timeout_ms);
+	s64 time;
+
+	do {
+		rc = wait_event_timeout(*wq, atomic_read(cnt) == 0, jiffies);
+		time = ktime_to_ms(ktime_get());
+
+		SDE_EVT32(drm_id, hw_id, rc, time, expected_time,
+				atomic_read(cnt));
+	/* If we timed out, counter is valid and time is less, wait again */
+	} while (atomic_read(cnt) && (rc == 0) && (time < expected_time));
+
+	return rc;
+}
+
+/**
+ * _sde_encoder_kickoff_phys - handle physical encoder kickoff
+ *	Iterate through the physical encoders and perform consolidated flush
+ *	and/or control start triggering as needed. This is done in the virtual
+ *	encoder rather than the individual physical ones in order to handle
+ *	use cases that require visibility into multiple physical encoders at
+ *	a time.
+ * sde_enc: Pointer to virtual encoder structure
+ */
+static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
+{
+	struct sde_hw_ctl *ctl;
+	uint32_t i, pending_flush;
+	unsigned long lock_flags;
+
+	if (!sde_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	pending_flush = 0x0;
+	sde_enc->crtc_frame_event = 0;
+
+	/* update pending counts and trigger kickoff ctl flush atomically */
+	spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
+
+	/* don't perform flush/start operations for slave encoders */
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (!phys || phys->enable_state == SDE_ENC_DISABLED)
+			continue;
+
+		ctl = phys->hw_ctl;
+		if (!ctl)
+			continue;
+
+		set_bit(i, sde_enc->frame_busy_mask);
+
+		if (!phys->ops.needs_single_flush ||
+				!phys->ops.needs_single_flush(phys))
+			_sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
+		else if (ctl->ops.get_pending_flush)
+			pending_flush |= ctl->ops.get_pending_flush(ctl);
+	}
+
+	/* for split flush, combine pending flush masks and send to master */
+	if (pending_flush && sde_enc->cur_master) {
+		_sde_encoder_trigger_flush(
+				&sde_enc->base,
+				sde_enc->cur_master,
+				pending_flush);
+	}
+
+	_sde_encoder_trigger_start(sde_enc->cur_master);
+
+	spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
+}
+
+void sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct sde_encoder_phys *phys;
+	unsigned int i;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	sde_enc = to_sde_encoder_virt(drm_enc);
+
+	SDE_DEBUG_ENC(sde_enc, "\n");
+	SDE_EVT32(DRMID(drm_enc));
+
+	/* prepare for next kickoff, may include waiting on previous kickoff */
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		phys = sde_enc->phys_encs[i];
+		if (phys && phys->ops.prepare_for_kickoff)
+			phys->ops.prepare_for_kickoff(phys);
+	}
+}
+
+void sde_encoder_kickoff(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct sde_encoder_phys *phys;
+	unsigned int i;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	sde_enc = to_sde_encoder_virt(drm_enc);
+
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	atomic_set(&sde_enc->frame_done_timeout,
+			SDE_ENCODER_FRAME_DONE_TIMEOUT * 1000 /
+			drm_enc->crtc->state->adjusted_mode.vrefresh);
+	mod_timer(&sde_enc->frame_done_timer, jiffies +
+		((atomic_read(&sde_enc->frame_done_timeout) * HZ) / 1000));
+
+	/* All phys encs are ready to go, trigger the kickoff */
+	_sde_encoder_kickoff_phys(sde_enc);
+
+	/* allow phys encs to handle any post-kickoff business */
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		phys = sde_enc->phys_encs[i];
+		if (phys && phys->ops.handle_post_kickoff)
+			phys->ops.handle_post_kickoff(phys);
+	}
+}
+
+static int _sde_encoder_status_show(struct seq_file *s, void *data)
+{
+	struct sde_encoder_virt *sde_enc;
+	int i;
+
+	if (!s || !s->private)
+		return -EINVAL;
+
+	sde_enc = s->private;
+
+	mutex_lock(&sde_enc->enc_lock);
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (!phys)
+			continue;
+
+		seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
+				phys->intf_idx - INTF_0,
+				atomic_read(&phys->vsync_cnt),
+				atomic_read(&phys->underrun_cnt));
+
+		switch (phys->intf_mode) {
+		case INTF_MODE_VIDEO:
+			seq_puts(s, "mode: video\n");
+			break;
+		case INTF_MODE_CMD:
+			seq_puts(s, "mode: command\n");
+			break;
+		case INTF_MODE_WB_BLOCK:
+			seq_puts(s, "mode: wb block\n");
+			break;
+		case INTF_MODE_WB_LINE:
+			seq_puts(s, "mode: wb line\n");
+			break;
+		default:
+			seq_puts(s, "mode: ???\n");
+			break;
+		}
+	}
+	mutex_unlock(&sde_enc->enc_lock);
+
+	return 0;
+}
+
+static int _sde_encoder_debugfs_status_open(struct inode *inode,
+		struct file *file)
+{
+	return single_open(file, _sde_encoder_status_show, inode->i_private);
+}
+
+static void _sde_set_misr_params(struct sde_encoder_phys *phys, u32 enable,
+					u32 frame_count)
+{
+	int j;
+
+	if (!phys->misr_map)
+		return;
+
+	phys->misr_map->enable = enable;
+
+	if (frame_count <= SDE_CRC_BATCH_SIZE)
+		phys->misr_map->frame_count = frame_count;
+	else if (frame_count <= 0)
+		phys->misr_map->frame_count = 0;
+	else
+		phys->misr_map->frame_count = SDE_CRC_BATCH_SIZE;
+
+	if (!enable) {
+		phys->misr_map->last_idx = 0;
+		phys->misr_map->frame_count = 0;
+		for (j = 0; j < SDE_CRC_BATCH_SIZE; j++)
+			phys->misr_map->crc_value[j] = 0;
+	}
+}
+
+static ssize_t _sde_encoder_misr_set(struct file *file,
+		const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct drm_encoder *drm_enc;
+	int i = 0;
+	char buf[10];
+	u32 enable, frame_count;
+
+	drm_enc = file->private_data;
+	sde_enc = to_sde_encoder_virt(drm_enc);
+
+	if (copy_from_user(buf, user_buf, count))
+		return -EFAULT;
+
+	buf[count] = 0; /* end of string */
+
+	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
+		return -EFAULT;
+
+	mutex_lock(&sde_enc->enc_lock);
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (!phys || !phys->misr_map || !phys->ops.setup_misr)
+			continue;
+
+		_sde_set_misr_params(phys, enable, frame_count);
+		phys->ops.setup_misr(phys, phys->misr_map);
+	}
+	mutex_unlock(&sde_enc->enc_lock);
+	return count;
+}
+
+static ssize_t _sde_encoder_misr_read(
+		struct file *file,
+		char __user *buff, size_t count, loff_t *ppos)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct drm_encoder *drm_enc;
+	int i = 0, j = 0, len = 0;
+	char buf[512] = {'\0'};
+
+	if (*ppos)
+		return 0;
+
+	drm_enc = file->private_data;
+	sde_enc = to_sde_encoder_virt(drm_enc);
+
+	mutex_lock(&sde_enc->enc_lock);
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+		struct sde_misr_params *misr_map;
+
+		if (!phys || !phys->misr_map)
+			continue;
+
+		misr_map = phys->misr_map;
+
+		len += snprintf(buf+len, sizeof(buf), "INTF%d\n", i);
+		for (j = 0; j < SDE_CRC_BATCH_SIZE; j++)
+			len += snprintf(buf+len, sizeof(buf), "%x\n",
+						misr_map->crc_value[j]);
+	}
+
+	if (len < 0 || len >= sizeof(buf))
+		return 0;
+
+	if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
+		return -EFAULT;
+
+	*ppos += len;   /* increase offset */
+	mutex_unlock(&sde_enc->enc_lock);
+
+	return len;
+}
+
+static void _sde_encoder_init_debugfs(struct drm_encoder *drm_enc,
+	struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms)
+{
+	static const struct file_operations debugfs_status_fops = {
+		.open =		_sde_encoder_debugfs_status_open,
+		.read =		seq_read,
+		.llseek =	seq_lseek,
+		.release =	single_release,
+	};
+
+	static const struct file_operations debugfs_misr_fops = {
+		.open = simple_open,
+		.read = _sde_encoder_misr_read,
+		.write = _sde_encoder_misr_set,
+	};
+
+	char name[SDE_NAME_SIZE];
+
+	if (!drm_enc || !sde_enc || !sde_kms) {
+		SDE_ERROR("invalid encoder or kms\n");
+		return;
+	}
+
+	snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
+
+	/* create overall sub-directory for the encoder */
+	sde_enc->debugfs_root = debugfs_create_dir(name,
+					sde_debugfs_get_root(sde_kms));
+	if (sde_enc->debugfs_root) {
+		/* don't error check these */
+		debugfs_create_file("status", S_IRUGO | S_IWUSR,
+			sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
+
+		debugfs_create_file("misr_data", S_IRUGO | S_IWUSR,
+			sde_enc->debugfs_root, drm_enc, &debugfs_misr_fops);
+
+	}
+}
+
+static int sde_encoder_virt_add_phys_encs(
+		u32 display_caps,
+		struct sde_encoder_virt *sde_enc,
+		struct sde_enc_phys_init_params *params)
+{
+	struct sde_encoder_phys *enc = NULL;
+
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	/*
+	 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
+	 * in this function, check up-front.
+	 */
+	if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
+			ARRAY_SIZE(sde_enc->phys_encs)) {
+		SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
+			  sde_enc->num_phys_encs);
+		return -EINVAL;
+	}
+
+	if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
+		enc = sde_encoder_phys_vid_init(params);
+
+		if (IS_ERR_OR_NULL(enc)) {
+			SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
+				PTR_ERR(enc));
+			return enc == 0 ? -EINVAL : PTR_ERR(enc);
+		}
+
+		sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
+		++sde_enc->num_phys_encs;
+	}
+
+	if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
+		enc = sde_encoder_phys_cmd_init(params);
+
+		if (IS_ERR_OR_NULL(enc)) {
+			SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
+				PTR_ERR(enc));
+			return enc == 0 ? -EINVAL : PTR_ERR(enc);
+		}
+
+		sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
+		++sde_enc->num_phys_encs;
+	}
+
+	return 0;
+}
+
+static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
+		struct sde_enc_phys_init_params *params)
+{
+	struct sde_encoder_phys *enc = NULL;
+
+	if (!sde_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
+		SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
+			  sde_enc->num_phys_encs);
+		return -EINVAL;
+	}
+
+	enc = sde_encoder_phys_wb_init(params);
+
+	if (IS_ERR_OR_NULL(enc)) {
+		SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
+			PTR_ERR(enc));
+		return enc == 0 ? -EINVAL : PTR_ERR(enc);
+	}
+
+	sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
+	++sde_enc->num_phys_encs;
+
+	return 0;
+}
+
+static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
+				 struct sde_kms *sde_kms,
+				 struct msm_display_info *disp_info,
+				 int *drm_enc_mode)
+{
+	int ret = 0;
+	int i = 0;
+	enum sde_intf_type intf_type;
+	struct sde_encoder_virt_ops parent_ops = {
+		sde_encoder_vblank_callback,
+		sde_encoder_underrun_callback,
+		sde_encoder_frame_done_callback,
+	};
+	struct sde_enc_phys_init_params phys_params;
+
+	if (!sde_enc || !sde_kms) {
+		SDE_ERROR("invalid arg(s), enc %d kms %d\n",
+				sde_enc != 0, sde_kms != 0);
+		return -EINVAL;
+	}
+
+	memset(&phys_params, 0, sizeof(phys_params));
+	phys_params.sde_kms = sde_kms;
+	phys_params.parent = &sde_enc->base;
+	phys_params.parent_ops = parent_ops;
+	phys_params.enc_spinlock = &sde_enc->enc_spinlock;
+
+	SDE_DEBUG("\n");
+
+	if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
+		*drm_enc_mode = DRM_MODE_ENCODER_DSI;
+		intf_type = INTF_DSI;
+	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
+		*drm_enc_mode = DRM_MODE_ENCODER_TMDS;
+		intf_type = INTF_HDMI;
+	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
+		*drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
+		intf_type = INTF_WB;
+	} else {
+		SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
+		return -EINVAL;
+	}
+
+	WARN_ON(disp_info->num_of_h_tiles < 1);
+
+	sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
+
+	SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
+
+	mutex_lock(&sde_enc->enc_lock);
+	for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
+		/*
+		 * Left-most tile is at index 0, content is controller id
+		 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
+		 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
+		 */
+		u32 controller_id = disp_info->h_tile_instance[i];
+
+		if (disp_info->num_of_h_tiles > 1) {
+			if (i == 0)
+				phys_params.split_role = ENC_ROLE_MASTER;
+			else
+				phys_params.split_role = ENC_ROLE_SLAVE;
+		} else {
+			phys_params.split_role = ENC_ROLE_SOLO;
+		}
+
+		SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
+				i, controller_id, phys_params.split_role);
+
+		if (intf_type == INTF_WB) {
+			phys_params.intf_idx = INTF_MAX;
+			phys_params.wb_idx = sde_encoder_get_wb(
+					sde_kms->catalog,
+					intf_type, controller_id);
+			if (phys_params.wb_idx == WB_MAX) {
+				SDE_ERROR_ENC(sde_enc,
+					"could not get wb: type %d, id %d\n",
+					intf_type, controller_id);
+				ret = -EINVAL;
+			}
+		} else {
+			phys_params.wb_idx = WB_MAX;
+			phys_params.intf_idx = sde_encoder_get_intf(
+					sde_kms->catalog, intf_type,
+					controller_id);
+			if (phys_params.intf_idx == INTF_MAX) {
+				SDE_ERROR_ENC(sde_enc,
+					"could not get wb: type %d, id %d\n",
+					intf_type, controller_id);
+				ret = -EINVAL;
+			}
+		}
+
+		if (!ret) {
+			if (intf_type == INTF_WB)
+				ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
+						&phys_params);
+			else
+				ret = sde_encoder_virt_add_phys_encs(
+						disp_info->capabilities,
+						sde_enc,
+						&phys_params);
+			if (ret)
+				SDE_ERROR_ENC(sde_enc,
+						"failed to add phys encs\n");
+		}
+	}
+	mutex_unlock(&sde_enc->enc_lock);
+
+
+	return ret;
+}
+
+static void sde_encoder_frame_done_timeout(unsigned long data)
+{
+	struct drm_encoder *drm_enc = (struct drm_encoder *) data;
+	struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
+	struct msm_drm_private *priv;
+
+	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
+		SDE_ERROR("invalid parameters\n");
+		return;
+	}
+	priv = drm_enc->dev->dev_private;
+
+	if (!sde_enc->frame_busy_mask[0] || !sde_enc->crtc_frame_event_cb) {
+		SDE_DEBUG("enc%d invalid timeout\n", drm_enc->base.id);
+		SDE_EVT32(DRMID(drm_enc),
+				sde_enc->frame_busy_mask[0], 0);
+		return;
+	} else if (!atomic_xchg(&sde_enc->frame_done_timeout, 0)) {
+		SDE_ERROR("enc%d invalid timeout\n", drm_enc->base.id);
+		SDE_EVT32(DRMID(drm_enc), 0, 1);
+		return;
+	}
+
+	SDE_EVT32(DRMID(drm_enc), 0, 2);
+	sde_enc->crtc_frame_event_cb(sde_enc->crtc_frame_event_cb_data,
+			SDE_ENCODER_FRAME_EVENT_ERROR);
+}
+
+struct drm_encoder *sde_encoder_init(
+		struct drm_device *dev,
+		struct msm_display_info *disp_info)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	struct sde_kms *sde_kms = to_sde_kms(priv->kms);
+	struct drm_encoder *drm_enc = NULL;
+	struct sde_encoder_virt *sde_enc = NULL;
+	int drm_enc_mode = DRM_MODE_ENCODER_NONE;
+	int ret = 0;
+
+	sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
+	if (!sde_enc) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	mutex_init(&sde_enc->enc_lock);
+	ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
+			&drm_enc_mode);
+	if (ret)
+		goto fail;
+
+	sde_enc->cur_master = NULL;
+	spin_lock_init(&sde_enc->enc_spinlock);
+	drm_enc = &sde_enc->base;
+	drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode);
+	drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
+
+	atomic_set(&sde_enc->frame_done_timeout, 0);
+	setup_timer(&sde_enc->frame_done_timer, sde_encoder_frame_done_timeout,
+			(unsigned long) sde_enc);
+
+	_sde_encoder_init_debugfs(drm_enc, sde_enc, sde_kms);
+
+	SDE_DEBUG_ENC(sde_enc, "created\n");
+
+	return drm_enc;
+
+fail:
+	SDE_ERROR("failed to create encoder\n");
+	if (drm_enc)
+		sde_encoder_destroy(drm_enc);
+
+	return ERR_PTR(ret);
+}
+
+int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	int i, ret = 0;
+
+	if (!drm_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	SDE_DEBUG_ENC(sde_enc, "\n");
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.wait_for_commit_done) {
+			ret = phys->ops.wait_for_commit_done(phys);
+			if (ret)
+				return ret;
+		}
+
+		if (phys && phys->ops.collect_misr)
+			if (phys->misr_map && phys->misr_map->enable)
+				phys->ops.collect_misr(phys, phys->misr_map);
+	}
+
+	return ret;
+}
+
+enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	int i;
+
+	if (!encoder) {
+		SDE_ERROR("invalid encoder\n");
+		return INTF_MODE_NONE;
+	}
+	sde_enc = to_sde_encoder_virt(encoder);
+
+	if (sde_enc->cur_master)
+		return sde_enc->cur_master->intf_mode;
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys)
+			return phys->intf_mode;
+	}
+
+	return INTF_MODE_NONE;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
new file mode 100644
index 0000000000000000000000000000000000000000..82576b479bf84b73d2c77725ace128729964c353
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SDE_ENCODER_H__
+#define __SDE_ENCODER_H__
+
+#include <drm/drm_crtc.h>
+
+#include "msm_prop.h"
+#include "sde_hw_mdss.h"
+
+#define SDE_ENCODER_FRAME_EVENT_DONE	BIT(0)
+#define SDE_ENCODER_FRAME_EVENT_ERROR	BIT(1)
+
+/**
+ * Encoder functions and data types
+ * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
+ * @wbs:	Writebacks this encoder is using, INTF_MODE_NONE if unused
+ * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
+ * @display_num_of_h_tiles:
+ */
+struct sde_encoder_hw_resources {
+	enum sde_intf_mode intfs[INTF_MAX];
+	enum sde_intf_mode wbs[WB_MAX];
+	bool needs_cdm;
+	u32 display_num_of_h_tiles;
+};
+
+/**
+ * sde_encoder_get_hw_resources - Populate table of required hardware resources
+ * @encoder:	encoder pointer
+ * @hw_res:	resource table to populate with encoder required resources
+ * @conn_state:	report hw reqs based on this proposed connector state
+ */
+void sde_encoder_get_hw_resources(struct drm_encoder *encoder,
+		struct sde_encoder_hw_resources *hw_res,
+		struct drm_connector_state *conn_state);
+
+/**
+ * sde_encoder_register_vblank_callback - provide callback to encoder that
+ *	will be called on the next vblank.
+ * @encoder:	encoder pointer
+ * @cb:		callback pointer, provide NULL to deregister and disable IRQs
+ * @data:	user data provided to callback
+ */
+void sde_encoder_register_vblank_callback(struct drm_encoder *encoder,
+		void (*cb)(void *), void *data);
+
+/**
+ * sde_encoder_register_frame_event_callback - provide callback to encoder that
+ *	will be called after the request is complete, or other events.
+ * @encoder:	encoder pointer
+ * @cb:		callback pointer, provide NULL to deregister
+ * @data:	user data provided to callback
+ */
+void sde_encoder_register_frame_event_callback(struct drm_encoder *encoder,
+		void (*cb)(void *, u32), void *data);
+
+/**
+ * sde_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
+ *	path (i.e. ctl flush and start) at next appropriate time.
+ *	Immediately: if no previous commit is outstanding.
+ *	Delayed: Block until next trigger can be issued.
+ * @encoder:	encoder pointer
+ */
+void sde_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
+
+/**
+ * sde_encoder_kickoff - trigger a double buffer flip of the ctl path
+ *	(i.e. ctl flush and start) immediately.
+ * @encoder:	encoder pointer
+ */
+void sde_encoder_kickoff(struct drm_encoder *encoder);
+
+/**
+ * sde_encoder_wait_nxt_committed - Wait for hardware to have flushed the
+ *	current pending frames to hardware at a vblank or ctl_start
+ *	Encoders will map this differently depending on irqs
+ *	vid mode -> vsync_irq
+ * @encoder:	encoder pointer
+ * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
+ */
+int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
+
+/*
+ * sde_encoder_get_intf_mode - get interface mode of the given encoder
+ * @encoder: Pointer to drm encoder object
+ */
+enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder);
+
+/**
+ * sde_encoder_init - initialize virtual encoder object
+ * @dev:        Pointer to drm device structure
+ * @disp_info:  Pointer to display information structure
+ * Returns:     Pointer to newly created drm encoder
+ */
+struct drm_encoder *sde_encoder_init(
+		struct drm_device *dev,
+		struct msm_display_info *disp_info);
+
+/**
+ * sde_encoder_destroy - destroy previously initialized virtual encoder
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ */
+void sde_encoder_destroy(struct drm_encoder *drm_enc);
+
+#endif /* __SDE_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
new file mode 100644
index 0000000000000000000000000000000000000000..ed4b7be34281f08b8db48cabc640a8e0cc737ecd
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SDE_ENCODER_PHYS_H__
+#define __SDE_ENCODER_PHYS_H__
+
+#include <linux/jiffies.h>
+
+#include "sde_kms.h"
+#include "sde_hw_intf.h"
+#include "sde_hw_pingpong.h"
+#include "sde_hw_ctl.h"
+#include "sde_hw_top.h"
+#include "sde_hw_wb.h"
+#include "sde_hw_cdm.h"
+#include "sde_encoder.h"
+#include "sde_connector.h"
+
+#define SDE_ENCODER_NAME_MAX	16
+
+/* wait for at most 2 vsync for lowest refresh rate (24hz) */
+#define KICKOFF_TIMEOUT_MS		84
+#define KICKOFF_TIMEOUT_JIFFIES		msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
+
+/**
+ * enum sde_enc_split_role - Role this physical encoder will play in a
+ *	split-panel configuration, where one panel is master, and others slaves.
+ *	Masters have extra responsibilities, like managing the VBLANK IRQ.
+ * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
+ * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
+ * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
+ */
+enum sde_enc_split_role {
+	ENC_ROLE_SOLO,
+	ENC_ROLE_MASTER,
+	ENC_ROLE_SLAVE
+};
+
+struct sde_encoder_phys;
+
+/**
+ * struct sde_encoder_virt_ops - Interface the containing virtual encoder
+ *	provides for the physical encoders to use to callback.
+ * @handle_vblank_virt:	Notify virtual encoder of vblank IRQ reception
+ *			Note: This is called from IRQ handler context.
+ * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
+ *			Note: This is called from IRQ handler context.
+ * @handle_frame_done:	Notify virtual encoder that this phys encoder
+ *			completes last request frame.
+ */
+struct sde_encoder_virt_ops {
+	void (*handle_vblank_virt)(struct drm_encoder *,
+			struct sde_encoder_phys *phys);
+	void (*handle_underrun_virt)(struct drm_encoder *,
+			struct sde_encoder_phys *phys);
+	void (*handle_frame_done)(struct drm_encoder *,
+			struct sde_encoder_phys *phys, u32 event);
+};
+
+/**
+ * struct sde_encoder_phys_ops - Interface the physical encoders provide to
+ *	the containing virtual encoder.
+ * @is_master:			Whether this phys_enc is the current master
+ *				encoder. Can be switched at enable time. Based
+ *				on split_role and current mode (CMD/VID).
+ * @mode_fixup:			DRM Call. Fixup a DRM mode.
+ * @mode_set:			DRM Call. Set a DRM mode.
+ *				This likely caches the mode, for use at enable.
+ * @enable:			DRM Call. Enable a DRM mode.
+ * @disable:			DRM Call. Disable mode.
+ * @atomic_check:		DRM Call. Atomic check new DRM state.
+ * @destroy:			DRM Call. Destroy and release resources.
+ * @get_hw_resources:		Populate the structure with the hardware
+ *				resources that this phys_enc is using.
+ *				Expect no overlap between phys_encs.
+ * @control_vblank_irq		Register/Deregister for VBLANK IRQ
+ * @wait_for_commit_done:	Wait for hardware to have flushed the
+ *				current pending frames to hardware
+ * @prepare_for_kickoff:	Do any work necessary prior to a kickoff
+ *				For CMD encoder, may wait for previous tx done
+ * @handle_post_kickoff:	Do any work necessary post-kickoff work
+ * @trigger_start:		Process start event on physical encoder
+ * @needs_single_flush:		Whether encoder slaves need to be flushed
+ * @setup_misr:		Sets up MISR, enable and disables based on sysfs
+ * @collect_misr:		Collects MISR data on frame update
+ */
+
+struct sde_encoder_phys_ops {
+	bool (*is_master)(struct sde_encoder_phys *encoder);
+	bool (*mode_fixup)(struct sde_encoder_phys *encoder,
+			const struct drm_display_mode *mode,
+			struct drm_display_mode *adjusted_mode);
+	void (*mode_set)(struct sde_encoder_phys *encoder,
+			struct drm_display_mode *mode,
+			struct drm_display_mode *adjusted_mode);
+	void (*enable)(struct sde_encoder_phys *encoder);
+	void (*disable)(struct sde_encoder_phys *encoder);
+	int (*atomic_check)(struct sde_encoder_phys *encoder,
+			    struct drm_crtc_state *crtc_state,
+			    struct drm_connector_state *conn_state);
+	void (*destroy)(struct sde_encoder_phys *encoder);
+	void (*get_hw_resources)(struct sde_encoder_phys *encoder,
+			struct sde_encoder_hw_resources *hw_res,
+			struct drm_connector_state *conn_state);
+	int (*control_vblank_irq)(struct sde_encoder_phys *enc, bool enable);
+	int (*wait_for_commit_done)(struct sde_encoder_phys *phys_enc);
+	void (*prepare_for_kickoff)(struct sde_encoder_phys *phys_enc);
+	void (*handle_post_kickoff)(struct sde_encoder_phys *phys_enc);
+	void (*trigger_start)(struct sde_encoder_phys *phys_enc);
+	bool (*needs_single_flush)(struct sde_encoder_phys *phys_enc);
+
+	void (*setup_misr)(struct sde_encoder_phys *phys_encs,
+			struct sde_misr_params *misr_map);
+	void (*collect_misr)(struct sde_encoder_phys *phys_enc,
+			struct sde_misr_params *misr_map);
+};
+
+/**
+ * enum sde_enc_enable_state - current enabled state of the physical encoder
+ * @SDE_ENC_DISABLED:	Encoder is disabled
+ * @SDE_ENC_ENABLING:	Encoder transitioning to enabled
+ *			Events bounding transition are encoder type specific
+ * @SDE_ENC_ENABLED:	Encoder is enabled
+ */
+enum sde_enc_enable_state {
+	SDE_ENC_DISABLED,
+	SDE_ENC_ENABLING,
+	SDE_ENC_ENABLED
+};
+
+/**
+ * enum sde_intr_idx - sde encoder interrupt index
+ * @INTR_IDX_VSYNC:    Vsync interrupt for video mode panel
+ * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
+ * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
+ * @INTR_IDX_RDPTR:    Readpointer done interrupt for cmd mode panel
+ */
+enum sde_intr_idx {
+	INTR_IDX_VSYNC,
+	INTR_IDX_PINGPONG,
+	INTR_IDX_UNDERRUN,
+	INTR_IDX_RDPTR,
+	INTR_IDX_MAX,
+};
+
+/**
+ * struct sde_encoder_phys - physical encoder that drives a single INTF block
+ *	tied to a specific panel / sub-panel. Abstract type, sub-classed by
+ *	phys_vid or phys_cmd for video mode or command mode encs respectively.
+ * @parent:		Pointer to the containing virtual encoder
+ * @connector:		If a mode is set, cached pointer to the active connector
+ * @ops:		Operations exposed to the virtual encoder
+ * @parent_ops:		Callbacks exposed by the parent to the phys_enc
+ * @hw_mdptop:		Hardware interface to the top registers
+ * @hw_ctl:		Hardware interface to the ctl registers
+ * @hw_cdm:		Hardware interface to the cdm registers
+ * @cdm_cfg:		Chroma-down hardware configuration
+ * @hw_pp:		Hardware interface to the ping pong registers
+ * @sde_kms:		Pointer to the sde_kms top level
+ * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
+ * @misr_map:		Interface for setting and collecting MISR data
+ * @enabled:		Whether the encoder has enabled and running a mode
+ * @split_role:		Role to play in a split-panel configuration
+ * @intf_mode:		Interface mode
+ * @intf_idx:		Interface index on sde hardware
+ * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
+ * @enable_state:	Enable state tracking
+ * @vblank_refcount:	Reference count of vblank request
+ * @vsync_cnt:		Vsync count for the physical encoder
+ * @underrun_cnt:	Underrun count for the physical encoder
+ * @pending_kickoff_cnt:	Atomic counter tracking the number of kickoffs
+ *				vs. the number of done/vblank irqs. Should hover
+ *				between 0-2 Incremented when a new kickoff is
+ *				scheduled. Decremented in irq handler
+ * @pending_kickoff_wq:		Wait queue for blocking until kickoff completes
+ */
+struct sde_encoder_phys {
+	struct drm_encoder *parent;
+	struct drm_connector *connector;
+	struct sde_encoder_phys_ops ops;
+	struct sde_encoder_virt_ops parent_ops;
+	struct sde_hw_mdp *hw_mdptop;
+	struct sde_hw_ctl *hw_ctl;
+	struct sde_hw_cdm *hw_cdm;
+	struct sde_hw_cdm_cfg cdm_cfg;
+	struct sde_hw_pingpong *hw_pp;
+	struct sde_kms *sde_kms;
+	struct drm_display_mode cached_mode;
+	struct sde_misr_params *misr_map;
+	enum sde_enc_split_role split_role;
+	enum sde_intf_mode intf_mode;
+	enum sde_intf intf_idx;
+	spinlock_t *enc_spinlock;
+	enum sde_enc_enable_state enable_state;
+	atomic_t vblank_refcount;
+	atomic_t vsync_cnt;
+	atomic_t underrun_cnt;
+	atomic_t pending_kickoff_cnt;
+	wait_queue_head_t pending_kickoff_wq;
+};
+
+static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys)
+{
+	return atomic_inc_return(&phys->pending_kickoff_cnt);
+}
+
+/**
+ * struct sde_encoder_phys_vid - sub-class of sde_encoder_phys to handle video
+ *	mode specific operations
+ * @base:	Baseclass physical encoder structure
+ * @irq_idx:	IRQ interface lookup index
+ * @irq_cb:	interrupt callback
+ * @hw_intf:	Hardware interface to the intf registers
+ */
+struct sde_encoder_phys_vid {
+	struct sde_encoder_phys base;
+	int irq_idx[INTR_IDX_MAX];
+	struct sde_irq_callback irq_cb[INTR_IDX_MAX];
+	struct sde_hw_intf *hw_intf;
+};
+
+/**
+ * struct sde_encoder_phys_cmd - sub-class of sde_encoder_phys to handle command
+ *	mode specific operations
+ * @base:	Baseclass physical encoder structure
+ * @intf_idx:	Intf Block index used by this phys encoder
+ * @stream_sel:	Stream selection for multi-stream interfaces
+ * @pp_rd_ptr_irq_idx:	IRQ signifying panel's frame read pointer
+ *			For CMD encoders, VBLANK is driven by the PP RD Done IRQ
+ * @pp_tx_done_irq_idx:	IRQ signifying frame transmission to panel complete
+ * @irq_cb:	interrupt callback
+ */
+struct sde_encoder_phys_cmd {
+	struct sde_encoder_phys base;
+	int intf_idx;
+	int stream_sel;
+	int irq_idx[INTR_IDX_MAX];
+	struct sde_irq_callback irq_cb[INTR_IDX_MAX];
+};
+
+/**
+ * struct sde_encoder_phys_wb - sub-class of sde_encoder_phys to handle
+ *	writeback specific operations
+ * @base:		Baseclass physical encoder structure
+ * @hw_wb:		Hardware interface to the wb registers
+ * @irq_idx:		IRQ interface lookup index
+ * @wbdone_timeout:	Timeout value for writeback done in msec
+ * @bypass_irqreg:	Bypass irq register/unregister if non-zero
+ * @wbdone_complete:	for wbdone irq synchronization
+ * @wb_cfg:		Writeback hardware configuration
+ * @intf_cfg:		Interface hardware configuration
+ * @wb_roi:		Writeback region-of-interest
+ * @wb_fmt:		Writeback pixel format
+ * @frame_count:	Counter of completed writeback operations
+ * @kickoff_count:	Counter of issued writeback operations
+ * @mmu_id:		mmu identifier for non-secure/secure domain
+ * @wb_dev:		Pointer to writeback device
+ * @start_time:		Start time of writeback latest request
+ * @end_time:		End time of writeback latest request
+ * @wb_name:		Name of this writeback device
+ * @debugfs_root:	Root entry of writeback debugfs
+ */
+struct sde_encoder_phys_wb {
+	struct sde_encoder_phys base;
+	struct sde_hw_wb *hw_wb;
+	int irq_idx;
+	struct sde_irq_callback irq_cb;
+	u32 wbdone_timeout;
+	u32 bypass_irqreg;
+	struct completion wbdone_complete;
+	struct sde_hw_wb_cfg wb_cfg;
+	struct sde_hw_intf_cfg intf_cfg;
+	struct sde_rect wb_roi;
+	const struct sde_format *wb_fmt;
+	u32 frame_count;
+	u32 kickoff_count;
+	int mmu_id[SDE_IOMMU_DOMAIN_MAX];
+	struct sde_wb_device *wb_dev;
+	ktime_t start_time;
+	ktime_t end_time;
+#ifdef CONFIG_DEBUG_FS
+	char wb_name[SDE_ENCODER_NAME_MAX];
+	struct dentry *debugfs_root;
+#endif
+};
+
+/**
+ * struct sde_enc_phys_init_params - initialization parameters for phys encs
+ * @sde_kms:		Pointer to the sde_kms top level
+ * @parent:		Pointer to the containing virtual encoder
+ * @parent_ops:		Callbacks exposed by the parent to the phys_enc
+ * @split_role:		Role to play in a split-panel configuration
+ * @intf_idx:		Interface index this phys_enc will control
+ * @wb_idx:		Writeback index this phys_enc will control
+ * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
+ */
+struct sde_enc_phys_init_params {
+	struct sde_kms *sde_kms;
+	struct drm_encoder *parent;
+	struct sde_encoder_virt_ops parent_ops;
+	enum sde_enc_split_role split_role;
+	enum sde_intf intf_idx;
+	enum sde_wb wb_idx;
+	spinlock_t *enc_spinlock;
+};
+
+/**
+ * sde_encoder_phys_vid_init - Construct a new video mode physical encoder
+ * @p:	Pointer to init params structure
+ * Return: Error code or newly allocated encoder
+ */
+struct sde_encoder_phys *sde_encoder_phys_vid_init(
+		struct sde_enc_phys_init_params *p);
+
+/**
+ * sde_encoder_phys_cmd_init - Construct a new command mode physical encoder
+ * @p:	Pointer to init params structure
+ * Return: Error code or newly allocated encoder
+ */
+struct sde_encoder_phys *sde_encoder_phys_cmd_init(
+		struct sde_enc_phys_init_params *p);
+
+/**
+ * sde_encoder_phys_wb_init - Construct a new writeback physical encoder
+ * @p:	Pointer to init params structure
+ * Return: Error code or newly allocated encoder
+ */
+#ifdef CONFIG_DRM_SDE_WB
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_enc_phys_init_params *p);
+#else
+static inline
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_enc_phys_init_params *p)
+{
+	return NULL;
+}
+#endif
+
+void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, const struct sde_format *format,
+		struct sde_rect *wb_roi);
+
+/**
+ * sde_encoder_helper_trigger_start - control start helper function
+ *	This helper function may be optionally specified by physical
+ *	encoders if they require ctl_start triggering.
+ * @phys_enc: Pointer to physical encoder structure
+ */
+void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc);
+
+/**
+ * sde_encoder_helper_wait_event_timeout - wait for event with timeout
+ *	taking into account that jiffies may jump between reads leading to
+ *	incorrectly detected timeouts. Prevent failure in this scenario by
+ *	making sure that elapsed time during wait is valid.
+ * @drm_id: drm object id for logging
+ * @hw_id: hw instance id for logging
+ * @wq: wait queue structure
+ * @cnt: atomic counter to wait on
+ * @timeout_ms: timeout value in milliseconds
+ */
+int sde_encoder_helper_wait_event_timeout(
+		int32_t drm_id,
+		int32_t hw_id,
+		wait_queue_head_t *wq,
+		atomic_t *cnt,
+		s64 timeout_ms);
+
+
+static inline enum sde_3d_blend_mode sde_encoder_helper_get_3d_blend_mode(
+		struct sde_encoder_phys *phys_enc)
+{
+	enum sde_rm_topology_name topology;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	if (phys_enc->split_role == ENC_ROLE_SOLO &&
+			topology == SDE_RM_TOPOLOGY_DUALPIPEMERGE)
+		return BLEND_3D_H_ROW_INT;
+
+	return BLEND_3D_NONE;
+}
+
+/**
+ * sde_encoder_helper_split_config - split display configuration helper function
+ *	This helper function may be used by physical encoders to configure
+ *	the split display related registers.
+ * @phys_enc: Pointer to physical encoder structure
+ * @interface: enum sde_intf setting
+ */
+void sde_encoder_helper_split_config(
+		struct sde_encoder_phys *phys_enc,
+		enum sde_intf interface);
+
+#endif /* __sde_encoder_phys_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
new file mode 100644
index 0000000000000000000000000000000000000000..76d6fe0e30235ec07eff0c6fb3cf6c5dfec8f526
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include "sde_encoder_phys.h"
+#include "sde_hw_interrupts.h"
+#include "sde_core_irq.h"
+#include "sde_formats.h"
+
+#define SDE_DEBUG_CMDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
+		(e) && (e)->base.parent ? \
+		(e)->base.parent->base.id : -1, \
+		(e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+
+#define SDE_ERROR_CMDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
+		(e) && (e)->base.parent ? \
+		(e)->base.parent->base.id : -1, \
+		(e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+
+#define to_sde_encoder_phys_cmd(x) \
+	container_of(x, struct sde_encoder_phys_cmd, base)
+
+/*
+ * Tearcheck sync start and continue thresholds are empirically found
+ * based on common panels In the future, may want to allow panels to override
+ * these default values
+ */
+#define DEFAULT_TEARCHECK_SYNC_THRESH_START	4
+#define DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE	4
+
+static inline bool sde_encoder_phys_cmd_is_master(
+		struct sde_encoder_phys *phys_enc)
+{
+	return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
+}
+
+static bool sde_encoder_phys_cmd_mode_fixup(
+		struct sde_encoder_phys *phys_enc,
+		const struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	if (phys_enc)
+		SDE_DEBUG_CMDENC(to_sde_encoder_phys_cmd(phys_enc), "\n");
+	return true;
+}
+
+static void sde_encoder_phys_cmd_mode_set(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	struct sde_rm *rm = &phys_enc->sde_kms->rm;
+	struct sde_rm_hw_iter iter;
+	int i, instance;
+
+	if (!phys_enc || !mode || !adj_mode) {
+		SDE_ERROR("invalid arg(s), enc %d mode %d adj_mode %d\n",
+				phys_enc != 0, mode != 0, adj_mode != 0);
+		return;
+	}
+	phys_enc->cached_mode = *adj_mode;
+	SDE_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
+	drm_mode_debug_printmodeline(adj_mode);
+
+	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
+
+	/* Retrieve previously allocated HW Resources. Shouldn't fail */
+	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
+	for (i = 0; i <= instance; i++) {
+		if (sde_rm_get_hw(rm, &iter))
+			phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
+	}
+
+	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
+		SDE_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
+				PTR_ERR(phys_enc->hw_ctl));
+		phys_enc->hw_ctl = NULL;
+		return;
+	}
+}
+
+static void sde_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_cmd *cmd_enc = arg;
+	struct sde_encoder_phys *phys_enc;
+	unsigned long lock_flags;
+	int new_cnt;
+
+	if (!cmd_enc)
+		return;
+
+	phys_enc = &cmd_enc->base;
+
+	/* notify all synchronous clients first, then asynchronous clients */
+	if (phys_enc->parent_ops.handle_frame_done)
+		phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
+				phys_enc, SDE_ENCODER_FRAME_EVENT_DONE);
+
+	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+	new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
+	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+
+	SDE_EVT32_IRQ(DRMID(phys_enc->parent),
+			phys_enc->hw_pp->idx - PINGPONG_0, new_cnt);
+
+	/* Signal any waiting atomic commit thread */
+	wake_up_all(&phys_enc->pending_kickoff_wq);
+}
+
+static void sde_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_cmd *cmd_enc = arg;
+	struct sde_encoder_phys *phys_enc = &cmd_enc->base;
+
+	if (!cmd_enc)
+		return;
+
+	if (phys_enc->parent_ops.handle_vblank_virt)
+		phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
+			phys_enc);
+}
+
+static bool _sde_encoder_phys_is_ppsplit_slave(
+		struct sde_encoder_phys *phys_enc)
+{
+	enum sde_rm_topology_name topology;
+
+	if (!phys_enc)
+		return false;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	if (topology == SDE_RM_TOPOLOGY_PPSPLIT &&
+			phys_enc->split_role == ENC_ROLE_SLAVE)
+		return true;
+
+	return false;
+}
+
+static int _sde_encoder_phys_cmd_wait_for_idle(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+			to_sde_encoder_phys_cmd(phys_enc);
+	u32 irq_status;
+	int ret;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	/* slave encoder doesn't enable for ppsplit */
+	if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
+		return 0;
+
+	/* return EWOULDBLOCK since we know the wait isn't necessary */
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR_CMDENC(cmd_enc, "encoder is disabled\n");
+		return -EWOULDBLOCK;
+	}
+
+	/* wait for previous kickoff to complete */
+	ret = sde_encoder_helper_wait_event_timeout(
+			DRMID(phys_enc->parent),
+			phys_enc->hw_pp->idx - PINGPONG_0,
+			&phys_enc->pending_kickoff_wq,
+			&phys_enc->pending_kickoff_cnt,
+			KICKOFF_TIMEOUT_MS);
+	if (ret <= 0) {
+		irq_status = sde_core_irq_read(phys_enc->sde_kms,
+				INTR_IDX_PINGPONG, true);
+		if (irq_status) {
+			SDE_EVT32(DRMID(phys_enc->parent),
+					phys_enc->hw_pp->idx - PINGPONG_0);
+			SDE_DEBUG_CMDENC(cmd_enc,
+					"pp:%d done but irq not triggered\n",
+					phys_enc->hw_pp->idx - PINGPONG_0);
+			sde_encoder_phys_cmd_pp_tx_done_irq(cmd_enc,
+					INTR_IDX_PINGPONG);
+			ret = 0;
+		} else {
+			SDE_EVT32(DRMID(phys_enc->parent),
+					phys_enc->hw_pp->idx - PINGPONG_0);
+			SDE_ERROR_CMDENC(cmd_enc, "pp:%d kickoff timed out\n",
+					phys_enc->hw_pp->idx - PINGPONG_0);
+			if (phys_enc->parent_ops.handle_frame_done)
+				phys_enc->parent_ops.handle_frame_done(
+						phys_enc->parent, phys_enc,
+						SDE_ENCODER_FRAME_EVENT_ERROR);
+			ret = -ETIMEDOUT;
+		}
+	} else {
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static void sde_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_cmd *cmd_enc = arg;
+	struct sde_encoder_phys *phys_enc;
+
+	if (!cmd_enc)
+		return;
+
+	phys_enc = &cmd_enc->base;
+	if (phys_enc->parent_ops.handle_underrun_virt)
+		phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
+			phys_enc);
+}
+
+static int sde_encoder_phys_cmd_register_irq(struct sde_encoder_phys *phys_enc,
+	enum sde_intr_type intr_type, int idx,
+	void (*irq_func)(void *, int), const char *irq_name)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+			to_sde_encoder_phys_cmd(phys_enc);
+	int ret = 0;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	cmd_enc->irq_idx[idx] = sde_core_irq_idx_lookup(phys_enc->sde_kms,
+			intr_type, phys_enc->hw_pp->idx);
+	if (cmd_enc->irq_idx[idx] < 0) {
+		SDE_ERROR_CMDENC(cmd_enc,
+			"failed to lookup IRQ index for %s with pp=%d\n",
+			irq_name,
+			phys_enc->hw_pp->idx - PINGPONG_0);
+		return -EINVAL;
+	}
+
+	cmd_enc->irq_cb[idx].func = irq_func;
+	cmd_enc->irq_cb[idx].arg = cmd_enc;
+	ret = sde_core_irq_register_callback(phys_enc->sde_kms,
+			cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
+	if (ret) {
+		SDE_ERROR_CMDENC(cmd_enc,
+				"failed to register IRQ callback %s\n",
+				irq_name);
+		return ret;
+	}
+
+	ret = sde_core_irq_enable(phys_enc->sde_kms, &cmd_enc->irq_idx[idx], 1);
+	if (ret) {
+		SDE_ERROR_CMDENC(cmd_enc,
+			"failed to enable IRQ for %s, pp %d, irq_idx %d\n",
+			irq_name,
+			phys_enc->hw_pp->idx - PINGPONG_0,
+			cmd_enc->irq_idx[idx]);
+		cmd_enc->irq_idx[idx] = -EINVAL;
+
+		/* Unregister callback on IRQ enable failure */
+		sde_core_irq_unregister_callback(phys_enc->sde_kms,
+				cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
+		return ret;
+	}
+
+	SDE_DEBUG_CMDENC(cmd_enc, "registered IRQ %s for pp %d, irq_idx %d\n",
+			irq_name,
+			phys_enc->hw_pp->idx - PINGPONG_0,
+			cmd_enc->irq_idx[idx]);
+
+	return ret;
+}
+
+static int sde_encoder_phys_cmd_unregister_irq(
+		struct sde_encoder_phys *phys_enc, int idx)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+			to_sde_encoder_phys_cmd(phys_enc);
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	sde_core_irq_disable(phys_enc->sde_kms, &cmd_enc->irq_idx[idx], 1);
+	sde_core_irq_unregister_callback(phys_enc->sde_kms,
+			cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
+
+	SDE_DEBUG_CMDENC(cmd_enc, "unregistered IRQ for pp %d, irq_idx %d\n",
+			phys_enc->hw_pp->idx - PINGPONG_0,
+			cmd_enc->irq_idx[idx]);
+
+	return 0;
+}
+
+static void sde_encoder_phys_cmd_tearcheck_config(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	struct sde_hw_tear_check tc_cfg = { 0 };
+	struct drm_display_mode *mode = &phys_enc->cached_mode;
+	bool tc_enable = true;
+	u32 vsync_hz;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
+
+	if (!phys_enc->hw_pp->ops.setup_tearcheck ||
+		!phys_enc->hw_pp->ops.enable_tearcheck) {
+		SDE_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
+		return;
+	}
+
+	sde_kms = phys_enc->sde_kms;
+	priv = sde_kms->dev->dev_private;
+	/*
+	 * TE default: dsi byte clock calculated base on 70 fps;
+	 * around 14 ms to complete a kickoff cycle if te disabled;
+	 * vclk_line base on 60 fps; write is faster than read;
+	 * init == start == rdptr;
+	 *
+	 * vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
+	 * frequency divided by the no. of rows (lines) in the LCDpanel.
+	 */
+	vsync_hz = sde_power_clk_get_rate(&priv->phandle, "vsync_clk");
+	if (!vsync_hz) {
+		SDE_DEBUG_CMDENC(cmd_enc, "invalid vsync clock rate\n");
+		return;
+	}
+
+	tc_cfg.vsync_count = vsync_hz / (mode->vtotal * mode->vrefresh);
+	tc_cfg.hw_vsync_mode = 1;
+
+	/*
+	 * By setting sync_cfg_height to near max register value, we essentially
+	 * disable sde hw generated TE signal, since hw TE will arrive first.
+	 * Only caveat is if due to error, we hit wrap-around.
+	 */
+	tc_cfg.sync_cfg_height = 0xFFF0;
+	tc_cfg.vsync_init_val = mode->vdisplay;
+	tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START;
+	tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
+	tc_cfg.start_pos = mode->vdisplay;
+	tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
+
+	SDE_DEBUG_CMDENC(cmd_enc,
+		"tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
+		phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
+		mode->vtotal, mode->vrefresh);
+	SDE_DEBUG_CMDENC(cmd_enc,
+		"tc %d enable %u start_pos %u rd_ptr_irq %u\n",
+		phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
+		tc_cfg.rd_ptr_irq);
+	SDE_DEBUG_CMDENC(cmd_enc,
+		"tc %d hw_vsync_mode %u vsync_count %u vsync_init_val %u\n",
+		phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode,
+		tc_cfg.vsync_count, tc_cfg.vsync_init_val);
+	SDE_DEBUG_CMDENC(cmd_enc,
+		"tc %d cfgheight %u thresh_start %u thresh_cont %u\n",
+		phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height,
+		tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
+
+	phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg);
+	phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
+}
+
+static void sde_encoder_phys_cmd_pingpong_config(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	struct sde_hw_intf_cfg intf_cfg = { 0 };
+
+	if (!phys_enc || !phys_enc->hw_ctl ||
+			!phys_enc->hw_ctl->ops.setup_intf_cfg) {
+		SDE_ERROR("invalid arg(s), enc %d\n", phys_enc != 0);
+		return;
+	}
+
+	SDE_DEBUG_CMDENC(cmd_enc, "pp %d, enabling mode:\n",
+			phys_enc->hw_pp->idx - PINGPONG_0);
+	drm_mode_debug_printmodeline(&phys_enc->cached_mode);
+
+	intf_cfg.intf = cmd_enc->intf_idx;
+	intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
+	intf_cfg.stream_sel = cmd_enc->stream_sel;
+	intf_cfg.mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
+
+	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+
+	sde_encoder_phys_cmd_tearcheck_config(phys_enc);
+}
+
+static bool sde_encoder_phys_cmd_needs_single_flush(
+		struct sde_encoder_phys *phys_enc)
+{
+	enum sde_rm_topology_name topology;
+
+	if (!phys_enc)
+		return false;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	return topology == SDE_RM_TOPOLOGY_PPSPLIT;
+}
+
+static int sde_encoder_phys_cmd_control_vblank_irq(
+		struct sde_encoder_phys *phys_enc,
+		bool enable)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	int ret = 0;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	/* Slave encoders don't report vblank */
+	if (!sde_encoder_phys_cmd_is_master(phys_enc))
+		goto end;
+
+	SDE_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
+			__builtin_return_address(0),
+			enable, atomic_read(&phys_enc->vblank_refcount));
+
+	SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
+			enable, atomic_read(&phys_enc->vblank_refcount));
+
+	if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
+		ret = sde_encoder_phys_cmd_register_irq(phys_enc,
+				SDE_IRQ_TYPE_PING_PONG_RD_PTR,
+				INTR_IDX_RDPTR,
+				sde_encoder_phys_cmd_pp_rd_ptr_irq,
+				"pp_rd_ptr");
+	else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
+		ret = sde_encoder_phys_cmd_unregister_irq(phys_enc,
+				INTR_IDX_RDPTR);
+
+end:
+	if (ret)
+		SDE_ERROR_CMDENC(cmd_enc,
+				"control vblank irq error %d, enable %d\n",
+				ret, enable);
+
+	return ret;
+}
+
+static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	struct sde_hw_ctl *ctl;
+	u32 flush_mask;
+	int ret;
+
+	if (!phys_enc || !phys_enc->hw_ctl) {
+		SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
+		return;
+	}
+	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
+
+	if (phys_enc->enable_state == SDE_ENC_ENABLED) {
+		SDE_ERROR("already enabled\n");
+		return;
+	}
+
+	sde_encoder_helper_split_config(phys_enc, cmd_enc->intf_idx);
+
+	sde_encoder_phys_cmd_pingpong_config(phys_enc);
+
+	if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
+		goto update_flush;
+
+	/* Both master and slave need to register for pp_tx_done */
+	ret = sde_encoder_phys_cmd_register_irq(phys_enc,
+			SDE_IRQ_TYPE_PING_PONG_COMP,
+			INTR_IDX_PINGPONG,
+			sde_encoder_phys_cmd_pp_tx_done_irq,
+			"pp_tx_done");
+	if (ret)
+		return;
+
+	ret = sde_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
+	if (ret) {
+		sde_encoder_phys_cmd_unregister_irq(phys_enc,
+				INTR_IDX_PINGPONG);
+		return;
+	}
+
+	ret = sde_encoder_phys_cmd_register_irq(phys_enc,
+			SDE_IRQ_TYPE_INTF_UNDER_RUN,
+			INTR_IDX_UNDERRUN,
+			sde_encoder_phys_cmd_underrun_irq,
+			"underrun");
+	if (ret) {
+		sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
+		sde_encoder_phys_cmd_unregister_irq(phys_enc,
+				INTR_IDX_PINGPONG);
+		return;
+	}
+
+update_flush:
+	ctl = phys_enc->hw_ctl;
+	ctl->ops.get_bitmask_intf(ctl, &flush_mask, cmd_enc->intf_idx);
+	ctl->ops.update_pending_flush(ctl, flush_mask);
+	phys_enc->enable_state = SDE_ENC_ENABLED;
+
+	SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
+			ctl->idx - CTL_0, flush_mask);
+}
+
+static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+	int ret;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
+
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR_CMDENC(cmd_enc, "already disabled\n");
+		return;
+	}
+
+	SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0);
+
+	if (!_sde_encoder_phys_is_ppsplit_slave(phys_enc)) {
+		ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
+		if (ret) {
+			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+			SDE_ERROR_CMDENC(cmd_enc,
+					"pp %d failed wait for idle, %d\n",
+					phys_enc->hw_pp->idx - PINGPONG_0, ret);
+			SDE_EVT32(DRMID(phys_enc->parent),
+					phys_enc->hw_pp->idx - PINGPONG_0, ret);
+		}
+
+		sde_encoder_phys_cmd_unregister_irq(
+				phys_enc, INTR_IDX_UNDERRUN);
+		sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
+		sde_encoder_phys_cmd_unregister_irq(
+				phys_enc, INTR_IDX_PINGPONG);
+	}
+
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+
+	if (atomic_read(&phys_enc->vblank_refcount))
+		SDE_ERROR("enc:%d role:%d invalid vblank refcount %d\n",
+				phys_enc->parent->base.id,
+				phys_enc->split_role,
+				atomic_read(&phys_enc->vblank_refcount));
+}
+
+static void sde_encoder_phys_cmd_destroy(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	kfree(cmd_enc);
+}
+
+static void sde_encoder_phys_cmd_get_hw_resources(
+		struct sde_encoder_phys *phys_enc,
+		struct sde_encoder_hw_resources *hw_res,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+		to_sde_encoder_phys_cmd(phys_enc);
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	SDE_DEBUG_CMDENC(cmd_enc, "\n");
+	hw_res->intfs[cmd_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
+}
+
+static int sde_encoder_phys_cmd_wait_for_commit_done(
+		struct sde_encoder_phys *phys_enc)
+{
+	/*
+	 * Since ctl_start "commits" the transaction to hardware, and the
+	 * tearcheck block takes it from there, there is no need to have a
+	 * separate wait for committed, a la wait-for-vsync in video mode
+	 */
+
+	return 0;
+}
+
+static void sde_encoder_phys_cmd_prepare_for_kickoff(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_cmd *cmd_enc =
+			to_sde_encoder_phys_cmd(phys_enc);
+	int ret;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
+	SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0);
+
+	/*
+	 * Mark kickoff request as outstanding. If there are more than one,
+	 * outstanding, then we have to wait for the previous one to complete
+	 */
+	ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
+	if (ret) {
+		/* force pending_kickoff_cnt 0 to discard failed kickoff */
+		atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+		SDE_EVT32(DRMID(phys_enc->parent),
+				phys_enc->hw_pp->idx - PINGPONG_0);
+		SDE_ERROR("failed wait_for_idle: %d\n", ret);
+	}
+}
+
+static void sde_encoder_phys_cmd_init_ops(
+		struct sde_encoder_phys_ops *ops)
+{
+	ops->is_master = sde_encoder_phys_cmd_is_master;
+	ops->mode_set = sde_encoder_phys_cmd_mode_set;
+	ops->mode_fixup = sde_encoder_phys_cmd_mode_fixup;
+	ops->enable = sde_encoder_phys_cmd_enable;
+	ops->disable = sde_encoder_phys_cmd_disable;
+	ops->destroy = sde_encoder_phys_cmd_destroy;
+	ops->get_hw_resources = sde_encoder_phys_cmd_get_hw_resources;
+	ops->control_vblank_irq = sde_encoder_phys_cmd_control_vblank_irq;
+	ops->wait_for_commit_done = sde_encoder_phys_cmd_wait_for_commit_done;
+	ops->prepare_for_kickoff = sde_encoder_phys_cmd_prepare_for_kickoff;
+	ops->trigger_start = sde_encoder_helper_trigger_start;
+	ops->needs_single_flush = sde_encoder_phys_cmd_needs_single_flush;
+}
+
+struct sde_encoder_phys *sde_encoder_phys_cmd_init(
+		struct sde_enc_phys_init_params *p)
+{
+	struct sde_encoder_phys *phys_enc = NULL;
+	struct sde_encoder_phys_cmd *cmd_enc = NULL;
+	struct sde_hw_mdp *hw_mdp;
+	int i, ret = 0;
+
+	SDE_DEBUG("intf %d\n", p->intf_idx - INTF_0);
+
+	cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
+	if (!cmd_enc) {
+		ret = -ENOMEM;
+		SDE_ERROR("failed to allocate\n");
+		goto fail;
+	}
+	phys_enc = &cmd_enc->base;
+
+	hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
+	if (IS_ERR_OR_NULL(hw_mdp)) {
+		ret = PTR_ERR(hw_mdp);
+		SDE_ERROR("failed to get mdptop\n");
+		goto fail_mdp_init;
+	}
+	phys_enc->hw_mdptop = hw_mdp;
+
+	cmd_enc->intf_idx = p->intf_idx;
+	phys_enc->intf_idx = p->intf_idx;
+
+	sde_encoder_phys_cmd_init_ops(&phys_enc->ops);
+	phys_enc->parent = p->parent;
+	phys_enc->parent_ops = p->parent_ops;
+	phys_enc->sde_kms = p->sde_kms;
+	phys_enc->split_role = p->split_role;
+	phys_enc->intf_mode = INTF_MODE_CMD;
+	phys_enc->enc_spinlock = p->enc_spinlock;
+	cmd_enc->stream_sel = 0;
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+	for (i = 0; i < INTR_IDX_MAX; i++)
+		INIT_LIST_HEAD(&cmd_enc->irq_cb[i].list);
+	atomic_set(&phys_enc->vblank_refcount, 0);
+	atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+	init_waitqueue_head(&phys_enc->pending_kickoff_wq);
+
+	SDE_DEBUG_CMDENC(cmd_enc, "created\n");
+
+	return phys_enc;
+
+fail_mdp_init:
+	kfree(cmd_enc);
+fail:
+	return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
new file mode 100644
index 0000000000000000000000000000000000000000..e61ff97d2ca435d8ae4c2af2e501e5382a783d42
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -0,0 +1,872 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include "sde_encoder_phys.h"
+#include "sde_hw_interrupts.h"
+#include "sde_core_irq.h"
+#include "sde_formats.h"
+
+#define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
+		(e) && (e)->base.parent ? \
+		(e)->base.parent->base.id : -1, \
+		(e) && (e)->hw_intf ? \
+		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
+
+#define SDE_ERROR_VIDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
+		(e) && (e)->base.parent ? \
+		(e)->base.parent->base.id : -1, \
+		(e) && (e)->hw_intf ? \
+		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
+
+#define to_sde_encoder_phys_vid(x) \
+	container_of(x, struct sde_encoder_phys_vid, base)
+
+static bool sde_encoder_phys_vid_is_master(
+		struct sde_encoder_phys *phys_enc)
+{
+	bool ret = false;
+
+	if (phys_enc->split_role != ENC_ROLE_SLAVE)
+		ret = true;
+
+	return ret;
+}
+
+static void drm_mode_to_intf_timing_params(
+		const struct sde_encoder_phys_vid *vid_enc,
+		const struct drm_display_mode *mode,
+		struct intf_timing_params *timing)
+{
+	memset(timing, 0, sizeof(*timing));
+	/*
+	 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
+	 *  Active Region      Front Porch   Sync   Back Porch
+	 * <-----------------><------------><-----><----------->
+	 * <- [hv]display --->
+	 * <--------- [hv]sync_start ------>
+	 * <----------------- [hv]sync_end ------->
+	 * <---------------------------- [hv]total ------------->
+	 */
+	timing->width = mode->hdisplay;	/* active width */
+	timing->height = mode->vdisplay;	/* active height */
+	timing->xres = timing->width;
+	timing->yres = timing->height;
+	timing->h_back_porch = mode->htotal - mode->hsync_end;
+	timing->h_front_porch = mode->hsync_start - mode->hdisplay;
+	timing->v_back_porch = mode->vtotal - mode->vsync_end;
+	timing->v_front_porch = mode->vsync_start - mode->vdisplay;
+	timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
+	timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
+	timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
+	timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
+	timing->border_clr = 0;
+	timing->underflow_clr = 0xff;
+	timing->hsync_skew = mode->hskew;
+
+	/* DSI controller cannot handle active-low sync signals. */
+	if (vid_enc->hw_intf->cap->type == INTF_DSI) {
+		timing->hsync_polarity = 0;
+		timing->vsync_polarity = 0;
+	}
+
+	/*
+	 * For edp only:
+	 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
+	 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
+	 */
+	/*
+	 * if (vid_enc->hw->cap->type == INTF_EDP) {
+	 * display_v_start += mode->htotal - mode->hsync_start;
+	 * display_v_end -= mode->hsync_start - mode->hdisplay;
+	 * }
+	 */
+}
+
+static inline u32 get_horizontal_total(const struct intf_timing_params *timing)
+{
+	u32 active = timing->xres;
+	u32 inactive =
+	    timing->h_back_porch + timing->h_front_porch +
+	    timing->hsync_pulse_width;
+	return active + inactive;
+}
+
+static inline u32 get_vertical_total(const struct intf_timing_params *timing)
+{
+	u32 active = timing->yres;
+	u32 inactive =
+	    timing->v_back_porch + timing->v_front_porch +
+	    timing->vsync_pulse_width;
+	return active + inactive;
+}
+
+/*
+ * programmable_fetch_get_num_lines:
+ *	Number of fetch lines in vertical front porch
+ * @timing: Pointer to the intf timing information for the requested mode
+ *
+ * Returns the number of fetch lines in vertical front porch at which mdp
+ * can start fetching the next frame.
+ *
+ * Number of needed prefetch lines is anything that cannot be absorbed in the
+ * start of frame time (back porch + vsync pulse width).
+ *
+ * Some panels have very large VFP, however we only need a total number of
+ * lines based on the chip worst case latencies.
+ */
+static u32 programmable_fetch_get_num_lines(
+		struct sde_encoder_phys_vid *vid_enc,
+		const struct intf_timing_params *timing)
+{
+	u32 worst_case_needed_lines =
+	    vid_enc->hw_intf->cap->prog_fetch_lines_worst_case;
+	u32 start_of_frame_lines =
+	    timing->v_back_porch + timing->vsync_pulse_width;
+	u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
+	u32 actual_vfp_lines = 0;
+
+	/* Fetch must be outside active lines, otherwise undefined. */
+	if (start_of_frame_lines >= worst_case_needed_lines) {
+		SDE_DEBUG_VIDENC(vid_enc,
+				"prog fetch is not needed, large vbp+vsw\n");
+		actual_vfp_lines = 0;
+	} else if (timing->v_front_porch < needed_vfp_lines) {
+		/* Warn fetch needed, but not enough porch in panel config */
+		pr_warn_once
+			("low vbp+vfp may lead to perf issues in some cases\n");
+		SDE_DEBUG_VIDENC(vid_enc,
+				"less vfp than fetch req, using entire vfp\n");
+		actual_vfp_lines = timing->v_front_porch;
+	} else {
+		SDE_DEBUG_VIDENC(vid_enc, "room in vfp for needed prefetch\n");
+		actual_vfp_lines = needed_vfp_lines;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc,
+		"v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
+		timing->v_front_porch, timing->v_back_porch,
+		timing->vsync_pulse_width);
+	SDE_DEBUG_VIDENC(vid_enc,
+		"wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
+		worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
+
+	return actual_vfp_lines;
+}
+
+/*
+ * programmable_fetch_config: Programs HW to prefetch lines by offsetting
+ *	the start of fetch into the vertical front porch for cases where the
+ *	vsync pulse width and vertical back porch time is insufficient
+ *
+ *	Gets # of lines to pre-fetch, then calculate VSYNC counter value.
+ *	HW layer requires VSYNC counter of first pixel of tgt VFP line.
+ *
+ * @timing: Pointer to the intf timing information for the requested mode
+ */
+static void programmable_fetch_config(struct sde_encoder_phys *phys_enc,
+				      const struct intf_timing_params *timing)
+{
+	struct sde_encoder_phys_vid *vid_enc =
+		to_sde_encoder_phys_vid(phys_enc);
+	struct intf_prog_fetch f = { 0 };
+	u32 vfp_fetch_lines = 0;
+	u32 horiz_total = 0;
+	u32 vert_total = 0;
+	u32 vfp_fetch_start_vsync_counter = 0;
+	unsigned long lock_flags;
+
+	if (WARN_ON_ONCE(!vid_enc->hw_intf->ops.setup_prg_fetch))
+		return;
+
+	vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);
+	if (vfp_fetch_lines) {
+		vert_total = get_vertical_total(timing);
+		horiz_total = get_horizontal_total(timing);
+		vfp_fetch_start_vsync_counter =
+		    (vert_total - vfp_fetch_lines) * horiz_total + 1;
+		f.enable = 1;
+		f.fetch_start = vfp_fetch_start_vsync_counter;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc,
+		"vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
+		vfp_fetch_lines, vfp_fetch_start_vsync_counter);
+
+	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+	vid_enc->hw_intf->ops.setup_prg_fetch(vid_enc->hw_intf, &f);
+	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+}
+
+static bool sde_encoder_phys_vid_mode_fixup(
+		struct sde_encoder_phys *phys_enc,
+		const struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	if (phys_enc)
+		SDE_DEBUG_VIDENC(to_sde_encoder_phys_vid(phys_enc), "\n");
+
+	/*
+	 * Modifying mode has consequences when the mode comes back to us
+	 */
+	return true;
+}
+
+static void sde_encoder_phys_vid_setup_timing_engine(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_vid *vid_enc;
+	struct drm_display_mode mode;
+	struct intf_timing_params timing_params = { 0 };
+	const struct sde_format *fmt = NULL;
+	u32 fmt_fourcc = DRM_FORMAT_RGB888;
+	unsigned long lock_flags;
+	struct sde_hw_intf_cfg intf_cfg = { 0 };
+
+	if (!phys_enc || !phys_enc->hw_ctl ||
+		!phys_enc->hw_ctl->ops.setup_intf_cfg) {
+		SDE_ERROR("invalid encoder %d\n", phys_enc != 0);
+		return;
+	}
+
+	mode = phys_enc->cached_mode;
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	if (!vid_enc->hw_intf->ops.setup_timing_gen) {
+		SDE_ERROR("timing engine setup is not supported\n");
+		return;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc, "enabling mode:\n");
+	drm_mode_debug_printmodeline(&mode);
+
+	if (phys_enc->split_role != ENC_ROLE_SOLO) {
+		mode.hdisplay >>= 1;
+		mode.htotal >>= 1;
+		mode.hsync_start >>= 1;
+		mode.hsync_end >>= 1;
+
+		SDE_DEBUG_VIDENC(vid_enc,
+			"split_role %d, halve horizontal %d %d %d %d\n",
+			phys_enc->split_role,
+			mode.hdisplay, mode.htotal,
+			mode.hsync_start, mode.hsync_end);
+	}
+
+	drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);
+
+	fmt = sde_get_sde_format(fmt_fourcc);
+	SDE_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
+
+	intf_cfg.intf = vid_enc->hw_intf->idx;
+	intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_VID;
+	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
+	intf_cfg.mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
+
+	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+	vid_enc->hw_intf->ops.setup_timing_gen(vid_enc->hw_intf,
+			&timing_params, fmt);
+	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+
+	programmable_fetch_config(phys_enc, &timing_params);
+}
+
+static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_vid *vid_enc = arg;
+	struct sde_encoder_phys *phys_enc;
+	unsigned long lock_flags;
+	int new_cnt;
+
+	if (!vid_enc)
+		return;
+
+	phys_enc = &vid_enc->base;
+	if (phys_enc->parent_ops.handle_vblank_virt)
+		phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
+				phys_enc);
+
+	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+	new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
+	SDE_EVT32_IRQ(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
+			new_cnt);
+	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+
+	/* Signal any waiting atomic commit thread */
+	wake_up_all(&phys_enc->pending_kickoff_wq);
+}
+
+static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_vid *vid_enc = arg;
+	struct sde_encoder_phys *phys_enc;
+
+	if (!vid_enc)
+		return;
+
+	phys_enc = &vid_enc->base;
+	if (phys_enc->parent_ops.handle_underrun_virt)
+		phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
+			phys_enc);
+}
+
+static bool sde_encoder_phys_vid_needs_single_flush(
+		struct sde_encoder_phys *phys_enc)
+{
+	return phys_enc && phys_enc->split_role != ENC_ROLE_SOLO;
+}
+
+static int sde_encoder_phys_vid_register_irq(struct sde_encoder_phys *phys_enc,
+	enum sde_intr_type intr_type, int idx,
+	void (*irq_func)(void *, int), const char *irq_name)
+{
+	struct sde_encoder_phys_vid *vid_enc;
+	int ret = 0;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	vid_enc->irq_idx[idx] = sde_core_irq_idx_lookup(phys_enc->sde_kms,
+			intr_type, vid_enc->hw_intf->idx);
+	if (vid_enc->irq_idx[idx] < 0) {
+		SDE_ERROR_VIDENC(vid_enc,
+			"failed to lookup IRQ index for %s type:%d\n", irq_name,
+			intr_type);
+		return -EINVAL;
+	}
+
+	vid_enc->irq_cb[idx].func = irq_func;
+	vid_enc->irq_cb[idx].arg = vid_enc;
+	ret = sde_core_irq_register_callback(phys_enc->sde_kms,
+			vid_enc->irq_idx[idx], &vid_enc->irq_cb[idx]);
+	if (ret) {
+		SDE_ERROR_VIDENC(vid_enc,
+			"failed to register IRQ callback for %s\n", irq_name);
+		return ret;
+	}
+
+	ret = sde_core_irq_enable(phys_enc->sde_kms, &vid_enc->irq_idx[idx], 1);
+	if (ret) {
+		SDE_ERROR_VIDENC(vid_enc,
+			"enable IRQ for intr:%s failed, irq_idx %d\n",
+			irq_name, vid_enc->irq_idx[idx]);
+		vid_enc->irq_idx[idx] = -EINVAL;
+
+		/* unregister callback on IRQ enable failure */
+		sde_core_irq_unregister_callback(phys_enc->sde_kms,
+				vid_enc->irq_idx[idx], &vid_enc->irq_cb[idx]);
+		return ret;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc, "registered irq %s idx: %d\n",
+			irq_name, vid_enc->irq_idx[idx]);
+
+	return ret;
+}
+
+static int sde_encoder_phys_vid_unregister_irq(
+	struct sde_encoder_phys *phys_enc, int idx)
+{
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		goto end;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	sde_core_irq_disable(phys_enc->sde_kms, &vid_enc->irq_idx[idx], 1);
+
+	sde_core_irq_unregister_callback(phys_enc->sde_kms,
+			vid_enc->irq_idx[idx], &vid_enc->irq_cb[idx]);
+
+	SDE_DEBUG_VIDENC(vid_enc, "unregistered %d\n", vid_enc->irq_idx[idx]);
+
+end:
+	return 0;
+}
+
+static void sde_encoder_phys_vid_mode_set(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	struct sde_rm *rm;
+	struct sde_rm_hw_iter iter;
+	int i, instance;
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc || !phys_enc->sde_kms) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	rm = &phys_enc->sde_kms->rm;
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	phys_enc->cached_mode = *adj_mode;
+	SDE_DEBUG_VIDENC(vid_enc, "caching mode:\n");
+	drm_mode_debug_printmodeline(adj_mode);
+
+	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
+
+	/* Retrieve previously allocated HW Resources. Shouldn't fail */
+	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
+	for (i = 0; i <= instance; i++) {
+		if (sde_rm_get_hw(rm, &iter))
+			phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
+	}
+	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
+		SDE_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
+				PTR_ERR(phys_enc->hw_ctl));
+		phys_enc->hw_ctl = NULL;
+		return;
+	}
+}
+
+static int sde_encoder_phys_vid_control_vblank_irq(
+		struct sde_encoder_phys *phys_enc,
+		bool enable)
+{
+	int ret = 0;
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+
+	/* Slave encoders don't report vblank */
+	if (!sde_encoder_phys_vid_is_master(phys_enc))
+		return 0;
+
+	SDE_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
+			__builtin_return_address(0),
+			enable, atomic_read(&phys_enc->vblank_refcount));
+
+	SDE_EVT32(DRMID(phys_enc->parent), enable,
+			atomic_read(&phys_enc->vblank_refcount));
+
+	if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
+		ret = sde_encoder_phys_vid_register_irq(phys_enc,
+			SDE_IRQ_TYPE_INTF_VSYNC,
+			INTR_IDX_VSYNC,
+			sde_encoder_phys_vid_vblank_irq, "vsync_irq");
+	else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
+		ret = sde_encoder_phys_vid_unregister_irq(phys_enc,
+			INTR_IDX_VSYNC);
+
+	if (ret)
+		SDE_ERROR_VIDENC(vid_enc,
+				"control vblank irq error %d, enable %d\n",
+				ret, enable);
+
+	return ret;
+}
+
+static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
+{
+	struct msm_drm_private *priv;
+	struct sde_encoder_phys_vid *vid_enc;
+	struct sde_hw_intf *intf;
+	struct sde_hw_ctl *ctl;
+	u32 flush_mask = 0;
+	int ret;
+
+	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
+			!phys_enc->parent->dev->dev_private) {
+		SDE_ERROR("invalid encoder/device\n");
+		return;
+	}
+	priv = phys_enc->parent->dev->dev_private;
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	intf = vid_enc->hw_intf;
+	ctl = phys_enc->hw_ctl;
+	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
+		SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
+				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+		return;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc, "\n");
+
+	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
+		return;
+
+	sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+			phys_enc->sde_kms->core_client, true);
+
+	sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);
+
+	sde_encoder_phys_vid_setup_timing_engine(phys_enc);
+	ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
+	if (ret)
+		goto end;
+
+	ret = sde_encoder_phys_vid_register_irq(phys_enc,
+		SDE_IRQ_TYPE_INTF_UNDER_RUN,
+		INTR_IDX_UNDERRUN,
+		sde_encoder_phys_vid_underrun_irq, "underrun");
+	if (ret) {
+		sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
+		goto end;
+	}
+
+	ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx);
+	ctl->ops.update_pending_flush(ctl, flush_mask);
+
+	SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d flush_mask %x\n",
+		ctl->idx - CTL_0, flush_mask);
+
+	/* ctl_flush & timing engine enable will be triggered by framework */
+	if (phys_enc->enable_state == SDE_ENC_DISABLED)
+		phys_enc->enable_state = SDE_ENC_ENABLING;
+
+end:
+	return;
+}
+
+static void sde_encoder_phys_vid_destroy(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	SDE_DEBUG_VIDENC(vid_enc, "\n");
+	kfree(vid_enc);
+}
+
+static void sde_encoder_phys_vid_get_hw_resources(
+		struct sde_encoder_phys *phys_enc,
+		struct sde_encoder_hw_resources *hw_res,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc || !hw_res) {
+		SDE_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
+				phys_enc != 0, hw_res != 0, conn_state != 0);
+		return;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	if (!vid_enc->hw_intf) {
+		SDE_ERROR("invalid arg(s), hw_intf\n");
+		return;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc, "\n");
+	hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
+}
+
+static int sde_encoder_phys_vid_wait_for_vblank(
+		struct sde_encoder_phys *phys_enc, bool notify)
+{
+	struct sde_encoder_phys_vid *vid_enc =
+			to_sde_encoder_phys_vid(phys_enc);
+	u32 irq_status;
+	int ret;
+
+	if (!sde_encoder_phys_vid_is_master(phys_enc)) {
+		/* always signal done for slave video encoder */
+		if (notify && phys_enc->parent_ops.handle_frame_done)
+			phys_enc->parent_ops.handle_frame_done(
+					phys_enc->parent, phys_enc,
+					SDE_ENCODER_FRAME_EVENT_DONE);
+		return 0;
+	}
+
+	if (phys_enc->enable_state != SDE_ENC_ENABLED) {
+		SDE_ERROR("encoder not enabled\n");
+		return -EWOULDBLOCK;
+	}
+
+	SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
+			SDE_EVTLOG_FUNC_ENTRY);
+
+	/* Wait for kickoff to complete */
+	ret = sde_encoder_helper_wait_event_timeout(
+			DRMID(phys_enc->parent),
+			vid_enc->hw_intf->idx - INTF_0,
+			&phys_enc->pending_kickoff_wq,
+			&phys_enc->pending_kickoff_cnt,
+			KICKOFF_TIMEOUT_MS);
+	if (ret <= 0) {
+		irq_status = sde_core_irq_read(phys_enc->sde_kms,
+				INTR_IDX_VSYNC, true);
+		if (irq_status) {
+			SDE_EVT32(DRMID(phys_enc->parent),
+					vid_enc->hw_intf->idx - INTF_0);
+			SDE_DEBUG_VIDENC(vid_enc, "done, irq not triggered\n");
+			if (notify && phys_enc->parent_ops.handle_frame_done)
+				phys_enc->parent_ops.handle_frame_done(
+						phys_enc->parent, phys_enc,
+						SDE_ENCODER_FRAME_EVENT_DONE);
+			sde_encoder_phys_vid_vblank_irq(vid_enc,
+					INTR_IDX_VSYNC);
+			ret = 0;
+		} else {
+			SDE_EVT32(DRMID(phys_enc->parent),
+					vid_enc->hw_intf->idx - INTF_0);
+			SDE_ERROR_VIDENC(vid_enc, "kickoff timed out\n");
+			if (notify && phys_enc->parent_ops.handle_frame_done)
+				phys_enc->parent_ops.handle_frame_done(
+						phys_enc->parent, phys_enc,
+						SDE_ENCODER_FRAME_EVENT_ERROR);
+			ret = -ETIMEDOUT;
+		}
+	} else {
+		if (notify && phys_enc->parent_ops.handle_frame_done)
+			phys_enc->parent_ops.handle_frame_done(
+					phys_enc->parent, phys_enc,
+					SDE_ENCODER_FRAME_EVENT_DONE);
+		ret = 0;
+	}
+
+	return 0;
+}
+
+static int sde_encoder_phys_vid_wait_for_commit_done(
+		struct sde_encoder_phys *phys_enc)
+{
+	int ret;
+
+	ret = sde_encoder_phys_vid_wait_for_vblank(phys_enc, true);
+
+	return ret;
+}
+
+static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
+{
+	struct msm_drm_private *priv;
+	struct sde_encoder_phys_vid *vid_enc;
+	unsigned long lock_flags;
+	int ret;
+
+	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
+			!phys_enc->parent->dev->dev_private) {
+		SDE_ERROR("invalid encoder/device\n");
+		return;
+	}
+	priv = phys_enc->parent->dev->dev_private;
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
+		SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
+				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+		return;
+	}
+
+	SDE_DEBUG_VIDENC(vid_enc, "\n");
+
+	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
+		return;
+
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR("already disabled\n");
+		return;
+	}
+
+	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+	vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 0);
+	if (sde_encoder_phys_vid_is_master(phys_enc))
+		sde_encoder_phys_inc_pending(phys_enc);
+	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+
+	/*
+	 * Wait for a vsync so we know the ENABLE=0 latched before
+	 * the (connector) source of the vsync's gets disabled,
+	 * otherwise we end up in a funny state if we re-enable
+	 * before the disable latches, which results that some of
+	 * the settings changes for the new modeset (like new
+	 * scanout buffer) don't latch properly..
+	 */
+	if (sde_encoder_phys_vid_is_master(phys_enc)) {
+		ret = sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
+		if (ret) {
+			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+			SDE_ERROR_VIDENC(vid_enc,
+					"failure waiting for disable: %d\n",
+					ret);
+			SDE_EVT32(DRMID(phys_enc->parent),
+					vid_enc->hw_intf->idx - INTF_0, ret);
+		}
+		sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
+	}
+
+	sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+			phys_enc->sde_kms->core_client, false);
+
+	if (atomic_read(&phys_enc->vblank_refcount))
+		SDE_ERROR_VIDENC(vid_enc, "invalid vblank refcount %d\n",
+				atomic_read(&phys_enc->vblank_refcount));
+
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+}
+
+static void sde_encoder_phys_vid_handle_post_kickoff(
+		struct sde_encoder_phys *phys_enc)
+{
+	unsigned long lock_flags;
+	struct sde_encoder_phys_vid *vid_enc;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	vid_enc = to_sde_encoder_phys_vid(phys_enc);
+	SDE_DEBUG_VIDENC(vid_enc, "enable_state %d\n", phys_enc->enable_state);
+
+	/*
+	 * Video mode must flush CTL before enabling timing engine
+	 * Video encoders need to turn on their interfaces now
+	 */
+	if (phys_enc->enable_state == SDE_ENC_ENABLING) {
+		SDE_EVT32(DRMID(phys_enc->parent),
+				vid_enc->hw_intf->idx - INTF_0);
+		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+		vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1);
+		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+		phys_enc->enable_state = SDE_ENC_ENABLED;
+	}
+}
+
+static void sde_encoder_phys_vid_setup_misr(struct sde_encoder_phys *phys_enc,
+			struct sde_misr_params *misr_map)
+{
+	struct sde_encoder_phys_vid *vid_enc =
+		to_sde_encoder_phys_vid(phys_enc);
+
+	if (vid_enc && vid_enc->hw_intf && vid_enc->hw_intf->ops.setup_misr)
+		vid_enc->hw_intf->ops.setup_misr(vid_enc->hw_intf, misr_map);
+}
+
+static void sde_encoder_phys_vid_collect_misr(struct sde_encoder_phys *phys_enc,
+			struct sde_misr_params *misr_map)
+{
+	struct sde_encoder_phys_vid *vid_enc =
+			to_sde_encoder_phys_vid(phys_enc);
+
+	if (vid_enc && vid_enc->hw_intf && vid_enc->hw_intf->ops.collect_misr)
+		vid_enc->hw_intf->ops.collect_misr(vid_enc->hw_intf, misr_map);
+}
+
+static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
+{
+	ops->is_master = sde_encoder_phys_vid_is_master;
+	ops->mode_set = sde_encoder_phys_vid_mode_set;
+	ops->mode_fixup = sde_encoder_phys_vid_mode_fixup;
+	ops->enable = sde_encoder_phys_vid_enable;
+	ops->disable = sde_encoder_phys_vid_disable;
+	ops->destroy = sde_encoder_phys_vid_destroy;
+	ops->get_hw_resources = sde_encoder_phys_vid_get_hw_resources;
+	ops->control_vblank_irq = sde_encoder_phys_vid_control_vblank_irq;
+	ops->wait_for_commit_done = sde_encoder_phys_vid_wait_for_commit_done;
+	ops->handle_post_kickoff = sde_encoder_phys_vid_handle_post_kickoff;
+	ops->needs_single_flush = sde_encoder_phys_vid_needs_single_flush;
+	ops->setup_misr = sde_encoder_phys_vid_setup_misr;
+	ops->collect_misr = sde_encoder_phys_vid_collect_misr;
+}
+
+struct sde_encoder_phys *sde_encoder_phys_vid_init(
+		struct sde_enc_phys_init_params *p)
+{
+	struct sde_encoder_phys *phys_enc = NULL;
+	struct sde_encoder_phys_vid *vid_enc = NULL;
+	struct sde_rm_hw_iter iter;
+	struct sde_hw_mdp *hw_mdp;
+	int i, ret = 0;
+
+	if (!p) {
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
+	if (!vid_enc) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	phys_enc = &vid_enc->base;
+
+	hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
+	if (IS_ERR_OR_NULL(hw_mdp)) {
+		ret = PTR_ERR(hw_mdp);
+		SDE_ERROR("failed to get mdptop\n");
+		goto fail;
+	}
+	phys_enc->hw_mdptop = hw_mdp;
+	phys_enc->intf_idx = p->intf_idx;
+
+	/**
+	 * hw_intf resource permanently assigned to this encoder
+	 * Other resources allocated at atomic commit time by use case
+	 */
+	sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_INTF);
+	while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
+		struct sde_hw_intf *hw_intf = (struct sde_hw_intf *)iter.hw;
+
+		if (hw_intf->idx == p->intf_idx) {
+			vid_enc->hw_intf = hw_intf;
+			break;
+		}
+	}
+
+	if (!vid_enc->hw_intf) {
+		ret = -EINVAL;
+		SDE_ERROR("failed to get hw_intf\n");
+		goto fail;
+	}
+
+	phys_enc->misr_map = kzalloc(sizeof(struct sde_misr_params),
+						GFP_KERNEL);
+	if (!phys_enc->misr_map)
+		SDE_ERROR("sde misr map allocation failed\n");
+
+	SDE_DEBUG_VIDENC(vid_enc, "\n");
+
+	sde_encoder_phys_vid_init_ops(&phys_enc->ops);
+	phys_enc->parent = p->parent;
+	phys_enc->parent_ops = p->parent_ops;
+	phys_enc->sde_kms = p->sde_kms;
+	phys_enc->split_role = p->split_role;
+	phys_enc->intf_mode = INTF_MODE_VIDEO;
+	phys_enc->enc_spinlock = p->enc_spinlock;
+	for (i = 0; i < INTR_IDX_MAX; i++)
+		INIT_LIST_HEAD(&vid_enc->irq_cb[i].list);
+	atomic_set(&phys_enc->vblank_refcount, 0);
+	atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+	init_waitqueue_head(&phys_enc->pending_kickoff_wq);
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+
+	SDE_DEBUG_VIDENC(vid_enc, "created intf idx:%d\n", p->intf_idx);
+
+	return phys_enc;
+
+fail:
+	SDE_ERROR("failed to create encoder\n");
+	if (vid_enc)
+		sde_encoder_phys_vid_destroy(phys_enc);
+
+	return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
new file mode 100644
index 0000000000000000000000000000000000000000..9943e3906df089e4af0c6207a52816c354c12fc5
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -0,0 +1,1096 @@
+/*
+ * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/debugfs.h>
+
+#include "sde_encoder_phys.h"
+#include "sde_formats.h"
+#include "sde_hw_top.h"
+#include "sde_hw_interrupts.h"
+#include "sde_core_irq.h"
+#include "sde_wb.h"
+#include "sde_vbif.h"
+
+#define to_sde_encoder_phys_wb(x) \
+	container_of(x, struct sde_encoder_phys_wb, base)
+
+#define WBID(wb_enc) ((wb_enc) ? wb_enc->wb_dev->wb_idx : -1)
+
+/**
+ * sde_encoder_phys_wb_is_master - report wb always as master encoder
+ */
+static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
+{
+	return true;
+}
+
+/**
+ * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
+ * @hw_wb:	Pointer to h/w writeback driver
+ */
+static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
+		struct sde_hw_wb *hw_wb)
+{
+	return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
+			SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
+}
+
+/**
+ * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_set_ot_limit(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_vbif_set_ot_params ot_params;
+
+	memset(&ot_params, 0, sizeof(ot_params));
+	ot_params.xin_id = hw_wb->caps->xin_id;
+	ot_params.num = hw_wb->idx - WB_0;
+	ot_params.width = wb_enc->wb_roi.w;
+	ot_params.height = wb_enc->wb_roi.h;
+	ot_params.is_wfd = true;
+	ot_params.frame_rate = phys_enc->cached_mode.vrefresh;
+	ot_params.vbif_idx = hw_wb->caps->vbif_idx;
+	ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
+	ot_params.rd = false;
+
+	sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
+}
+
+/**
+ * sde_encoder_phys_wb_set_traffic_shaper - set traffic shaper for writeback
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_set_traffic_shaper(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb_cfg *wb_cfg = &wb_enc->wb_cfg;
+
+	/* traffic shaper is only enabled for rotator */
+	wb_cfg->ts_cfg.en = false;
+}
+
+/**
+ * sde_encoder_phys_setup_cdm - setup chroma down block
+ * @phys_enc:	Pointer to physical encoder
+ * @fb:		Pointer to output framebuffer
+ * @format:	Output format
+ */
+void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, const struct sde_format *format,
+		struct sde_rect *wb_roi)
+{
+	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;
+	struct sde_hw_cdm_cfg *cdm_cfg = &phys_enc->cdm_cfg;
+	int ret;
+
+	if (!SDE_FORMAT_IS_YUV(format)) {
+		SDE_DEBUG("[cdm_disable fmt:%x]\n",
+				format->base.pixel_format);
+
+		if (hw_cdm && hw_cdm->ops.disable)
+			hw_cdm->ops.disable(hw_cdm);
+
+		return;
+	}
+
+	memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
+
+	cdm_cfg->output_width = wb_roi->w;
+	cdm_cfg->output_height = wb_roi->h;
+	cdm_cfg->output_fmt = format;
+	cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
+	cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
+		CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
+
+	/* enable 10 bit logic */
+	switch (cdm_cfg->output_fmt->chroma_sample) {
+	case SDE_CHROMA_RGB:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	case SDE_CHROMA_H2V1:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	case SDE_CHROMA_420:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
+		break;
+	case SDE_CHROMA_H1V2:
+	default:
+		SDE_ERROR("unsupported chroma sampling type\n");
+		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	}
+
+	SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
+			cdm_cfg->output_width,
+			cdm_cfg->output_height,
+			cdm_cfg->output_fmt->base.pixel_format,
+			cdm_cfg->output_type,
+			cdm_cfg->output_bit_depth,
+			cdm_cfg->h_cdwn_type,
+			cdm_cfg->v_cdwn_type);
+
+	if (hw_cdm && hw_cdm->ops.setup_cdwn) {
+		ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
+		if (ret < 0) {
+			SDE_ERROR("failed to setup CDM %d\n", ret);
+			return;
+		}
+	}
+
+	if (hw_cdm && hw_cdm->ops.enable) {
+		ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
+		if (ret < 0) {
+			SDE_ERROR("failed to enable CDM %d\n", ret);
+			return;
+		}
+	}
+}
+
+/**
+ * sde_encoder_phys_wb_setup_fb - setup output framebuffer
+ * @phys_enc:	Pointer to physical encoder
+ * @fb:		Pointer to output framebuffer
+ * @wb_roi:	Pointer to output region of interest
+ */
+static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, struct sde_rect *wb_roi)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb;
+	struct sde_hw_wb_cfg *wb_cfg;
+	const struct msm_format *format;
+	int ret, mmu_id;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	hw_wb = wb_enc->hw_wb;
+	wb_cfg = &wb_enc->wb_cfg;
+	memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
+
+	wb_cfg->intf_mode = phys_enc->intf_mode;
+	wb_cfg->is_secure = (fb->flags & DRM_MODE_FB_SECURE) ? true : false;
+	mmu_id = (wb_cfg->is_secure) ?
+			wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] :
+			wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE];
+
+	SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
+
+	format = msm_framebuffer_format(fb);
+	if (!format) {
+		SDE_DEBUG("invalid format for fb\n");
+		return;
+	}
+
+	wb_cfg->dest.format = sde_get_sde_format_ext(
+			format->pixel_format,
+			fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!wb_cfg->dest.format) {
+		/* this error should be detected during atomic_check */
+		SDE_ERROR("failed to get format %x\n", format->pixel_format);
+		return;
+	}
+	wb_cfg->roi = *wb_roi;
+
+	if (hw_wb->caps->features & BIT(SDE_WB_XY_ROI_OFFSET)) {
+		ret = sde_format_populate_layout(mmu_id, fb, &wb_cfg->dest);
+		if (ret) {
+			SDE_DEBUG("failed to populate layout %d\n", ret);
+			return;
+		}
+		wb_cfg->dest.width = fb->width;
+		wb_cfg->dest.height = fb->height;
+		wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
+	} else {
+		ret = sde_format_populate_layout_with_roi(mmu_id, fb, wb_roi,
+			&wb_cfg->dest);
+		if (ret) {
+			/* this error should be detected during atomic_check */
+			SDE_DEBUG("failed to populate layout %d\n", ret);
+			return;
+		}
+	}
+
+	if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
+			(wb_cfg->dest.format->element[0] == C1_B_Cb))
+		swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
+
+	SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
+			wb_cfg->dest.plane_addr[0],
+			wb_cfg->dest.plane_addr[1],
+			wb_cfg->dest.plane_addr[2],
+			wb_cfg->dest.plane_addr[3]);
+	SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
+			wb_cfg->dest.plane_pitch[0],
+			wb_cfg->dest.plane_pitch[1],
+			wb_cfg->dest.plane_pitch[2],
+			wb_cfg->dest.plane_pitch[3]);
+
+	if (hw_wb->ops.setup_roi)
+		hw_wb->ops.setup_roi(hw_wb, wb_cfg);
+
+	if (hw_wb->ops.setup_outformat)
+		hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
+
+	if (hw_wb->ops.setup_outaddress)
+		hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
+}
+
+/**
+ * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_hw_intf_cfg *intf_cfg = &wb_enc->intf_cfg;
+
+	memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
+
+	intf_cfg->intf = SDE_NONE;
+	intf_cfg->wb = hw_wb->idx;
+	intf_cfg->mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
+
+	if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg)
+		phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
+				intf_cfg);
+}
+
+/**
+ * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
+ * @phys_enc:	Pointer to physical encoder
+ * @crtc_state:	Pointer to CRTC atomic state
+ * @conn_state:	Pointer to connector atomic state
+ */
+static int sde_encoder_phys_wb_atomic_check(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
+	struct drm_framebuffer *fb;
+	const struct sde_format *fmt;
+	struct sde_rect wb_roi;
+	const struct drm_display_mode *mode = &crtc_state->mode;
+	int rc;
+
+	SDE_DEBUG("[atomic_check:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode->base.id, mode->name,
+			mode->hdisplay, mode->vdisplay);
+
+	if (!conn_state || !conn_state->connector) {
+		SDE_ERROR("invalid connector state\n");
+		return -EINVAL;
+	} else if (conn_state->connector->status !=
+			connector_status_connected) {
+		SDE_ERROR("connector not connected %d\n",
+				conn_state->connector->status);
+		return -EINVAL;
+	}
+
+	memset(&wb_roi, 0, sizeof(struct sde_rect));
+
+	rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
+	if (rc) {
+		SDE_ERROR("failed to get roi %d\n", rc);
+		return rc;
+	}
+
+	SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
+			wb_roi.w, wb_roi.h);
+
+	fb = sde_wb_connector_state_get_output_fb(conn_state);
+	if (!fb) {
+		SDE_ERROR("no output framebuffer\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
+			fb->width, fb->height);
+
+	fmt = sde_get_sde_format_ext(fb->pixel_format, fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!fmt) {
+		SDE_ERROR("unsupported output pixel format:%x\n",
+				fb->pixel_format);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->pixel_format,
+			fb->modifier[0]);
+
+	if (SDE_FORMAT_IS_YUV(fmt) &&
+			!(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
+		SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
+		return -EINVAL;
+	}
+
+	if (SDE_FORMAT_IS_UBWC(fmt) &&
+			!(wb_cfg->features & BIT(SDE_WB_UBWC_1_0))) {
+		SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
+		return -EINVAL;
+	}
+
+	if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
+		crtc_state->mode_changed = true;
+
+	if (wb_roi.w && wb_roi.h) {
+		if (wb_roi.w != mode->hdisplay) {
+			SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
+					mode->hdisplay);
+			return -EINVAL;
+		} else if (wb_roi.h != mode->vdisplay) {
+			SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
+					mode->vdisplay);
+			return -EINVAL;
+		} else if (wb_roi.x + wb_roi.w > fb->width) {
+			SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
+					wb_roi.x, wb_roi.w, fb->width);
+			return -EINVAL;
+		} else if (wb_roi.y + wb_roi.h > fb->height) {
+			SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
+					wb_roi.y, wb_roi.h, fb->height);
+			return -EINVAL;
+		} else if (wb_roi.w > wb_cfg->sblk->maxlinewidth) {
+			SDE_ERROR("invalid roi w=%d, maxlinewidth=%u\n",
+					wb_roi.w, wb_cfg->sblk->maxlinewidth);
+			return -EINVAL;
+		}
+	} else {
+		if (wb_roi.x || wb_roi.y) {
+			SDE_ERROR("invalid roi x=%d, y=%d\n",
+					wb_roi.x, wb_roi.y);
+			return -EINVAL;
+		} else if (fb->width != mode->hdisplay) {
+			SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
+					mode->hdisplay);
+			return -EINVAL;
+		} else if (fb->height != mode->vdisplay) {
+			SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
+					mode->vdisplay);
+			return -EINVAL;
+		} else if (fb->width > wb_cfg->sblk->maxlinewidth) {
+			SDE_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
+					fb->width, wb_cfg->sblk->maxlinewidth);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_flush - flush hardware update
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_flush(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
+	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;
+	u32 flush_mask = 0;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (!hw_ctl) {
+		SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
+		return;
+	}
+
+	if (hw_ctl->ops.get_bitmask_wb)
+		hw_ctl->ops.get_bitmask_wb(hw_ctl, &flush_mask, hw_wb->idx);
+
+	if (hw_ctl->ops.get_bitmask_cdm && hw_cdm)
+		hw_ctl->ops.get_bitmask_cdm(hw_ctl, &flush_mask, hw_cdm->idx);
+
+	if (hw_ctl->ops.update_pending_flush)
+		hw_ctl->ops.update_pending_flush(hw_ctl, flush_mask);
+
+	SDE_DEBUG("Flushing CTL_ID %d, flush_mask %x, WB %d\n",
+			hw_ctl->idx - CTL_0, flush_mask, hw_wb->idx - WB_0);
+}
+
+/**
+ * sde_encoder_phys_wb_setup - setup writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_setup(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct drm_display_mode mode = phys_enc->cached_mode;
+	struct drm_framebuffer *fb;
+	struct sde_rect *wb_roi = &wb_enc->wb_roi;
+
+	SDE_DEBUG("[mode_set:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode.base.id, mode.name,
+			mode.hdisplay, mode.vdisplay);
+
+	memset(wb_roi, 0, sizeof(struct sde_rect));
+
+	fb = sde_wb_get_output_fb(wb_enc->wb_dev);
+	if (!fb) {
+		SDE_DEBUG("no output framebuffer\n");
+		return;
+	}
+
+	SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
+			fb->width, fb->height);
+
+	sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
+	if (wb_roi->w == 0 || wb_roi->h == 0) {
+		wb_roi->x = 0;
+		wb_roi->y = 0;
+		wb_roi->w = fb->width;
+		wb_roi->h = fb->height;
+	}
+
+	SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
+			wb_roi->w, wb_roi->h);
+
+	wb_enc->wb_fmt = sde_get_sde_format_ext(fb->pixel_format, fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!wb_enc->wb_fmt) {
+		SDE_ERROR("unsupported output pixel format: %d\n",
+				fb->pixel_format);
+		return;
+	}
+
+	SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->pixel_format,
+			fb->modifier[0]);
+
+	sde_encoder_phys_wb_set_ot_limit(phys_enc);
+
+	sde_encoder_phys_wb_set_traffic_shaper(phys_enc);
+
+	sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
+
+	sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
+
+	sde_encoder_phys_wb_setup_cdp(phys_enc);
+}
+
+/**
+ * sde_encoder_phys_wb_unregister_irq - unregister writeback interrupt handler
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_unregister_irq(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	if (wb_enc->bypass_irqreg)
+		return 0;
+
+	sde_core_irq_disable(phys_enc->sde_kms, &wb_enc->irq_idx, 1);
+	sde_core_irq_unregister_callback(phys_enc->sde_kms, wb_enc->irq_idx,
+			&wb_enc->irq_cb);
+
+	SDE_DEBUG("un-register IRQ for wb %d, irq_idx=%d\n",
+			hw_wb->idx - WB_0,
+			wb_enc->irq_idx);
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_done_irq - writeback interrupt handler
+ * @arg:	Pointer to writeback encoder
+ * @irq_idx:	interrupt index
+ */
+static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_wb *wb_enc = arg;
+	struct sde_encoder_phys *phys_enc = &wb_enc->base;
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0,
+			wb_enc->frame_count);
+
+	if (phys_enc->parent_ops.handle_frame_done)
+		phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
+				phys_enc, SDE_ENCODER_FRAME_EVENT_DONE);
+
+	phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
+			phys_enc);
+
+	complete_all(&wb_enc->wbdone_complete);
+}
+
+/**
+ * sde_encoder_phys_wb_register_irq - register writeback interrupt handler
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_register_irq(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_irq_callback *irq_cb = &wb_enc->irq_cb;
+	enum sde_intr_type intr_type;
+	int ret = 0;
+
+	if (wb_enc->bypass_irqreg)
+		return 0;
+
+	intr_type = sde_encoder_phys_wb_get_intr_type(hw_wb);
+	wb_enc->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
+			intr_type, hw_wb->idx);
+	if (wb_enc->irq_idx < 0) {
+		SDE_ERROR(
+			"failed to lookup IRQ index for WB_DONE with wb=%d\n",
+			hw_wb->idx - WB_0);
+		return -EINVAL;
+	}
+
+	irq_cb->func = sde_encoder_phys_wb_done_irq;
+	irq_cb->arg = wb_enc;
+	ret = sde_core_irq_register_callback(phys_enc->sde_kms,
+			wb_enc->irq_idx, irq_cb);
+	if (ret) {
+		SDE_ERROR("failed to register IRQ callback WB_DONE\n");
+		return ret;
+	}
+
+	ret = sde_core_irq_enable(phys_enc->sde_kms, &wb_enc->irq_idx, 1);
+	if (ret) {
+		SDE_ERROR(
+			"failed to enable IRQ for WB_DONE, wb %d, irq_idx=%d\n",
+				hw_wb->idx - WB_0,
+				wb_enc->irq_idx);
+		wb_enc->irq_idx = -EINVAL;
+
+		/* Unregister callback on IRQ enable failure */
+		sde_core_irq_unregister_callback(phys_enc->sde_kms,
+				wb_enc->irq_idx, irq_cb);
+		return ret;
+	}
+
+	SDE_DEBUG("registered IRQ for wb %d, irq_idx=%d\n",
+			hw_wb->idx - WB_0,
+			wb_enc->irq_idx);
+
+	return ret;
+}
+
+/**
+ * sde_encoder_phys_wb_mode_set - set display mode
+ * @phys_enc:	Pointer to physical encoder
+ * @mode:	Pointer to requested display mode
+ * @adj_mode:	Pointer to adjusted display mode
+ */
+static void sde_encoder_phys_wb_mode_set(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_rm *rm = &phys_enc->sde_kms->rm;
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_rm_hw_iter iter;
+	int i, instance;
+
+	phys_enc->cached_mode = *adj_mode;
+	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
+
+	SDE_DEBUG("[mode_set_cache:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode->base.id,
+			mode->name, mode->hdisplay, mode->vdisplay);
+
+	phys_enc->hw_ctl = NULL;
+	phys_enc->hw_cdm = NULL;
+
+	/* Retrieve previously allocated HW Resources. CTL shouldn't fail */
+	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
+	for (i = 0; i <= instance; i++) {
+		sde_rm_get_hw(rm, &iter);
+		if (i == instance)
+			phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
+	}
+
+	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
+		SDE_ERROR("failed init ctl: %ld\n", PTR_ERR(phys_enc->hw_ctl));
+		phys_enc->hw_ctl = NULL;
+		return;
+	}
+
+	/* CDM is optional */
+	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
+	for (i = 0; i <= instance; i++) {
+		sde_rm_get_hw(rm, &iter);
+		if (i == instance)
+			phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
+	}
+
+	if (IS_ERR(phys_enc->hw_cdm)) {
+		SDE_ERROR("CDM required but not allocated: %ld\n",
+				PTR_ERR(phys_enc->hw_cdm));
+		phys_enc->hw_ctl = NULL;
+	}
+}
+
+/**
+ * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_wait_for_commit_done(
+		struct sde_encoder_phys *phys_enc)
+{
+	unsigned long ret;
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	u32 irq_status;
+	u64 wb_time = 0;
+	int rc = 0;
+
+	/* Return EWOULDBLOCK since we know the wait isn't necessary */
+	if (WARN_ON(phys_enc->enable_state != SDE_ENC_ENABLED))
+		return -EWOULDBLOCK;
+
+	SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count);
+
+	ret = wait_for_completion_timeout(&wb_enc->wbdone_complete,
+			KICKOFF_TIMEOUT_JIFFIES);
+
+	if (!ret) {
+		SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
+				wb_enc->frame_count);
+
+		irq_status = sde_core_irq_read(phys_enc->sde_kms,
+				wb_enc->irq_idx, true);
+		if (irq_status) {
+			SDE_DEBUG("wb:%d done but irq not triggered\n",
+					wb_enc->wb_dev->wb_idx - WB_0);
+			sde_encoder_phys_wb_done_irq(wb_enc, wb_enc->irq_idx);
+		} else {
+			SDE_ERROR("wb:%d kickoff timed out\n",
+					wb_enc->wb_dev->wb_idx - WB_0);
+			if (phys_enc->parent_ops.handle_frame_done)
+				phys_enc->parent_ops.handle_frame_done(
+						phys_enc->parent, phys_enc,
+						SDE_ENCODER_FRAME_EVENT_ERROR);
+			rc = -ETIMEDOUT;
+		}
+	}
+
+	sde_encoder_phys_wb_unregister_irq(phys_enc);
+
+	if (!rc)
+		wb_enc->end_time = ktime_get();
+
+	/* once operation is done, disable traffic shaper */
+	if (wb_enc->wb_cfg.ts_cfg.en && wb_enc->hw_wb &&
+			wb_enc->hw_wb->ops.setup_trafficshaper) {
+		wb_enc->wb_cfg.ts_cfg.en = false;
+		wb_enc->hw_wb->ops.setup_trafficshaper(
+				wb_enc->hw_wb, &wb_enc->wb_cfg);
+	}
+
+	/* remove vote for iommu/clk/bus */
+	wb_enc->frame_count++;
+
+	if (!rc) {
+		wb_time = (u64)ktime_to_us(wb_enc->end_time) -
+				(u64)ktime_to_us(wb_enc->start_time);
+		SDE_DEBUG("wb:%d took %llu us\n",
+			wb_enc->wb_dev->wb_idx - WB_0, wb_time);
+	}
+
+	SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
+			wb_time);
+
+	return rc;
+}
+
+/**
+ * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_prepare_for_kickoff(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	int ret;
+
+	SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
+			wb_enc->kickoff_count);
+
+	reinit_completion(&wb_enc->wbdone_complete);
+
+	ret = sde_encoder_phys_wb_register_irq(phys_enc);
+	if (ret) {
+		SDE_ERROR("failed to register irq %d\n", ret);
+		return;
+	}
+
+	wb_enc->kickoff_count++;
+
+	/* set OT limit & enable traffic shaper */
+	sde_encoder_phys_wb_setup(phys_enc);
+
+	sde_encoder_phys_wb_flush(phys_enc);
+
+	/* vote for iommu/clk/bus */
+	wb_enc->start_time = ktime_get();
+
+	SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->kickoff_count);
+}
+
+/**
+ * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_handle_post_kickoff(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
+
+	SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
+}
+
+/**
+ * sde_encoder_phys_wb_enable - enable writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct drm_device *dev;
+	struct drm_connector *connector;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
+		SDE_ERROR("invalid drm device\n");
+		return;
+	}
+	dev = wb_enc->base.parent->dev;
+
+	/* find associated writeback connector */
+	mutex_lock(&dev->mode_config.mutex);
+	drm_for_each_connector(connector, phys_enc->parent->dev) {
+		if (connector->encoder == phys_enc->parent)
+			break;
+	}
+	mutex_unlock(&dev->mode_config.mutex);
+
+	if (!connector || connector->encoder != phys_enc->parent) {
+		SDE_ERROR("failed to find writeback connector\n");
+		return;
+	}
+	wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
+
+	phys_enc->enable_state = SDE_ENC_ENABLED;
+}
+
+/**
+ * sde_encoder_phys_wb_disable - disable writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR("encoder is already disabled\n");
+		return;
+	}
+
+	if (wb_enc->frame_count != wb_enc->kickoff_count) {
+		SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
+				hw_wb->idx - WB_0, wb_enc->frame_count,
+				wb_enc->kickoff_count);
+		sde_encoder_phys_wb_wait_for_commit_done(phys_enc);
+	}
+
+	if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.disable) {
+		SDE_DEBUG_DRIVER("[cdm_disable]\n");
+		phys_enc->hw_cdm->ops.disable(phys_enc->hw_cdm);
+	}
+
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+}
+
+/**
+ * sde_encoder_phys_wb_get_hw_resources - get hardware resources
+ * @phys_enc:	Pointer to physical encoder
+ * @hw_res:	Pointer to encoder resources
+ */
+static void sde_encoder_phys_wb_get_hw_resources(
+		struct sde_encoder_phys *phys_enc,
+		struct sde_encoder_hw_resources *hw_res,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb;
+	struct drm_framebuffer *fb;
+	const struct sde_format *fmt;
+
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return;
+	}
+
+	fb = sde_wb_connector_state_get_output_fb(conn_state);
+	if (!fb) {
+		SDE_ERROR("no output framebuffer\n");
+		return;
+	}
+
+	fmt = sde_get_sde_format_ext(fb->pixel_format, fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!fmt) {
+		SDE_ERROR("unsupported output pixel format:%d\n",
+				fb->pixel_format);
+		return;
+	}
+
+	hw_wb = wb_enc->hw_wb;
+	hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
+	hw_res->needs_cdm = SDE_FORMAT_IS_YUV(fmt);
+	SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
+			hw_res->wbs[hw_wb->idx - WB_0],
+			hw_res->needs_cdm);
+}
+
+#ifdef CONFIG_DEBUG_FS
+/**
+ * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
+ * @phys_enc:	Pointer to physical encoder
+ * @sde_kms:	Pointer to SDE KMS object
+ */
+static int sde_encoder_phys_wb_init_debugfs(
+		struct sde_encoder_phys *phys_enc, struct sde_kms *kms)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	if (!phys_enc || !kms || !wb_enc->hw_wb)
+		return -EINVAL;
+
+	snprintf(wb_enc->wb_name, ARRAY_SIZE(wb_enc->wb_name), "encoder_wb%d",
+			wb_enc->hw_wb->idx - WB_0);
+
+	wb_enc->debugfs_root =
+		debugfs_create_dir(wb_enc->wb_name,
+				sde_debugfs_get_root(kms));
+	if (!wb_enc->debugfs_root) {
+		SDE_ERROR("failed to create debugfs\n");
+		return -ENOMEM;
+	}
+
+	if (!debugfs_create_u32("wbdone_timeout", S_IRUGO | S_IWUSR,
+			wb_enc->debugfs_root, &wb_enc->wbdone_timeout)) {
+		SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
+		return -ENOMEM;
+	}
+
+	if (!debugfs_create_u32("bypass_irqreg", S_IRUGO | S_IWUSR,
+			wb_enc->debugfs_root, &wb_enc->bypass_irqreg)) {
+		SDE_ERROR("failed to create debugfs/bypass_irqreg\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_destroy_debugfs - destroy writeback encoder debugfs
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_destroy_debugfs(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	if (!phys_enc)
+		return;
+
+	debugfs_remove_recursive(wb_enc->debugfs_root);
+}
+#else
+static int sde_encoder_phys_wb_init_debugfs(
+		struct sde_encoder_phys *phys_enc, struct sde_kms *kms)
+{
+	return 0;
+}
+static void sde_encoder_phys_wb_destroy_debugfs(
+		struct sde_encoder_phys *phys_enc)
+{
+}
+#endif
+
+/**
+ * sde_encoder_phys_wb_destroy - destroy writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (!phys_enc)
+		return;
+
+	sde_encoder_phys_wb_destroy_debugfs(phys_enc);
+
+	kfree(wb_enc);
+}
+
+/**
+ * sde_encoder_phys_wb_init_ops - initialize writeback operations
+ * @ops:	Pointer to encoder operation table
+ */
+static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
+{
+	ops->is_master = sde_encoder_phys_wb_is_master;
+	ops->mode_set = sde_encoder_phys_wb_mode_set;
+	ops->enable = sde_encoder_phys_wb_enable;
+	ops->disable = sde_encoder_phys_wb_disable;
+	ops->destroy = sde_encoder_phys_wb_destroy;
+	ops->atomic_check = sde_encoder_phys_wb_atomic_check;
+	ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
+	ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
+	ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
+	ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
+	ops->trigger_start = sde_encoder_helper_trigger_start;
+}
+
+/**
+ * sde_encoder_phys_wb_init - initialize writeback encoder
+ * @init:	Pointer to init info structure with initialization params
+ */
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_enc_phys_init_params *p)
+{
+	struct sde_encoder_phys *phys_enc;
+	struct sde_encoder_phys_wb *wb_enc;
+	struct sde_hw_mdp *hw_mdp;
+	int ret = 0;
+
+	SDE_DEBUG("\n");
+
+	wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
+	if (!wb_enc) {
+		ret = -ENOMEM;
+		goto fail_alloc;
+	}
+	wb_enc->irq_idx = -EINVAL;
+	wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
+	init_completion(&wb_enc->wbdone_complete);
+
+	phys_enc = &wb_enc->base;
+
+	if (p->sde_kms->vbif[VBIF_NRT]) {
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE];
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE];
+	} else {
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE];
+	}
+
+	hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
+	if (IS_ERR_OR_NULL(hw_mdp)) {
+		ret = PTR_ERR(hw_mdp);
+		SDE_ERROR("failed to init hw_top: %d\n", ret);
+		goto fail_mdp_init;
+	}
+	phys_enc->hw_mdptop = hw_mdp;
+
+	/**
+	 * hw_wb resource permanently assigned to this encoder
+	 * Other resources allocated at atomic commit time by use case
+	 */
+	if (p->wb_idx != SDE_NONE) {
+		struct sde_rm_hw_iter iter;
+
+		sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
+		while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
+			struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
+
+			if (hw_wb->idx == p->wb_idx) {
+				wb_enc->hw_wb = hw_wb;
+				break;
+			}
+		}
+
+		if (!wb_enc->hw_wb) {
+			ret = -EINVAL;
+			SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
+			goto fail_wb_init;
+		}
+	} else {
+		ret = -EINVAL;
+		SDE_ERROR("invalid wb_idx\n");
+		goto fail_wb_check;
+	}
+
+	sde_encoder_phys_wb_init_ops(&phys_enc->ops);
+	phys_enc->parent = p->parent;
+	phys_enc->parent_ops = p->parent_ops;
+	phys_enc->sde_kms = p->sde_kms;
+	phys_enc->split_role = p->split_role;
+	phys_enc->intf_mode = INTF_MODE_WB_LINE;
+	phys_enc->intf_idx = p->intf_idx;
+	phys_enc->enc_spinlock = p->enc_spinlock;
+	INIT_LIST_HEAD(&wb_enc->irq_cb.list);
+
+	ret = sde_encoder_phys_wb_init_debugfs(phys_enc, p->sde_kms);
+	if (ret) {
+		SDE_ERROR("failed to init debugfs %d\n", ret);
+		goto fail_debugfs_init;
+	}
+
+	SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
+			wb_enc->hw_wb->idx - WB_0);
+
+	return phys_enc;
+
+fail_debugfs_init:
+fail_wb_init:
+fail_wb_check:
+fail_mdp_init:
+	kfree(wb_enc);
+fail_alloc:
+	return ERR_PTR(ret);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.c b/drivers/gpu/drm/msm/sde/sde_fence.c
new file mode 100644
index 0000000000000000000000000000000000000000..6db6f989006fba243c5294e45290e5f0265d0963
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_fence.c
@@ -0,0 +1,232 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <sync.h>
+#include <sw_sync.h>
+#include "msm_drv.h"
+#include "sde_kms.h"
+#include "sde_fence.h"
+
+void *sde_sync_get(uint64_t fd)
+{
+	/* force signed compare, fdget accepts an int argument */
+	return (signed int)fd >= 0 ? sync_fence_fdget(fd) : NULL;
+}
+
+void sde_sync_put(void *fence)
+{
+	if (fence)
+		sync_fence_put(fence);
+}
+
+int sde_sync_wait(void *fence, long timeout_ms)
+{
+	if (!fence)
+		return -EINVAL;
+	return sync_fence_wait(fence, timeout_ms);
+}
+
+uint32_t sde_sync_get_name_prefix(void *fence)
+{
+	char *name;
+	uint32_t i, prefix;
+
+	if (!fence)
+		return 0x0;
+
+	name = ((struct sync_fence *)fence)->name;
+	prefix = 0x0;
+	for (i = 0; i < sizeof(uint32_t) && name[i]; ++i)
+		prefix = (prefix << CHAR_BIT) | name[i];
+
+	return prefix;
+}
+
+#if IS_ENABLED(CONFIG_SW_SYNC)
+/**
+ * _sde_fence_create_fd - create fence object and return an fd for it
+ * This function is NOT thread-safe.
+ * @timeline: Timeline to associate with fence
+ * @name: Name for fence
+ * @val: Timeline value at which to signal the fence
+ * Return: File descriptor on success, or error code on error
+ */
+static int _sde_fence_create_fd(void *timeline, const char *name, uint32_t val)
+{
+	struct sync_pt *sync_pt;
+	struct sync_fence *fence;
+	signed int fd = -EINVAL;
+
+	if (!timeline) {
+		SDE_ERROR("invalid timeline\n");
+		goto exit;
+	}
+
+	if (!name)
+		name = "sde_fence";
+
+	/* create sync point */
+	sync_pt = sw_sync_pt_create(timeline, val);
+	if (sync_pt == NULL) {
+		SDE_ERROR("failed to create sync point, %s\n", name);
+		goto exit;
+	}
+
+	/* create fence */
+	fence = sync_fence_create(name, sync_pt);
+	if (fence == NULL) {
+		sync_pt_free(sync_pt);
+		SDE_ERROR("couldn't create fence, %s\n", name);
+		goto exit;
+	}
+
+	/* create fd */
+	fd = get_unused_fd_flags(0);
+	if (fd < 0) {
+		SDE_ERROR("failed to get_unused_fd_flags(), %s\n", name);
+		sync_fence_put(fence);
+		goto exit;
+	}
+
+	sync_fence_install(fence, fd);
+exit:
+	return fd;
+}
+
+/**
+ * SDE_FENCE_TIMELINE_NAME - macro for accessing s/w timeline's name
+ * @fence: Pointer to sde fence structure
+ * @drm_id: ID number of owning DRM Object
+ * Returns: Pointer to timeline name string
+ */
+#define SDE_FENCE_TIMELINE_NAME(fence) \
+	(((struct sw_sync_timeline *)fence->timeline)->obj.name)
+
+int sde_fence_init(struct sde_fence *fence,
+		const char *name,
+		uint32_t drm_id)
+{
+	if (!fence) {
+		SDE_ERROR("invalid argument(s)\n");
+		return -EINVAL;
+	}
+
+	fence->timeline = sw_sync_timeline_create(name ? name : "sde");
+	if (!fence->timeline) {
+		SDE_ERROR("failed to create timeline\n");
+		return -ENOMEM;
+	}
+
+	fence->commit_count = 0;
+	fence->done_count = 0;
+	fence->drm_id = drm_id;
+
+	mutex_init(&fence->fence_lock);
+	return 0;
+
+}
+
+void sde_fence_deinit(struct sde_fence *fence)
+{
+	if (!fence) {
+		SDE_ERROR("invalid fence\n");
+		return;
+	}
+
+	mutex_destroy(&fence->fence_lock);
+	if (fence->timeline)
+		sync_timeline_destroy(fence->timeline);
+}
+
+int sde_fence_prepare(struct sde_fence *fence)
+{
+	if (!fence) {
+		SDE_ERROR("invalid fence\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&fence->fence_lock);
+	++fence->commit_count;
+	SDE_EVT32(fence->drm_id, fence->commit_count, fence->done_count);
+	mutex_unlock(&fence->fence_lock);
+	return 0;
+}
+
+int sde_fence_create(struct sde_fence *fence, uint64_t *val, int offset)
+{
+	uint32_t trigger_value;
+	int fd, rc = -EINVAL;
+
+	if (!fence || !fence->timeline || !val) {
+		SDE_ERROR("invalid argument(s), fence %pK, pval %pK\n",
+				fence, val);
+	} else  {
+		/*
+		 * Allow created fences to have a constant offset with respect
+		 * to the timeline. This allows us to delay the fence signalling
+		 * w.r.t. the commit completion (e.g., an offset of +1 would
+		 * cause fences returned during a particular commit to signal
+		 * after an additional delay of one commit, rather than at the
+		 * end of the current one.
+		 */
+		mutex_lock(&fence->fence_lock);
+		trigger_value = fence->commit_count + (int32_t)offset;
+		fd = _sde_fence_create_fd(fence->timeline,
+				SDE_FENCE_TIMELINE_NAME(fence),
+				trigger_value);
+		*val = fd;
+
+		SDE_EVT32(fence->drm_id, trigger_value, fd);
+		mutex_unlock(&fence->fence_lock);
+
+		if (fd >= 0)
+			rc = 0;
+	}
+
+	return rc;
+}
+
+void sde_fence_signal(struct sde_fence *fence, bool is_error)
+{
+	if (!fence || !fence->timeline) {
+		SDE_ERROR("invalid fence, %pK\n", fence);
+		return;
+	}
+
+	mutex_lock(&fence->fence_lock);
+	if ((fence->done_count - fence->commit_count) < 0)
+		++fence->done_count;
+	else
+		SDE_ERROR("detected extra signal attempt!\n");
+
+	/*
+	 * Always advance 'done' counter,
+	 * but only advance timeline if !error
+	 */
+	if (!is_error) {
+		int32_t val;
+
+		val = fence->done_count;
+		val -= ((struct sw_sync_timeline *)
+				fence->timeline)->value;
+		if (val < 0)
+			SDE_ERROR("invalid value\n");
+		else
+			sw_sync_timeline_inc(fence->timeline, (int)val);
+	}
+
+	SDE_EVT32(fence->drm_id, fence->done_count,
+			((struct sw_sync_timeline *) fence->timeline)->value);
+
+	mutex_unlock(&fence->fence_lock);
+}
+#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.h b/drivers/gpu/drm/msm/sde/sde_fence.h
new file mode 100644
index 0000000000000000000000000000000000000000..113d16b916f7745376b37af92df78d91d4ba5c75
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_fence.h
@@ -0,0 +1,177 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_FENCE_H_
+#define _SDE_FENCE_H_
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+
+#ifndef CHAR_BIT
+#define CHAR_BIT 8 /* define this if limits.h not available */
+#endif
+
+#ifdef CONFIG_SYNC
+/**
+ * sde_sync_get - Query sync fence object from a file handle
+ *
+ * On success, this function also increments the refcount of the sync fence
+ *
+ * @fd: Integer sync fence handle
+ *
+ * Return: Pointer to sync fence object, or NULL
+ */
+void *sde_sync_get(uint64_t fd);
+
+/**
+ * sde_sync_put - Releases a sync fence object acquired by @sde_sync_get
+ *
+ * This function decrements the sync fence's reference count; the object will
+ * be released if the reference count goes to zero.
+ *
+ * @fence: Pointer to sync fence
+ */
+void sde_sync_put(void *fence);
+
+/**
+ * sde_sync_wait - Query sync fence object from a file handle
+ *
+ * @fence: Pointer to sync fence
+ * @timeout_ms: Time to wait, in milliseconds. Waits forever if timeout_ms < 0
+ *
+ * Return: Zero on success, or -ETIME on timeout
+ */
+int sde_sync_wait(void *fence, long timeout_ms);
+
+/**
+ * sde_sync_get_name_prefix - get integer representation of fence name prefix
+ * @fence: Pointer to opaque fence structure
+ *
+ * Return: 32-bit integer containing first 4 characters of fence name,
+ *         big-endian notation
+ */
+uint32_t sde_sync_get_name_prefix(void *fence);
+#else
+static inline void *sde_sync_get(uint64_t fd)
+{
+	return NULL;
+}
+
+static inline void sde_sync_put(void *fence)
+{
+}
+
+static inline int sde_sync_wait(void *fence, long timeout_ms)
+{
+	return 0;
+}
+
+static inline uint32_t sde_sync_get_name_prefix(void *fence)
+{
+	return 0x0;
+}
+#endif
+
+/**
+ * struct sde_fence - output fence container structure
+ * @timeline: Pointer to fence timeline
+ * @commit_count: Number of detected commits since bootup
+ * @done_count: Number of completed commits since bootup
+ * @drm_id: ID number of owning DRM Object
+ * @fence_lock: Mutex object to protect local fence variables
+ */
+struct sde_fence {
+	void *timeline;
+	int32_t commit_count;
+	int32_t done_count;
+	uint32_t drm_id;
+	struct mutex fence_lock;
+};
+
+#if IS_ENABLED(CONFIG_SW_SYNC)
+/**
+ * sde_fence_init - initialize fence object
+ * @fence: Pointer to crtc fence object
+ * @drm_id: ID number of owning DRM Object
+ * @name: Timeline name
+ * Returns: Zero on success
+ */
+int sde_fence_init(struct sde_fence *fence,
+		const char *name,
+		uint32_t drm_id);
+
+/**
+ * sde_fence_deinit - deinit fence container
+ * @fence: Pointer fence container
+ */
+void sde_fence_deinit(struct sde_fence *fence);
+
+/**
+ * sde_fence_prepare - prepare to return fences for current commit
+ * @fence: Pointer fence container
+ * Returns: Zero on success
+ */
+int sde_fence_prepare(struct sde_fence *fence);
+
+/**
+ * sde_fence_create - create output fence object
+ * @fence: Pointer fence container
+ * @val: Pointer to output value variable, fence fd will be placed here
+ * @offset: Fence signal commit offset, e.g., +1 to signal on next commit
+ * Returns: Zero on success
+ */
+int sde_fence_create(struct sde_fence *fence, uint64_t *val, int offset);
+
+/**
+ * sde_fence_signal - advance fence timeline to signal outstanding fences
+ * @fence: Pointer fence container
+ * @is_error: Set to non-zero if the commit didn't complete successfully
+ */
+void sde_fence_signal(struct sde_fence *fence, bool is_error);
+#else
+static inline int sde_fence_init(struct sde_fence *fence,
+		const char *name,
+		uint32_t drm_id)
+{
+	/* do nothing */
+	return 0;
+}
+
+static inline void sde_fence_deinit(struct sde_fence *fence)
+{
+	/* do nothing */
+}
+
+static inline void sde_fence_prepare(struct sde_fence *fence)
+{
+	/* do nothing */
+}
+
+static inline int sde_fence_get(struct sde_fence *fence, uint64_t *val)
+{
+	return -EINVAL;
+}
+
+static inline void sde_fence_signal(struct sde_fence *fence, bool is_error)
+{
+	/* do nothing */
+}
+
+static inline int sde_fence_create(struct sde_fence *fence, uint64_t *val,
+								int offset)
+{
+	return 0;
+}
+#endif /* IS_ENABLED(CONFIG_SW_SYNC) */
+
+#endif /* _SDE_FENCE_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_formats.c b/drivers/gpu/drm/msm/sde/sde_formats.c
new file mode 100644
index 0000000000000000000000000000000000000000..41180f5dec122a6a4bbbcdff8143781305d3e4c2
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_formats.c
@@ -0,0 +1,996 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <uapi/drm/drm_fourcc.h>
+
+#include "sde_kms.h"
+#include "sde_formats.h"
+
+#define SDE_UBWC_META_MACRO_W_H		16
+#define SDE_UBWC_META_BLOCK_SIZE	256
+#define SDE_MAX_IMG_WIDTH		0x3FFF
+#define SDE_MAX_IMG_HEIGHT		0x3FFF
+
+/**
+ * SDE supported format packing, bpp, and other format
+ * information.
+ * SDE currently only supports interleaved RGB formats
+ * UBWC support for a pixel format is indicated by the flag,
+ * there is additional meta data plane for such formats
+ */
+
+#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha,   \
+bp, flg, fm, np)                                                          \
+{                                                                         \
+	.base.pixel_format = DRM_FORMAT_ ## fmt,                          \
+	.fetch_planes = SDE_PLANE_INTERLEAVED,                            \
+	.alpha_enable = alpha,                                            \
+	.element = { (e0), (e1), (e2), (e3) },                            \
+	.bits = { g, b, r, a },                                           \
+	.chroma_sample = SDE_CHROMA_RGB,                                  \
+	.unpack_align_msb = 0,                                            \
+	.unpack_tight = 1,                                                \
+	.unpack_count = uc,                                               \
+	.bpp = bp,                                                        \
+	.fetch_mode = fm,                                                 \
+	.flag = flg,                                                      \
+	.num_planes = np                                                  \
+}
+
+#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3,              \
+alpha, chroma, count, bp, flg, fm, np)                                    \
+{                                                                         \
+	.base.pixel_format = DRM_FORMAT_ ## fmt,                          \
+	.fetch_planes = SDE_PLANE_INTERLEAVED,                            \
+	.alpha_enable = alpha,                                            \
+	.element = { (e0), (e1), (e2), (e3)},                             \
+	.bits = { g, b, r, a },                                           \
+	.chroma_sample = chroma,                                          \
+	.unpack_align_msb = 0,                                            \
+	.unpack_tight = 1,                                                \
+	.unpack_count = count,                                            \
+	.bpp = bp,                                                        \
+	.fetch_mode = fm,                                                 \
+	.flag = flg,                                                      \
+	.num_planes = np                                                  \
+}
+
+#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)      \
+{                                                                         \
+	.base.pixel_format = DRM_FORMAT_ ## fmt,                          \
+	.fetch_planes = SDE_PLANE_PSEUDO_PLANAR,                          \
+	.alpha_enable = false,                                            \
+	.element = { (e0), (e1), 0, 0 },                                  \
+	.bits = { g, b, r, a },                                           \
+	.chroma_sample = chroma,                                          \
+	.unpack_align_msb = 0,                                            \
+	.unpack_tight = 1,                                                \
+	.unpack_count = 2,                                                \
+	.bpp = 2,                                                         \
+	.fetch_mode = fm,                                                 \
+	.flag = flg,                                                      \
+	.num_planes = np                                                  \
+}
+
+#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp,    \
+flg, fm, np)                                                      \
+{                                                                         \
+	.base.pixel_format = DRM_FORMAT_ ## fmt,                          \
+	.fetch_planes = SDE_PLANE_PLANAR,                                 \
+	.alpha_enable = alpha,                                            \
+	.element = { (e0), (e1), (e2), 0 },                               \
+	.bits = { g, b, r, a },                                           \
+	.chroma_sample = chroma,                                          \
+	.unpack_align_msb = 0,                                            \
+	.unpack_tight = 1,                                                \
+	.unpack_count = 1,                                                \
+	.bpp = bp,                                                        \
+	.fetch_mode = fm,                                                 \
+	.flag = flg,                                                      \
+	.num_planes = np                                                  \
+}
+
+static const struct sde_format sde_format_map[] = {
+	INTERLEAVED_RGB_FMT(ARGB8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		true, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ABGR8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		true, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XBGR8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		true, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBA8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRA8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		true, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRX8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		false, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XRGB8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		false, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBX8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		false, 4, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGB888,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+		false, 3, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGR888,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+		false, 3, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGB565,
+		0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGR565,
+		0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ARGB1555,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ABGR1555,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBA5551,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRA5551,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XRGB1555,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XBGR1555,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBX5551,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRX5551,
+		COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ARGB4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ABGR4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBA4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRA4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		true, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XRGB4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XBGR4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBX4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRX4444,
+		COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		false, 2, 0,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRA1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBA1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ABGR2101010,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(ARGB2101010,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XRGB2101010,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+		false, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(BGRX1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+		false, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(XBGR2101010,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+		false, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	INTERLEAVED_RGB_FMT(RGBX1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		false, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_LINEAR, 1),
+
+	PSEUDO_YUV_FMT(NV12,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C2_R_Cr,
+		SDE_CHROMA_420, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	PSEUDO_YUV_FMT(NV21,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C1_B_Cb,
+		SDE_CHROMA_420, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	PSEUDO_YUV_FMT(NV16,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C2_R_Cr,
+		SDE_CHROMA_H2V1, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	PSEUDO_YUV_FMT(NV61,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C1_B_Cb,
+		SDE_CHROMA_H2V1, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	INTERLEAVED_YUV_FMT(VYUY,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
+		false, SDE_CHROMA_H2V1, 4, 2, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	INTERLEAVED_YUV_FMT(UYVY,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
+		false, SDE_CHROMA_H2V1, 4, 2, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	INTERLEAVED_YUV_FMT(YUYV,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
+		false, SDE_CHROMA_H2V1, 4, 2, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	INTERLEAVED_YUV_FMT(YVYU,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
+		false, SDE_CHROMA_H2V1, 4, 2, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 2),
+
+	PLANAR_YUV_FMT(YUV420,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C0_G_Y, C1_B_Cb, C2_R_Cr,
+		false, SDE_CHROMA_420, 1, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 3),
+
+	PLANAR_YUV_FMT(YVU420,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C0_G_Y, C2_R_Cr, C1_B_Cb,
+		false, SDE_CHROMA_420, 1, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_LINEAR, 3),
+};
+
+/*
+ * UBWC formats table:
+ * This table holds the UBWC formats supported.
+ * If a compression ratio needs to be used for this or any other format,
+ * the data will be passed by user-space.
+ */
+static const struct sde_format sde_format_map_ubwc[] = {
+	INTERLEAVED_RGB_FMT(RGB565,
+		0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+		false, 2, 0,
+		SDE_FETCH_UBWC, 2),
+
+	INTERLEAVED_RGB_FMT(RGBA8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 4, 0,
+		SDE_FETCH_UBWC, 2),
+
+	INTERLEAVED_RGB_FMT(RGBX8888,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		false, 4, 0,
+		SDE_FETCH_UBWC, 2),
+
+	INTERLEAVED_RGB_FMT(RGBA1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_UBWC, 2),
+
+	INTERLEAVED_RGB_FMT(RGBX1010102,
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+		true, 4, SDE_FORMAT_FLAG_DX,
+		SDE_FETCH_UBWC, 2),
+
+	PSEUDO_YUV_FMT(NV12,
+		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+		C1_B_Cb, C2_R_Cr,
+		SDE_CHROMA_420, SDE_FORMAT_FLAG_YUV,
+		SDE_FETCH_UBWC, 4),
+};
+
+/* _sde_get_v_h_subsample_rate - Get subsample rates for all formats we support
+ *   Note: Not using the drm_format_*_subsampling since we have formats
+ */
+static void _sde_get_v_h_subsample_rate(
+	enum sde_chroma_samp_type chroma_sample,
+	uint32_t *v_sample,
+	uint32_t *h_sample)
+{
+	if (!v_sample || !h_sample)
+		return;
+
+	switch (chroma_sample) {
+	case SDE_CHROMA_H2V1:
+		*v_sample = 1;
+		*h_sample = 2;
+		break;
+	case SDE_CHROMA_H1V2:
+		*v_sample = 2;
+		*h_sample = 1;
+		break;
+	case SDE_CHROMA_420:
+		*v_sample = 2;
+		*h_sample = 2;
+		break;
+	default:
+		*v_sample = 1;
+		*h_sample = 1;
+		break;
+	}
+}
+
+static int _sde_format_get_plane_sizes_ubwc(
+		const struct sde_format *fmt,
+		const uint32_t width,
+		const uint32_t height,
+		struct sde_hw_fmt_layout *layout)
+{
+	int i;
+
+	memset(layout, 0, sizeof(struct sde_hw_fmt_layout));
+	layout->format = fmt;
+	layout->width = width;
+	layout->height = height;
+	layout->num_planes = fmt->num_planes;
+
+	if (fmt->base.pixel_format == DRM_FORMAT_NV12) {
+		uint32_t y_stride_alignment, uv_stride_alignment;
+		uint32_t y_height_alignment, uv_height_alignment;
+		uint32_t y_tile_width = 32;
+		uint32_t y_tile_height = 8;
+		uint32_t uv_tile_width = y_tile_width / 2;
+		uint32_t uv_tile_height = y_tile_height;
+		uint32_t y_bpp_numer = 1, y_bpp_denom = 1;
+		uint32_t uv_bpp_numer = 1, uv_bpp_denom = 1;
+
+		y_stride_alignment = 128;
+		uv_stride_alignment = 64;
+		y_height_alignment = 32;
+		uv_height_alignment = 32;
+		y_bpp_numer = 1;
+		uv_bpp_numer = 2;
+		y_bpp_denom = 1;
+		uv_bpp_denom = 1;
+
+		layout->num_planes = 4;
+		/* Y bitstream stride and plane size */
+		layout->plane_pitch[0] = ALIGN(width, y_stride_alignment);
+		layout->plane_pitch[0] = (layout->plane_pitch[0] * y_bpp_numer)
+				/ y_bpp_denom;
+		layout->plane_size[0] = ALIGN(layout->plane_pitch[0] *
+				ALIGN(height, y_height_alignment), 4096);
+
+		/* CbCr bitstream stride and plane size */
+		layout->plane_pitch[1] = ALIGN(width / 2, uv_stride_alignment);
+		layout->plane_pitch[1] = (layout->plane_pitch[1] * uv_bpp_numer)
+				/ uv_bpp_denom;
+		layout->plane_size[1] = ALIGN(layout->plane_pitch[1] *
+			ALIGN(height / 2, uv_height_alignment), 4096);
+
+		/* Y meta data stride and plane size */
+		layout->plane_pitch[2] = ALIGN(
+				DIV_ROUND_UP(width, y_tile_width), 64);
+		layout->plane_size[2] = ALIGN(layout->plane_pitch[2] *
+			ALIGN(DIV_ROUND_UP(height, y_tile_height), 16), 4096);
+
+		/* CbCr meta data stride and plane size */
+		layout->plane_pitch[3] = ALIGN(
+				DIV_ROUND_UP(width / 2, uv_tile_width), 64);
+		layout->plane_size[3] = ALIGN(layout->plane_pitch[3] *
+			ALIGN(DIV_ROUND_UP(height / 2, uv_tile_height), 16),
+			4096);
+
+	} else if (fmt->base.pixel_format == DRM_FORMAT_RGBA8888 ||
+		fmt->base.pixel_format == DRM_FORMAT_RGBX8888    ||
+		fmt->base.pixel_format == DRM_FORMAT_RGBA1010102 ||
+		fmt->base.pixel_format == DRM_FORMAT_RGBX1010102 ||
+		fmt->base.pixel_format == DRM_FORMAT_RGB565) {
+		uint32_t stride_alignment, aligned_bitstream_width;
+
+		if (fmt->base.pixel_format == DRM_FORMAT_RGB565)
+			stride_alignment = 128;
+		else
+			stride_alignment = 64;
+		layout->num_planes = 3;
+
+		/* Nothing in plane[1] */
+
+		/* RGB bitstream stride and plane size */
+		aligned_bitstream_width = ALIGN(width, stride_alignment);
+		layout->plane_pitch[0] = aligned_bitstream_width * fmt->bpp;
+		layout->plane_size[0] = ALIGN(fmt->bpp * aligned_bitstream_width
+				* ALIGN(height, 16), 4096);
+
+		/* RGB meta data stride and plane size */
+		layout->plane_pitch[2] = ALIGN(DIV_ROUND_UP(
+				aligned_bitstream_width, 16), 64);
+		layout->plane_size[2] = ALIGN(layout->plane_pitch[2] *
+			ALIGN(DIV_ROUND_UP(height, 4), 16), 4096);
+	} else {
+		DRM_ERROR("UBWC format not supported for fmt:0x%X\n",
+			fmt->base.pixel_format);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < SDE_MAX_PLANES; i++)
+		layout->total_size += layout->plane_size[i];
+
+	return 0;
+}
+
+static int _sde_format_get_plane_sizes_linear(
+		const struct sde_format *fmt,
+		const uint32_t width,
+		const uint32_t height,
+		struct sde_hw_fmt_layout *layout)
+{
+	int i;
+
+	memset(layout, 0, sizeof(struct sde_hw_fmt_layout));
+	layout->format = fmt;
+	layout->width = width;
+	layout->height = height;
+	layout->num_planes = fmt->num_planes;
+
+	/* Due to memset above, only need to set planes of interest */
+	if (fmt->fetch_planes == SDE_PLANE_INTERLEAVED) {
+		layout->num_planes = 1;
+		layout->plane_size[0] = width * height * layout->format->bpp;
+		layout->plane_pitch[0] = width * layout->format->bpp;
+	} else {
+		uint32_t v_subsample, h_subsample;
+		uint32_t chroma_samp;
+
+		chroma_samp = fmt->chroma_sample;
+		_sde_get_v_h_subsample_rate(chroma_samp, &v_subsample,
+				&h_subsample);
+
+		if (width % h_subsample || height % v_subsample) {
+			DRM_ERROR("mismatch in subsample vs dimensions\n");
+			return -EINVAL;
+		}
+
+		layout->plane_pitch[0] = width;
+		layout->plane_pitch[1] = width / h_subsample;
+		layout->plane_size[0] = layout->plane_pitch[0] * height;
+		layout->plane_size[1] = layout->plane_pitch[1] *
+				(height / v_subsample);
+
+		if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
+			layout->num_planes = 2;
+			layout->plane_size[1] *= 2;
+			layout->plane_pitch[1] *= 2;
+		} else {
+			/* planar */
+			layout->num_planes = 3;
+			layout->plane_size[2] = layout->plane_size[1];
+			layout->plane_pitch[2] = layout->plane_pitch[1];
+		}
+	}
+
+	for (i = 0; i < SDE_MAX_PLANES; i++)
+		layout->total_size += layout->plane_size[i];
+
+	return 0;
+}
+
+static int _sde_format_get_plane_sizes(
+		const struct sde_format *fmt,
+		const uint32_t w,
+		const uint32_t h,
+		struct sde_hw_fmt_layout *layout)
+{
+	if (!layout || !fmt) {
+		DRM_ERROR("invalid pointer\n");
+		return -EINVAL;
+	}
+
+	if ((w > SDE_MAX_IMG_WIDTH) || (h > SDE_MAX_IMG_HEIGHT)) {
+		DRM_ERROR("image dimensions outside max range\n");
+		return -ERANGE;
+	}
+
+	if (SDE_FORMAT_IS_UBWC(fmt))
+		return _sde_format_get_plane_sizes_ubwc(fmt, w, h, layout);
+
+	return _sde_format_get_plane_sizes_linear(fmt, w, h, layout);
+}
+
+static int _sde_format_populate_addrs_ubwc(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_hw_fmt_layout *layout)
+{
+	uint32_t base_addr;
+
+	if (!fb || !layout) {
+		DRM_ERROR("invalid pointers\n");
+		return -EINVAL;
+	}
+
+	base_addr = msm_framebuffer_iova(fb, mmu_id, 0);
+	if (!base_addr) {
+		DRM_ERROR("failed to retrieve base addr\n");
+		return -EFAULT;
+	}
+
+	/* Per-format logic for verifying active planes */
+	if (SDE_FORMAT_IS_YUV(layout->format)) {
+		/************************************************/
+		/*      UBWC            **                      */
+		/*      buffer          **      SDE PLANE       */
+		/*      format          **                      */
+		/************************************************/
+		/* -------------------  ** -------------------- */
+		/* |      Y meta     |  ** |    Y bitstream   | */
+		/* |       data      |  ** |       plane      | */
+		/* -------------------  ** -------------------- */
+		/* |    Y bitstream  |  ** |  CbCr bitstream  | */
+		/* |       data      |  ** |       plane      | */
+		/* -------------------  ** -------------------- */
+		/* |   Cbcr metadata |  ** |       Y meta     | */
+		/* |       data      |  ** |       plane      | */
+		/* -------------------  ** -------------------- */
+		/* |  CbCr bitstream |  ** |     CbCr meta    | */
+		/* |       data      |  ** |       plane      | */
+		/* -------------------  ** -------------------- */
+		/************************************************/
+
+		/* configure Y bitstream plane */
+		layout->plane_addr[0] = base_addr + layout->plane_size[2];
+
+		/* configure CbCr bitstream plane */
+		layout->plane_addr[1] = base_addr + layout->plane_size[0]
+			+ layout->plane_size[2] + layout->plane_size[3];
+
+		/* configure Y metadata plane */
+		layout->plane_addr[2] = base_addr;
+
+		/* configure CbCr metadata plane */
+		layout->plane_addr[3] = base_addr + layout->plane_size[0]
+			+ layout->plane_size[2];
+
+	} else {
+		/************************************************/
+		/*      UBWC            **                      */
+		/*      buffer          **      SDE PLANE       */
+		/*      format          **                      */
+		/************************************************/
+		/* -------------------  ** -------------------- */
+		/* |      RGB meta   |  ** |   RGB bitstream  | */
+		/* |       data      |  ** |       plane      | */
+		/* -------------------  ** -------------------- */
+		/* |  RGB bitstream  |  ** |       NONE       | */
+		/* |       data      |  ** |                  | */
+		/* -------------------  ** -------------------- */
+		/*                      ** |     RGB meta     | */
+		/*                      ** |       plane      | */
+		/*                      ** -------------------- */
+		/************************************************/
+
+		layout->plane_addr[0] = base_addr + layout->plane_size[2];
+		layout->plane_addr[1] = 0;
+		layout->plane_addr[2] = base_addr;
+		layout->plane_addr[3] = 0;
+	}
+
+	return 0;
+}
+
+static int _sde_format_populate_addrs_linear(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_hw_fmt_layout *layout)
+{
+	unsigned int i;
+
+	/* Can now check the pitches given vs pitches expected */
+	for (i = 0; i < layout->num_planes; ++i) {
+		if (layout->plane_pitch[i] != fb->pitches[i]) {
+			DRM_ERROR("plane %u expected pitch %u, fb %u\n",
+				i, layout->plane_pitch[i], fb->pitches[i]);
+			return -EINVAL;
+		}
+	}
+
+	/* Populate addresses for simple formats here */
+	for (i = 0; i < layout->num_planes; ++i) {
+		layout->plane_addr[i] = msm_framebuffer_iova(fb, mmu_id, i);
+		if (!layout->plane_addr[i]) {
+			DRM_ERROR("failed to retrieve base addr\n");
+			return -EFAULT;
+		}
+	}
+
+	return 0;
+}
+
+int sde_format_populate_layout(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_hw_fmt_layout *layout)
+{
+	uint32_t plane_addr[SDE_MAX_PLANES];
+	int i, ret;
+
+	if (!fb || !layout) {
+		DRM_ERROR("invalid arguments\n");
+		return -EINVAL;
+	}
+
+	if ((fb->width > SDE_MAX_IMG_WIDTH) ||
+			(fb->height > SDE_MAX_IMG_HEIGHT)) {
+		DRM_ERROR("image dimensions outside max range\n");
+		return -ERANGE;
+	}
+
+	layout->format = to_sde_format(msm_framebuffer_format(fb));
+
+	/* Populate the plane sizes etc via get_format */
+	ret = _sde_format_get_plane_sizes(layout->format, fb->width, fb->height,
+			layout);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < SDE_MAX_PLANES; ++i)
+		plane_addr[i] = layout->plane_addr[i];
+
+	/* Populate the addresses given the fb */
+	if (SDE_FORMAT_IS_UBWC(layout->format))
+		ret = _sde_format_populate_addrs_ubwc(mmu_id, fb, layout);
+	else
+		ret = _sde_format_populate_addrs_linear(mmu_id, fb, layout);
+
+	/* check if anything changed */
+	if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
+		ret = -EAGAIN;
+
+	return ret;
+}
+
+static void _sde_format_calc_offset_linear(struct sde_hw_fmt_layout *source,
+		u32 x, u32 y)
+{
+	if ((x == 0) && (y == 0))
+		return;
+
+	source->plane_addr[0] += y * source->plane_pitch[0];
+
+	if (source->num_planes == 1) {
+		source->plane_addr[0] += x * source->format->bpp;
+	} else {
+		uint32_t xoff, yoff;
+		uint32_t v_subsample = 1;
+		uint32_t h_subsample = 1;
+
+		_sde_get_v_h_subsample_rate(source->format->chroma_sample,
+				&v_subsample, &h_subsample);
+
+		xoff = x / h_subsample;
+		yoff = y / v_subsample;
+
+		source->plane_addr[0] += x;
+		source->plane_addr[1] += xoff +
+				(yoff * source->plane_pitch[1]);
+		if (source->num_planes == 2) /* pseudo planar */
+			source->plane_addr[1] += xoff;
+		else /* planar */
+			source->plane_addr[2] += xoff +
+				(yoff * source->plane_pitch[2]);
+	}
+}
+
+int sde_format_populate_layout_with_roi(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_rect *roi,
+		struct sde_hw_fmt_layout *layout)
+{
+	int ret;
+
+	ret = sde_format_populate_layout(mmu_id, fb, layout);
+	if (ret || !roi)
+		return ret;
+
+	if (!roi->w || !roi->h || (roi->x + roi->w > fb->width) ||
+			(roi->y + roi->h > fb->height)) {
+		DRM_ERROR("invalid roi=[%d,%d,%d,%d], fb=[%u,%u]\n",
+				roi->x, roi->y, roi->w, roi->h,
+				fb->width, fb->height);
+		ret = -EINVAL;
+	} else if (SDE_FORMAT_IS_LINEAR(layout->format)) {
+		_sde_format_calc_offset_linear(layout, roi->x, roi->y);
+		layout->width = roi->w;
+		layout->height = roi->h;
+	} else if (roi->x || roi->y || (roi->w != fb->width) ||
+			(roi->h != fb->height)) {
+		DRM_ERROR("non-linear layout with roi not supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int sde_format_check_modified_format(
+		const struct msm_kms *kms,
+		const struct msm_format *msm_fmt,
+		const struct drm_mode_fb_cmd2 *cmd,
+		struct drm_gem_object **bos)
+{
+	int ret, i, num_base_fmt_planes;
+	const struct sde_format *fmt;
+	struct sde_hw_fmt_layout layout;
+	uint32_t bos_total_size = 0;
+
+	if (!msm_fmt || !cmd || !bos) {
+		DRM_ERROR("invalid arguments\n");
+		return -EINVAL;
+	}
+
+	fmt = to_sde_format(msm_fmt);
+	num_base_fmt_planes = drm_format_num_planes(fmt->base.pixel_format);
+
+	ret = _sde_format_get_plane_sizes(fmt, cmd->width, cmd->height,
+			&layout);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < num_base_fmt_planes; i++) {
+		if (!bos[i]) {
+			DRM_ERROR("invalid handle for plane %d\n", i);
+			return -EINVAL;
+		}
+		bos_total_size += bos[i]->size;
+	}
+
+	if (bos_total_size < layout.total_size) {
+		DRM_ERROR("buffers total size too small %u expected %u\n",
+				bos_total_size, layout.total_size);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+const struct sde_format *sde_get_sde_format_ext(
+		const uint32_t format,
+		const uint64_t *modifiers,
+		const uint32_t modifiers_len)
+{
+	uint32_t i = 0;
+	uint64_t mod0 = 0;
+	const struct sde_format *fmt = NULL;
+	const struct sde_format *map = NULL;
+	ssize_t map_size = 0;
+
+	/*
+	 * Currently only support exactly zero or one modifier.
+	 * All planes used must specify the same modifier.
+	 */
+	if (modifiers_len && !modifiers) {
+		DRM_ERROR("invalid modifiers array\n");
+		return NULL;
+	} else if (modifiers && modifiers_len && modifiers[0]) {
+		mod0 = modifiers[0];
+		DBG("plane format modifier 0x%llX", mod0);
+		for (i = 1; i < modifiers_len; i++) {
+			if (modifiers[i] != mod0) {
+				DRM_ERROR("bad fmt mod 0x%llX on plane %d\n",
+					modifiers[i], i);
+				return NULL;
+			}
+		}
+	}
+
+	switch (mod0) {
+	case 0:
+		map = sde_format_map;
+		map_size = ARRAY_SIZE(sde_format_map);
+		break;
+	case DRM_FORMAT_MOD_QCOM_COMPRESSED:
+		map = sde_format_map_ubwc;
+		map_size = ARRAY_SIZE(sde_format_map_ubwc);
+		DBG("found fmt 0x%X DRM_FORMAT_MOD_QCOM_COMPRESSED", format);
+		break;
+	default:
+		DRM_ERROR("unsupported format modifier %llX\n", mod0);
+		return NULL;
+	}
+
+	for (i = 0; i < map_size; i++) {
+		if (format == map[i].base.pixel_format) {
+			fmt = &map[i];
+			break;
+		}
+	}
+
+	if (fmt == NULL)
+		DRM_ERROR("unsupported fmt 0x%X modifier 0x%llX\n",
+				format, mod0);
+	else
+		DBG("fmt %s mod 0x%llX ubwc %d yuv %d",
+				drm_get_format_name(format), mod0,
+				SDE_FORMAT_IS_UBWC(fmt),
+				SDE_FORMAT_IS_YUV(fmt));
+
+	return fmt;
+}
+
+const struct msm_format *sde_get_msm_format(
+		struct msm_kms *kms,
+		const uint32_t format,
+		const uint64_t *modifiers,
+		const uint32_t modifiers_len)
+{
+	const struct sde_format *fmt = sde_get_sde_format_ext(format,
+			modifiers, modifiers_len);
+	if (fmt)
+		return &fmt->base;
+	return NULL;
+}
+
+uint32_t sde_populate_formats(
+		const struct sde_format_extended *format_list,
+		uint32_t *pixel_formats,
+		uint64_t *pixel_modifiers,
+		uint32_t pixel_formats_max)
+{
+	uint32_t i, fourcc_format;
+
+	if (!format_list || !pixel_formats)
+		return 0;
+
+	for (i = 0, fourcc_format = 0;
+			format_list->fourcc_format && i < pixel_formats_max;
+			++format_list) {
+		/* verify if listed format is in sde_format_map? */
+
+		/* optionally return modified formats */
+		if (pixel_modifiers) {
+			/* assume same modifier for all fb planes */
+			pixel_formats[i] = format_list->fourcc_format;
+			pixel_modifiers[i++] = format_list->modifier;
+		} else {
+			/* assume base formats grouped together */
+			if (fourcc_format != format_list->fourcc_format) {
+				fourcc_format = format_list->fourcc_format;
+				pixel_formats[i++] = fourcc_format;
+			}
+		}
+	}
+
+	return i;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_formats.h b/drivers/gpu/drm/msm/sde/sde_formats.h
new file mode 100644
index 0000000000000000000000000000000000000000..5dcdfbb653ed664cf23e9b25de1b5d11633c434a
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_formats.h
@@ -0,0 +1,107 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_FORMATS_H
+#define _SDE_FORMATS_H
+
+#include <drm/drm_fourcc.h>
+#include "sde_hw_mdss.h"
+
+/**
+ * sde_get_sde_format_ext() - Returns sde format structure pointer.
+ * @format:          DRM FourCC Code
+ * @modifiers:       format modifier array from client, one per plane
+ * @modifiers_len:   number of planes and array size for plane_modifiers
+ */
+const struct sde_format *sde_get_sde_format_ext(
+		const uint32_t format,
+		const uint64_t *modifiers,
+		const uint32_t modifiers_len);
+
+#define sde_get_sde_format(f) sde_get_sde_format_ext(f, NULL, 0)
+
+/**
+ * sde_get_msm_format - get an sde_format by its msm_format base
+ *                     callback function registers with the msm_kms layer
+ * @kms:             kms driver
+ * @format:          DRM FourCC Code
+ * @modifiers:       format modifier array from client, one per plane
+ * @modifiers_len:   number of planes and array size for plane_modifiers
+ */
+const struct msm_format *sde_get_msm_format(
+		struct msm_kms *kms,
+		const uint32_t format,
+		const uint64_t *modifiers,
+		const uint32_t modifiers_len);
+
+/**
+ * sde_populate_formats - populate the given array with fourcc codes supported
+ * @format_list:       pointer to list of possible formats
+ * @pixel_formats:     array to populate with fourcc codes
+ * @pixel_modifiers:   array to populate with drm modifiers, can be NULL
+ * @pixel_formats_max: length of pixel formats array
+ * Return: number of elements populated
+ */
+uint32_t sde_populate_formats(
+		const struct sde_format_extended *format_list,
+		uint32_t *pixel_formats,
+		uint64_t *pixel_modifiers,
+		uint32_t pixel_formats_max);
+
+/**
+ * sde_format_check_modified_format - validate format and buffers for
+ *                   sde non-standard, i.e. modified format
+ * @kms:             kms driver
+ * @msm_fmt:         pointer to the msm_fmt base pointer of an sde_format
+ * @cmd:             fb_cmd2 structure user request
+ * @bos:             gem buffer object list
+ *
+ * Return: error code on failure, 0 on success
+ */
+int sde_format_check_modified_format(
+		const struct msm_kms *kms,
+		const struct msm_format *msm_fmt,
+		const struct drm_mode_fb_cmd2 *cmd,
+		struct drm_gem_object **bos);
+
+/**
+ * sde_format_populate_layout - populate the given format layout based on
+ *                     mmu, fb, and format found in the fb
+ * @mmu_id:            mmu id handle
+ * @fb:                framebuffer pointer
+ * @fmtl:              format layout structure to populate
+ *
+ * Return: error code on failure, -EAGAIN if success but the addresses
+ *         are the same as before or 0 if new addresses were populated
+ */
+int sde_format_populate_layout(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_hw_fmt_layout *fmtl);
+
+/**
+ * sde_format_populate_layout_with_roi - populate the given format layout
+ *                     based on mmu, fb, roi, and format found in the fb
+ * @mmu_id:            mmu id handle
+ * @fb:                framebuffer pointer
+ * @roi:               region of interest (optional)
+ * @fmtl:              format layout structure to populate
+ *
+ * Return: error code on failure, 0 on success
+ */
+int sde_format_populate_layout_with_roi(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_rect *roi,
+		struct sde_hw_fmt_layout *fmtl);
+
+#endif /*_SDE_FORMATS_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
new file mode 100644
index 0000000000000000000000000000000000000000..31a6d985c38f9f71a623904b57599e6e7f76fee4
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -0,0 +1,1998 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/slab.h>
+#include <linux/of_address.h>
+
+#include "sde_hw_mdss.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_catalog_format.h"
+#include "sde_kms.h"
+
+/*************************************************************
+ * MACRO DEFINITION
+ *************************************************************/
+
+/**
+ * Max hardware block in certain hardware. For ex: sspp pipes
+ * can have QSEED, pcc, igc, pa, csc, etc. This count is max
+ * 12 based on software design. It should be increased if any of the
+ * hardware block has more subblocks.
+ */
+#define MAX_SDE_HW_BLK  12
+
+/* each entry will have register address and bit offset in that register */
+#define MAX_BIT_OFFSET 2
+
+/* default line width for sspp */
+#define DEFAULT_SDE_LINE_WIDTH 2048
+
+/* max mixer blend stages */
+#define DEFAULT_SDE_MIXER_BLENDSTAGES 7
+
+/* max bank bit for macro tile and ubwc format */
+#define DEFAULT_SDE_HIGHEST_BANK_BIT 15
+
+/* default hardware block size if dtsi entry is not present */
+#define DEFAULT_SDE_HW_BLOCK_LEN 0x100
+
+/* default rects for multi rect case */
+#define DEFAULT_SDE_SSPP_MAX_RECTS 1
+
+/* total number of intf - dp, dsi, hdmi */
+#define INTF_COUNT			3
+
+#define MAX_SSPP_UPSCALE		20
+#define MAX_SSPP_DOWNSCALE		4
+#define SSPP_UNITY_SCALE		1
+
+#define MAX_HORZ_DECIMATION		4
+#define MAX_VERT_DECIMATION		4
+
+#define MAX_SPLIT_DISPLAY_CTL		2
+#define MAX_PP_SPLIT_DISPLAY_CTL	1
+
+#define MDSS_BASE_OFFSET		0x0
+
+#define ROT_LM_OFFSET			3
+#define LINE_LM_OFFSET			5
+#define LINE_MODE_WB_OFFSET		2
+
+/* maximum XIN halt timeout in usec */
+#define VBIF_XIN_HALT_TIMEOUT		0x4000
+
+#define DEFAULT_CREQ_LUT_NRT		0x0
+#define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
+
+/* access property value based on prop_type and hardware index */
+#define PROP_VALUE_ACCESS(p, i, j)		((p + i)->value[j])
+
+/*
+ * access element within PROP_TYPE_BIT_OFFSET_ARRAYs based on prop_type,
+ * hardware index and offset array index
+ */
+#define PROP_BITVALUE_ACCESS(p, i, j, k)	((p + i)->bit_value[j][k])
+
+/*************************************************************
+ *  DTSI PROPERTY INDEX
+ *************************************************************/
+enum {
+	HW_OFF,
+	HW_LEN,
+	HW_PROP_MAX,
+};
+
+enum sde_prop {
+	SDE_OFF,
+	SDE_LEN,
+	SSPP_LINEWIDTH,
+	MIXER_LINEWIDTH,
+	MIXER_BLEND,
+	WB_LINEWIDTH,
+	BANK_BIT,
+	QSEED_TYPE,
+	CSC_TYPE,
+	PANIC_PER_PIPE,
+	CDP,
+	SRC_SPLIT,
+	SDE_PROP_MAX,
+};
+
+enum {
+	PERF_MAX_BW_LOW,
+	PERF_MAX_BW_HIGH,
+	PERF_PROP_MAX,
+};
+
+enum {
+	SSPP_OFF,
+	SSPP_SIZE,
+	SSPP_TYPE,
+	SSPP_XIN,
+	SSPP_CLK_CTRL,
+	SSPP_CLK_STATUS,
+	SSPP_DANGER,
+	SSPP_SAFE,
+	SSPP_MAX_RECTS,
+	SSPP_SCALE_SIZE,
+	SSPP_VIG_BLOCKS,
+	SSPP_RGB_BLOCKS,
+	SSPP_PROP_MAX,
+};
+
+enum {
+	VIG_QSEED_OFF,
+	VIG_CSC_OFF,
+	VIG_HSIC_PROP,
+	VIG_MEMCOLOR_PROP,
+	VIG_PCC_PROP,
+	VIG_PROP_MAX,
+};
+
+enum {
+	RGB_SCALER_OFF,
+	RGB_PCC_PROP,
+	RGB_PROP_MAX,
+};
+
+enum {
+	INTF_OFF,
+	INTF_LEN,
+	INTF_PREFETCH,
+	INTF_TYPE,
+	INTF_PROP_MAX,
+};
+
+enum {
+	PP_OFF,
+	PP_LEN,
+	TE_OFF,
+	TE_LEN,
+	TE2_OFF,
+	TE2_LEN,
+	DSC_OFF,
+	DSC_LEN,
+	PP_SLAVE,
+	PP_PROP_MAX,
+};
+
+enum {
+	DSPP_OFF,
+	DSPP_SIZE,
+	DSPP_BLOCKS,
+	DSPP_PROP_MAX,
+};
+
+enum {
+	DSPP_IGC_PROP,
+	DSPP_PCC_PROP,
+	DSPP_GC_PROP,
+	DSPP_HSIC_PROP,
+	DSPP_MEMCOLOR_PROP,
+	DSPP_SIXZONE_PROP,
+	DSPP_GAMUT_PROP,
+	DSPP_DITHER_PROP,
+	DSPP_HIST_PROP,
+	DSPP_VLUT_PROP,
+	DSPP_BLOCKS_PROP_MAX,
+};
+
+enum {
+	AD_OFF,
+	AD_VERSION,
+	AD_PROP_MAX,
+};
+
+enum {
+	MIXER_OFF,
+	MIXER_LEN,
+	MIXER_BLOCKS,
+	MIXER_PROP_MAX,
+};
+
+enum {
+	MIXER_GC_PROP,
+	MIXER_BLOCKS_PROP_MAX,
+};
+
+enum {
+	WB_OFF,
+	WB_LEN,
+	WB_ID,
+	WB_XIN_ID,
+	WB_CLK_CTRL,
+	WB_PROP_MAX,
+};
+
+enum {
+	VBIF_OFF,
+	VBIF_LEN,
+	VBIF_ID,
+	VBIF_DEFAULT_OT_RD_LIMIT,
+	VBIF_DEFAULT_OT_WR_LIMIT,
+	VBIF_DYNAMIC_OT_RD_LIMIT,
+	VBIF_DYNAMIC_OT_WR_LIMIT,
+	VBIF_PROP_MAX,
+};
+
+/*************************************************************
+ * dts property definition
+ *************************************************************/
+enum prop_type {
+	PROP_TYPE_BOOL,
+	PROP_TYPE_U32,
+	PROP_TYPE_U32_ARRAY,
+	PROP_TYPE_STRING,
+	PROP_TYPE_STRING_ARRAY,
+	PROP_TYPE_BIT_OFFSET_ARRAY,
+	PROP_TYPE_NODE,
+};
+
+struct sde_prop_type {
+	/* use property index from enum property for readability purpose */
+	u8 id;
+	/* it should be property name based on dtsi documentation */
+	char *prop_name;
+	/**
+	 * if property is marked mandatory then it will fail parsing
+	 * when property is not present
+	 */
+	u32  is_mandatory;
+	/* property type based on "enum prop_type"  */
+	enum prop_type type;
+};
+
+struct sde_prop_value {
+	u32 value[MAX_SDE_HW_BLK];
+	u32 bit_value[MAX_SDE_HW_BLK][MAX_BIT_OFFSET];
+};
+
+/*************************************************************
+ * dts property list
+ *************************************************************/
+static struct sde_prop_type sde_prop[] = {
+	{SDE_OFF, "qcom,sde-off", true, PROP_TYPE_U32},
+	{SDE_LEN, "qcom,sde-len", false, PROP_TYPE_U32},
+	{SSPP_LINEWIDTH, "qcom,sde-sspp-linewidth", false, PROP_TYPE_U32},
+	{MIXER_LINEWIDTH, "qcom,sde-mixer-linewidth", false, PROP_TYPE_U32},
+	{MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32},
+	{WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32},
+	{BANK_BIT, "qcom,sde-highest-bank-bit", false, PROP_TYPE_U32},
+	{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
+	{CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},
+	{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
+	{CDP, "qcom,sde-has-cdp", false, PROP_TYPE_BOOL},
+	{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
+};
+
+static struct sde_prop_type sde_perf_prop[] = {
+	{PERF_MAX_BW_LOW, "qcom,sde-max-bw-low-kbps", false, PROP_TYPE_U32},
+	{PERF_MAX_BW_HIGH, "qcom,sde-max-bw-high-kbps", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type sspp_prop[] = {
+	{SSPP_OFF, "qcom,sde-sspp-off", true, PROP_TYPE_U32_ARRAY},
+	{SSPP_SIZE, "qcom,sde-sspp-src-size", false, PROP_TYPE_U32},
+	{SSPP_TYPE, "qcom,sde-sspp-type", true, PROP_TYPE_STRING_ARRAY},
+	{SSPP_XIN, "qcom,sde-sspp-xin-id", true, PROP_TYPE_U32_ARRAY},
+	{SSPP_CLK_CTRL, "qcom,sde-sspp-clk-ctrl", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
+	{SSPP_CLK_STATUS, "qcom,sde-sspp-clk-status", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
+	{SSPP_DANGER, "qcom,sde-sspp-danger-lut", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_SAFE, "qcom,sde-sspp-safe-lut", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_MAX_RECTS, "qcom,sde-sspp-max-rects", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_SCALE_SIZE, "qcom,sde-sspp-scale-size", false, PROP_TYPE_U32},
+	{SSPP_VIG_BLOCKS, "qcom,sde-sspp-vig-blocks", false, PROP_TYPE_NODE},
+	{SSPP_RGB_BLOCKS, "qcom,sde-sspp-rgb-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type vig_prop[] = {
+	{VIG_QSEED_OFF, "qcom,sde-vig-qseed-off", false, PROP_TYPE_U32},
+	{VIG_CSC_OFF, "qcom,sde-vig-csc-off", false, PROP_TYPE_U32},
+	{VIG_HSIC_PROP, "qcom,sde-vig-hsic", false, PROP_TYPE_U32_ARRAY},
+	{VIG_MEMCOLOR_PROP, "qcom,sde-vig-memcolor", false,
+		PROP_TYPE_U32_ARRAY},
+	{VIG_PCC_PROP, "qcom,sde-vig-pcc", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type rgb_prop[] = {
+	{RGB_SCALER_OFF, "qcom,sde-rgb-scaler-off", false, PROP_TYPE_U32},
+	{RGB_PCC_PROP, "qcom,sde-rgb-pcc", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type ctl_prop[] = {
+	{HW_OFF, "qcom,sde-ctl-off", true, PROP_TYPE_U32_ARRAY},
+	{HW_LEN, "qcom,sde-ctl-size", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type mixer_prop[] = {
+	{MIXER_OFF, "qcom,sde-mixer-off", true, PROP_TYPE_U32_ARRAY},
+	{MIXER_LEN, "qcom,sde-mixer-size", false, PROP_TYPE_U32},
+	{MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type mixer_blocks_prop[] = {
+	{MIXER_GC_PROP, "qcom,sde-mixer-gc", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type dspp_prop[] = {
+	{DSPP_OFF, "qcom,sde-dspp-off", true, PROP_TYPE_U32_ARRAY},
+	{DSPP_SIZE, "qcom,sde-dspp-size", false, PROP_TYPE_U32},
+	{DSPP_BLOCKS, "qcom,sde-dspp-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type dspp_blocks_prop[] = {
+	{DSPP_IGC_PROP, "qcom,sde-dspp-igc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_PCC_PROP, "qcom,sde-dspp-pcc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_GC_PROP, "qcom,sde-dspp-gc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_HSIC_PROP, "qcom,sde-dspp-hsic", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_MEMCOLOR_PROP, "qcom,sde-dspp-memcolor", false,
+		PROP_TYPE_U32_ARRAY},
+	{DSPP_SIXZONE_PROP, "qcom,sde-dspp-sixzone", false,
+		PROP_TYPE_U32_ARRAY},
+	{DSPP_GAMUT_PROP, "qcom,sde-dspp-gamut", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_DITHER_PROP, "qcom,sde-dspp-dither", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_HIST_PROP, "qcom,sde-dspp-hist", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_VLUT_PROP, "qcom,sde-dspp-vlut", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type ad_prop[] = {
+	{AD_OFF, "qcom,sde-dspp-ad-off", false, PROP_TYPE_U32_ARRAY},
+	{AD_VERSION, "qcom,sde-dspp-ad-version", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type pp_prop[] = {
+	{PP_OFF, "qcom,sde-pp-off", true, PROP_TYPE_U32_ARRAY},
+	{PP_LEN, "qcom,sde-pp-size", false, PROP_TYPE_U32},
+	{TE_OFF, "qcom,sde-te-off", false, PROP_TYPE_U32_ARRAY},
+	{TE_LEN, "qcom,sde-te-size", false, PROP_TYPE_U32},
+	{TE2_OFF, "qcom,sde-te2-off", false, PROP_TYPE_U32_ARRAY},
+	{TE2_LEN, "qcom,sde-te2-size", false, PROP_TYPE_U32},
+	{DSC_OFF, "qcom,sde-dsc-off", false, PROP_TYPE_U32_ARRAY},
+	{DSC_LEN, "qcom,sde-dsc-size", false, PROP_TYPE_U32},
+	{PP_SLAVE, "qcom,sde-pp-slave", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type cdm_prop[] = {
+	{HW_OFF, "qcom,sde-cdm-off", false, PROP_TYPE_U32_ARRAY},
+	{HW_LEN, "qcom,sde-cdm-size", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type intf_prop[] = {
+	{INTF_OFF, "qcom,sde-intf-off", true, PROP_TYPE_U32_ARRAY},
+	{INTF_LEN, "qcom,sde-intf-size", false, PROP_TYPE_U32},
+	{INTF_PREFETCH, "qcom,sde-intf-max-prefetch-lines", false,
+						PROP_TYPE_U32_ARRAY},
+	{INTF_TYPE, "qcom,sde-intf-type", false, PROP_TYPE_STRING_ARRAY},
+};
+
+static struct sde_prop_type wb_prop[] = {
+	{WB_OFF, "qcom,sde-wb-off", true, PROP_TYPE_U32_ARRAY},
+	{WB_LEN, "qcom,sde-wb-size", false, PROP_TYPE_U32},
+	{WB_ID, "qcom,sde-wb-id", true, PROP_TYPE_U32_ARRAY},
+	{WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
+	{WB_CLK_CTRL, "qcom,sde-wb-clk-ctrl", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
+};
+
+static struct sde_prop_type vbif_prop[] = {
+	{VBIF_OFF, "qcom,sde-vbif-off", true, PROP_TYPE_U32_ARRAY},
+	{VBIF_LEN, "qcom,sde-vbif-size", false, PROP_TYPE_U32},
+	{VBIF_ID, "qcom,sde-vbif-id", false, PROP_TYPE_U32_ARRAY},
+	{VBIF_DEFAULT_OT_RD_LIMIT, "qcom,sde-vbif-default-ot-rd-limit", false,
+		PROP_TYPE_U32},
+	{VBIF_DEFAULT_OT_WR_LIMIT, "qcom,sde-vbif-default-ot-wr-limit", false,
+		PROP_TYPE_U32},
+	{VBIF_DYNAMIC_OT_RD_LIMIT, "qcom,sde-vbif-dynamic-ot-rd-limit", false,
+		PROP_TYPE_U32_ARRAY},
+	{VBIF_DYNAMIC_OT_WR_LIMIT, "qcom,sde-vbif-dynamic-ot-wr-limit", false,
+		PROP_TYPE_U32_ARRAY},
+};
+
+/*************************************************************
+ * static API list
+ *************************************************************/
+static int _parse_dt_u32_handler(struct device_node *np,
+	char *prop_name, u32 *offsets, int len, bool mandatory)
+{
+	int rc = of_property_read_u32_array(np, prop_name, offsets, len);
+
+	if (rc && mandatory)
+		SDE_ERROR("mandatory prop: %s u32 array read len:%d\n",
+				prop_name, len);
+	else if (rc)
+		SDE_DEBUG("optional prop: %s u32 array read len:%d\n",
+				prop_name, len);
+
+	return rc;
+}
+
+static int _parse_dt_bit_offset(struct device_node *np,
+	char *prop_name, struct sde_prop_value *prop_value, u32 prop_index,
+	u32 count, bool mandatory)
+{
+	int rc = 0, len, i, j;
+	const u32 *arr;
+
+	arr = of_get_property(np, prop_name, &len);
+	if (arr) {
+		len /= sizeof(u32);
+		len &= ~0x1;
+		for (i = 0, j = 0; i < len; j++) {
+			PROP_BITVALUE_ACCESS(prop_value, prop_index, j, 0) =
+				be32_to_cpu(arr[i]);
+			i++;
+			PROP_BITVALUE_ACCESS(prop_value, prop_index, j, 1) =
+				be32_to_cpu(arr[i]);
+			i++;
+		}
+	} else {
+		if (mandatory) {
+			SDE_ERROR("error mandatory property '%s' not found\n",
+				prop_name);
+			rc = -EINVAL;
+		} else {
+			SDE_DEBUG("error optional property '%s' not found\n",
+				prop_name);
+		}
+	}
+
+	return rc;
+}
+
+static int _validate_dt_entry(struct device_node *np,
+	struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
+	int *off_count)
+{
+	int rc = 0, i, val;
+	struct device_node *snp = NULL;
+
+	if (off_count) {
+		*off_count = of_property_count_u32_elems(np,
+				sde_prop[0].prop_name);
+		if ((*off_count > MAX_BLOCKS) || (*off_count < 0)) {
+			if (sde_prop[0].is_mandatory) {
+				SDE_ERROR("invalid hw offset prop name:%s\"\
+					  count: %d\n",
+					sde_prop[0].prop_name, *off_count);
+				rc = -EINVAL;
+			}
+			*off_count = 0;
+			return rc;
+		}
+	}
+
+	for (i = 0; i < prop_size; i++) {
+		switch (sde_prop[i].type) {
+		case PROP_TYPE_U32:
+			rc = of_property_read_u32(np, sde_prop[i].prop_name,
+				&val);
+			break;
+		case PROP_TYPE_U32_ARRAY:
+			prop_count[i] = of_property_count_u32_elems(np,
+				sde_prop[i].prop_name);
+			if (prop_count[i] < 0)
+				rc = prop_count[i];
+			break;
+		case PROP_TYPE_STRING_ARRAY:
+			prop_count[i] = of_property_count_strings(np,
+				sde_prop[i].prop_name);
+			if (prop_count[i] < 0)
+				rc = prop_count[i];
+			break;
+		case PROP_TYPE_BIT_OFFSET_ARRAY:
+			of_get_property(np, sde_prop[i].prop_name, &val);
+			prop_count[i] = val / (MAX_BIT_OFFSET * sizeof(u32));
+			break;
+		case PROP_TYPE_NODE:
+			snp = of_get_child_by_name(np,
+					sde_prop[i].prop_name);
+			if (!snp)
+				rc = -EINVAL;
+			break;
+		default:
+			SDE_DEBUG("invalid property type:%d\n",
+							sde_prop[i].type);
+			break;
+		}
+		SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+			prop_count:%d\n", i, sde_prop[i].prop_name,
+			sde_prop[i].type, prop_count[i]);
+
+		if (rc && sde_prop[i].is_mandatory &&
+		   ((sde_prop[i].type == PROP_TYPE_U32) ||
+		    (sde_prop[i].type == PROP_TYPE_NODE))) {
+			SDE_ERROR("prop:%s not present\n",
+						sde_prop[i].prop_name);
+			goto end;
+		} else if (sde_prop[i].type == PROP_TYPE_U32 ||
+			sde_prop[i].type == PROP_TYPE_BOOL ||
+			sde_prop[i].type == PROP_TYPE_NODE) {
+			rc = 0;
+			continue;
+		}
+
+		if (off_count && (prop_count[i] != *off_count) &&
+				sde_prop[i].is_mandatory) {
+			SDE_ERROR("prop:%s count:%d is different compared to \"\
+				offset array:%d\n", sde_prop[i].prop_name,
+				prop_count[i], *off_count);
+			rc = -EINVAL;
+			goto end;
+		} else if (off_count && prop_count[i] != *off_count) {
+			SDE_DEBUG("prop:%s count:%d is different compared to \"\
+				offset array:%d\n", sde_prop[i].prop_name,
+				prop_count[i], *off_count);
+			rc = 0;
+			prop_count[i] = 0;
+		}
+		if (!off_count && prop_count[i] < 0) {
+			prop_count[i] = 0;
+			if (sde_prop[i].is_mandatory) {
+				SDE_ERROR("prop:%s count:%d is negative\n",
+					sde_prop[i].prop_name, prop_count[i]);
+				rc = -EINVAL;
+			} else {
+				rc = 0;
+				SDE_DEBUG("prop:%s count:%d is negative\n",
+					sde_prop[i].prop_name, prop_count[i]);
+			}
+		}
+	}
+
+end:
+	return rc;
+}
+
+static int _read_dt_entry(struct device_node *np,
+	struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
+	bool *prop_exists,
+	struct sde_prop_value *prop_value)
+{
+	int rc = 0, i, j;
+
+	for (i = 0; i < prop_size; i++) {
+		prop_exists[i] = true;
+		switch (sde_prop[i].type) {
+		case PROP_TYPE_U32:
+			rc = of_property_read_u32(np, sde_prop[i].prop_name,
+				&PROP_VALUE_ACCESS(prop_value, i, 0));
+			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+				 value:0x%x\n", i, sde_prop[i].prop_name,
+				sde_prop[i].type,
+				PROP_VALUE_ACCESS(prop_value, i, 0));
+			if (rc)
+				prop_exists[i] = false;
+			break;
+		case PROP_TYPE_BOOL:
+			PROP_VALUE_ACCESS(prop_value, i, 0) =
+				of_property_read_bool(np,
+					sde_prop[i].prop_name);
+			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+				value:0x%x\n", i, sde_prop[i].prop_name,
+				sde_prop[i].type,
+				PROP_VALUE_ACCESS(prop_value, i, 0));
+			break;
+		case PROP_TYPE_U32_ARRAY:
+			rc = _parse_dt_u32_handler(np, sde_prop[i].prop_name,
+				&PROP_VALUE_ACCESS(prop_value, i, 0),
+				prop_count[i], sde_prop[i].is_mandatory);
+			if (rc && sde_prop[i].is_mandatory) {
+				SDE_ERROR("%s prop validation success but \"\
+					read failed\n", sde_prop[i].prop_name);
+				prop_exists[i] = false;
+				goto end;
+			} else {
+				if (rc)
+					prop_exists[i] = false;
+				/* only for debug purpose */
+				SDE_DEBUG("prop id:%d prop name:%s prop \"\
+					type:%d", i, sde_prop[i].prop_name,
+					sde_prop[i].type);
+				for (j = 0; j < prop_count[i]; j++)
+					SDE_DEBUG(" value[%d]:0x%x ", j,
+						PROP_VALUE_ACCESS(prop_value, i,
+								j));
+				SDE_DEBUG("\n");
+			}
+			break;
+		case PROP_TYPE_BIT_OFFSET_ARRAY:
+			rc = _parse_dt_bit_offset(np, sde_prop[i].prop_name,
+				prop_value, i, prop_count[i],
+				sde_prop[i].is_mandatory);
+			if (rc && sde_prop[i].is_mandatory) {
+				SDE_ERROR("%s prop validation success but \"\
+					read failed\n", sde_prop[i].prop_name);
+				prop_exists[i] = false;
+				goto end;
+			} else {
+				if (rc)
+					prop_exists[i] = false;
+				SDE_DEBUG("prop id:%d prop name:%s prop \"\
+					type:%d", i, sde_prop[i].prop_name,
+					sde_prop[i].type);
+				for (j = 0; j < prop_count[i]; j++)
+					SDE_DEBUG(" count[%d]: bit:0x%x \"\
+					off:0x%x \n", j,
+					PROP_BITVALUE_ACCESS(prop_value,
+						i, j, 0),
+					PROP_BITVALUE_ACCESS(prop_value,
+						i, j, 1));
+				SDE_DEBUG("\n");
+			}
+			break;
+		case PROP_TYPE_NODE:
+			/* Node will be parsed in calling function */
+			rc = 0;
+			break;
+		default:
+			SDE_DEBUG("invalid property type:%d\n",
+							sde_prop[i].type);
+			break;
+		}
+		rc = 0;
+	}
+
+end:
+	return rc;
+}
+
+static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	bool *prop_exists, struct sde_prop_value *prop_value, u32 *vig_count)
+{
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_VIG0 + *vig_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;
+	sblk->format_list = plane_formats_yuv;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
+	(*vig_count)++;
+
+	if (!prop_value)
+		return;
+
+	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
+		set_bit(SDE_SSPP_SCALER_QSEED2, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_QSEED_OFF, 0);
+	 } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
+		set_bit(SDE_SSPP_SCALER_QSEED3, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_QSEED_OFF, 0);
+	}
+
+	sblk->csc_blk.id = SDE_SSPP_CSC;
+	if (sde_cfg->csc_type == SDE_SSPP_CSC) {
+		set_bit(SDE_SSPP_CSC, &sspp->features);
+		sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
+							VIG_CSC_OFF, 0);
+	} else if (sde_cfg->csc_type == SDE_SSPP_CSC_10BIT) {
+		set_bit(SDE_SSPP_CSC_10BIT, &sspp->features);
+		sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
+							VIG_CSC_OFF, 0);
+	}
+
+	sblk->hsic_blk.id = SDE_SSPP_HSIC;
+	if (prop_exists[VIG_HSIC_PROP]) {
+		sblk->hsic_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_HSIC_PROP, 0);
+		sblk->hsic_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_HSIC_PROP, 1);
+		sblk->hsic_blk.len = 0;
+		set_bit(SDE_SSPP_HSIC, &sspp->features);
+	}
+
+	sblk->memcolor_blk.id = SDE_SSPP_MEMCOLOR;
+	if (prop_exists[VIG_MEMCOLOR_PROP]) {
+		sblk->memcolor_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_MEMCOLOR_PROP, 0);
+		sblk->memcolor_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_MEMCOLOR_PROP, 1);
+		sblk->memcolor_blk.len = 0;
+		set_bit(SDE_SSPP_MEMCOLOR, &sspp->features);
+	}
+
+	sblk->pcc_blk.id = SDE_SSPP_PCC;
+	if (prop_exists[VIG_PCC_PROP]) {
+		sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_PCC_PROP, 0);
+		sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_PCC_PROP, 1);
+		sblk->pcc_blk.len = 0;
+		set_bit(SDE_SSPP_PCC, &sspp->features);
+	}
+}
+
+static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	bool *prop_exists, struct sde_prop_value *prop_value, u32 *rgb_count)
+{
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_RGB0 + *rgb_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;
+	sblk->format_list = plane_formats;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
+	(*rgb_count)++;
+
+	if (!prop_value)
+		return;
+
+	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
+		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_SCALER_OFF, 0);
+	} else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
+		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_SCALER_OFF, 0);
+	}
+
+	sblk->pcc_blk.id = SDE_SSPP_PCC;
+	if (prop_exists[RGB_PCC_PROP]) {
+		sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_PCC_PROP, 0);
+		sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
+			RGB_PCC_PROP, 1);
+		sblk->pcc_blk.len = 0;
+		set_bit(SDE_SSPP_PCC, &sspp->features);
+	}
+}
+
+static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	struct sde_prop_value *prop_value, u32 *cursor_count)
+{
+	set_bit(SDE_SSPP_CURSOR, &sspp->features);
+	sblk->maxupscale = SSPP_UNITY_SCALE;
+	sblk->maxdwnscale = SSPP_UNITY_SCALE;
+	sspp->id = SSPP_CURSOR0 + *cursor_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;
+	sblk->format_list = plane_formats;
+	(*cursor_count)++;
+}
+
+static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	struct sde_prop_value *prop_value, u32 *dma_count)
+{
+	sblk->maxupscale = SSPP_UNITY_SCALE;
+	sblk->maxdwnscale = SSPP_UNITY_SCALE;
+	sspp->id = SSPP_DMA0 + *dma_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_DMA0 + *dma_count;
+	sblk->format_list = plane_formats;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
+	(*dma_count)++;
+}
+
+static int sde_sspp_parse_dt(struct device_node *np,
+	struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[SSPP_PROP_MAX], off_count, i, j;
+	int vig_prop_count[VIG_PROP_MAX], rgb_prop_count[RGB_PROP_MAX];
+	bool prop_exists[SSPP_PROP_MAX], vig_prop_exists[VIG_PROP_MAX];
+	bool rgb_prop_exists[RGB_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL;
+	struct sde_prop_value *vig_prop_value = NULL, *rgb_prop_value = NULL;
+	const char *type;
+	struct sde_sspp_cfg *sspp;
+	struct sde_sspp_sub_blks *sblk;
+	u32 vig_count = 0, dma_count = 0, rgb_count = 0, cursor_count = 0;
+	u32 danger_count = 0, safe_count = 0;
+	struct device_node *snp = NULL;
+
+	prop_value = kzalloc(SSPP_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &sspp_prop[SSPP_DANGER], 1,
+			&prop_count[SSPP_DANGER], &danger_count);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &sspp_prop[SSPP_SAFE], 1,
+			&prop_count[SSPP_SAFE], &safe_count);
+	if (rc)
+		goto end;
+
+	rc = _read_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop), prop_count,
+					prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	sde_cfg->sspp_count = off_count;
+
+	/* get vig feature dt properties if they exist */
+	snp = of_get_child_by_name(np, sspp_prop[SSPP_VIG_BLOCKS].prop_name);
+	if (snp) {
+		vig_prop_value = kzalloc(VIG_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+		if (!vig_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
+			vig_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
+				vig_prop_count, vig_prop_exists,
+				vig_prop_value);
+	}
+
+	/* get rgb feature dt properties if they exist */
+	snp = of_get_child_by_name(np, sspp_prop[SSPP_RGB_BLOCKS].prop_name);
+	if (snp) {
+		rgb_prop_value = kzalloc(RGB_PROP_MAX *
+					sizeof(struct sde_prop_value),
+					GFP_KERNEL);
+		if (!rgb_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
+			rgb_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
+				rgb_prop_count, rgb_prop_exists,
+				rgb_prop_value);
+	}
+
+	for (i = 0; i < off_count; i++) {
+		sspp = sde_cfg->sspp + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		sspp->sblk = sblk;
+
+		sspp->base = PROP_VALUE_ACCESS(prop_value, SSPP_OFF, i);
+		sblk->maxlinewidth = sde_cfg->max_sspp_linewidth;
+
+		set_bit(SDE_SSPP_SRC, &sspp->features);
+		sblk->src_blk.id = SDE_SSPP_SRC;
+
+		of_property_read_string_index(np,
+				sspp_prop[SSPP_TYPE].prop_name, i, &type);
+		if (!strcmp(type, "vig")) {
+			_sde_sspp_setup_vig(sde_cfg, sspp, sblk,
+				vig_prop_exists, vig_prop_value, &vig_count);
+		} else if (!strcmp(type, "rgb")) {
+			_sde_sspp_setup_rgb(sde_cfg, sspp, sblk,
+				rgb_prop_exists, rgb_prop_value, &rgb_count);
+		} else if (!strcmp(type, "cursor")) {
+			/* No prop values for cursor pipes */
+			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,
+								&cursor_count);
+		} else if (!strcmp(type, "dma")) {
+			/* No prop values for DMA pipes */
+			_sde_sspp_setup_dma(sde_cfg, sspp, sblk, NULL,
+								&dma_count);
+		} else {
+			SDE_ERROR("invalid sspp type:%s\n", type);
+			rc = -EINVAL;
+			goto end;
+		}
+
+		sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
+		sblk->maxvdeciexp = MAX_VERT_DECIMATION;
+
+		sspp->xin_id = PROP_VALUE_ACCESS(prop_value, SSPP_XIN, i);
+		sblk->danger_lut_linear =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 0);
+		sblk->danger_lut_tile =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 1);
+		sblk->danger_lut_nrt =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 2);
+		sblk->safe_lut_linear =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 0);
+		sblk->safe_lut_tile =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 1);
+		sblk->safe_lut_nrt =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 2);
+		sblk->creq_lut_nrt = DEFAULT_CREQ_LUT_NRT;
+		sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
+		sblk->src_blk.len = PROP_VALUE_ACCESS(prop_value, SSPP_SIZE, 0);
+
+		for (j = 0; j < sde_cfg->mdp_count; j++) {
+			sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].reg_off =
+				PROP_BITVALUE_ACCESS(prop_value,
+						SSPP_CLK_CTRL, i, 0);
+			sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].bit_off =
+				PROP_BITVALUE_ACCESS(prop_value,
+						SSPP_CLK_CTRL, i, 1);
+		}
+
+		SDE_DEBUG(
+			"xin:%d danger:%x/%x/%x safe:%x/%x/%x creq:%x ram:%d clk%d:%x/%d\n",
+			sspp->xin_id,
+			sblk->danger_lut_linear,
+			sblk->danger_lut_tile,
+			sblk->danger_lut_nrt,
+			sblk->safe_lut_linear,
+			sblk->safe_lut_tile,
+			sblk->safe_lut_nrt,
+			sblk->creq_lut_nrt,
+			sblk->pixel_ram_size,
+			sspp->clk_ctrl,
+			sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].reg_off,
+			sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].bit_off);
+	}
+
+end:
+	kfree(prop_value);
+	kfree(vig_prop_value);
+	kfree(rgb_prop_value);
+	return rc;
+}
+
+static int sde_ctl_parse_dt(struct device_node *np,
+		struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[HW_PROP_MAX], i;
+	bool prop_exists[HW_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL;
+	struct sde_ctl_cfg *ctl;
+	u32 off_count;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument input param\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(HW_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->ctl_count = off_count;
+
+	rc = _read_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		ctl = sde_cfg->ctl + i;
+		ctl->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
+		ctl->id = CTL_0 + i;
+
+		if (i < MAX_SPLIT_DISPLAY_CTL)
+			set_bit(SDE_CTL_SPLIT_DISPLAY, &ctl->features);
+		if (i < MAX_PP_SPLIT_DISPLAY_CTL)
+			set_bit(SDE_CTL_PINGPONG_SPLIT, &ctl->features);
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_mixer_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MIXER_PROP_MAX], i;
+	int blocks_prop_count[MIXER_BLOCKS_PROP_MAX];
+	bool prop_exists[MIXER_PROP_MAX];
+	bool blocks_prop_exists[MIXER_BLOCKS_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL, *blocks_prop_value = NULL;
+	u32 off_count, max_blendstages;
+	u32 blend_reg_base[] = {0x20, 0x50, 0x80, 0xb0, 0x230, 0x260, 0x290};
+	u32 lm_pair_mask[] = {LM_1, LM_0, LM_5, 0x0, 0x0, LM_2};
+	struct sde_lm_cfg *mixer;
+	struct sde_lm_sub_blks *sblk;
+	int pp_count, dspp_count;
+	u32 pp_idx, dspp_idx;
+	struct device_node *snp = NULL;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument input param\n");
+		rc = -EINVAL;
+		goto end;
+	}
+	max_blendstages = sde_cfg->max_mixer_blendstages;
+
+	prop_value = kzalloc(MIXER_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->mixer_count = off_count;
+
+	rc = _read_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	pp_count = sde_cfg->pingpong_count;
+	dspp_count = sde_cfg->dspp_count;
+
+	/* get mixer feature dt properties if they exist */
+	snp = of_get_child_by_name(np, mixer_prop[MIXER_BLOCKS].prop_name);
+	if (snp) {
+		blocks_prop_value = kzalloc(MIXER_BLOCKS_PROP_MAX *
+				MAX_SDE_HW_BLK * sizeof(struct sde_prop_value),
+				GFP_KERNEL);
+		if (!blocks_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, mixer_blocks_prop,
+			ARRAY_SIZE(mixer_blocks_prop), blocks_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, mixer_blocks_prop,
+				ARRAY_SIZE(mixer_blocks_prop),
+				blocks_prop_count, blocks_prop_exists,
+				blocks_prop_value);
+	}
+
+	for (i = 0, pp_idx = 0, dspp_idx = 0; i < off_count; i++) {
+		mixer = sde_cfg->mixer + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		mixer->sblk = sblk;
+
+		mixer->base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);
+		mixer->len = PROP_VALUE_ACCESS(prop_value, MIXER_LEN, 0);
+		mixer->id = LM_0 + i;
+		if (!prop_exists[MIXER_LEN])
+			mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+		if (lm_pair_mask[i])
+			mixer->lm_pair_mask = 1 << lm_pair_mask[i];
+
+		sblk->maxblendstages = max_blendstages;
+		sblk->maxwidth = sde_cfg->max_mixer_width;
+		memcpy(sblk->blendstage_base, blend_reg_base, sizeof(u32) *
+			min_t(u32, MAX_BLOCKS, min_t(u32,
+			ARRAY_SIZE(blend_reg_base), max_blendstages)));
+		if (sde_cfg->has_src_split)
+			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);
+
+		if ((i < ROT_LM_OFFSET) || (i >= LINE_LM_OFFSET)) {
+			mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
+								: PINGPONG_MAX;
+			mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
+								: DSPP_MAX;
+			pp_count--;
+			dspp_count--;
+			pp_idx++;
+			dspp_idx++;
+		} else {
+			mixer->pingpong = PINGPONG_MAX;
+			mixer->dspp = DSPP_MAX;
+		}
+
+		sblk->gc.id = SDE_MIXER_GC;
+		if (blocks_prop_value && blocks_prop_exists[MIXER_GC_PROP]) {
+			sblk->gc.base = PROP_VALUE_ACCESS(blocks_prop_value,
+					MIXER_GC_PROP, 0);
+			sblk->gc.version = PROP_VALUE_ACCESS(blocks_prop_value,
+					MIXER_GC_PROP, 1);
+			sblk->gc.len = 0;
+			set_bit(SDE_MIXER_GC, &mixer->features);
+		}
+	}
+
+end:
+	kfree(prop_value);
+	kfree(blocks_prop_value);
+	return rc;
+}
+
+static int sde_intf_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[INTF_PROP_MAX], i;
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[INTF_PROP_MAX];
+	u32 off_count;
+	u32 dsi_count = 0, none_count = 0, hdmi_count = 0, dp_count = 0;
+	const char *type;
+	struct sde_intf_cfg *intf;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(INTF_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->intf_count = off_count;
+
+	rc = _read_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		intf = sde_cfg->intf + i;
+		intf->base = PROP_VALUE_ACCESS(prop_value, INTF_OFF, i);
+		intf->len = PROP_VALUE_ACCESS(prop_value, INTF_LEN, 0);
+		intf->id = INTF_0 + i;
+		if (!prop_exists[INTF_LEN])
+			intf->len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+		intf->prog_fetch_lines_worst_case =
+				PROP_VALUE_ACCESS(prop_value, INTF_PREFETCH, i);
+
+		of_property_read_string_index(np,
+				intf_prop[INTF_TYPE].prop_name, i, &type);
+		if (!strcmp(type, "dsi")) {
+			intf->type = INTF_DSI;
+			intf->controller_id = dsi_count;
+			dsi_count++;
+		} else if (!strcmp(type, "hdmi")) {
+			intf->type = INTF_HDMI;
+			intf->controller_id = hdmi_count;
+			hdmi_count++;
+		} else if (!strcmp(type, "dp")) {
+			intf->type = INTF_DP;
+			intf->controller_id = dp_count;
+			dp_count++;
+		} else {
+			intf->type = INTF_NONE;
+			intf->controller_id = none_count;
+			none_count++;
+		}
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[WB_PROP_MAX], i, j;
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[WB_PROP_MAX];
+	u32 off_count;
+	struct sde_wb_cfg *wb;
+	struct sde_wb_sub_blocks *sblk;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(WB_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->wb_count = off_count;
+
+	rc = _read_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		wb = sde_cfg->wb + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		wb->sblk = sblk;
+
+		wb->base = PROP_VALUE_ACCESS(prop_value, WB_OFF, i);
+		wb->id = WB_0 + PROP_VALUE_ACCESS(prop_value, WB_ID, i);
+		wb->clk_ctrl = SDE_CLK_CTRL_WB0 +
+			PROP_VALUE_ACCESS(prop_value, WB_ID, i);
+		wb->xin_id = PROP_VALUE_ACCESS(prop_value, WB_XIN_ID, i);
+		wb->vbif_idx = VBIF_NRT;
+		wb->len = PROP_VALUE_ACCESS(prop_value, WB_LEN, 0);
+		wb->format_list = wb2_formats;
+		if (!prop_exists[WB_LEN])
+			wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
+		sblk->maxlinewidth = sde_cfg->max_wb_linewidth;
+
+		if (wb->id >= LINE_MODE_WB_OFFSET)
+			set_bit(SDE_WB_LINE_MODE, &wb->features);
+		else
+			set_bit(SDE_WB_BLOCK_MODE, &wb->features);
+		set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
+		set_bit(SDE_WB_YUV_CONFIG, &wb->features);
+
+		for (j = 0; j < sde_cfg->mdp_count; j++) {
+			sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].reg_off =
+				PROP_BITVALUE_ACCESS(prop_value,
+						WB_CLK_CTRL, i, 0);
+			sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].bit_off =
+				PROP_BITVALUE_ACCESS(prop_value,
+						WB_CLK_CTRL, i, 1);
+		}
+
+		SDE_DEBUG(
+			"wb:%d xin:%d vbif:%d clk%d:%x/%d\n",
+			wb->id - WB_0,
+			wb->xin_id,
+			wb->vbif_idx,
+			wb->clk_ctrl,
+			sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].reg_off,
+			sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].bit_off);
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static void _sde_dspp_setup_blocks(struct sde_mdss_cfg *sde_cfg,
+	struct sde_dspp_cfg *dspp, struct sde_dspp_sub_blks *sblk,
+	bool *prop_exists, struct sde_prop_value *prop_value)
+{
+	sblk->igc.id = SDE_DSPP_IGC;
+	if (prop_exists[DSPP_IGC_PROP]) {
+		sblk->igc.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_IGC_PROP, 0);
+		sblk->igc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_IGC_PROP, 1);
+		sblk->igc.len = 0;
+		set_bit(SDE_DSPP_IGC, &dspp->features);
+	}
+
+	sblk->pcc.id = SDE_DSPP_PCC;
+	if (prop_exists[DSPP_PCC_PROP]) {
+		sblk->pcc.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_PCC_PROP, 0);
+		sblk->pcc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_PCC_PROP, 1);
+		sblk->pcc.len = 0;
+		set_bit(SDE_DSPP_PCC, &dspp->features);
+	}
+
+	sblk->gc.id = SDE_DSPP_GC;
+	if (prop_exists[DSPP_GC_PROP]) {
+		sblk->gc.base = PROP_VALUE_ACCESS(prop_value, DSPP_GC_PROP, 0);
+		sblk->gc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GC_PROP, 1);
+		sblk->gc.len = 0;
+		set_bit(SDE_DSPP_GC, &dspp->features);
+	}
+
+	sblk->gamut.id = SDE_DSPP_GAMUT;
+	if (prop_exists[DSPP_GAMUT_PROP]) {
+		sblk->gamut.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GAMUT_PROP, 0);
+		sblk->gamut.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GAMUT_PROP, 1);
+		sblk->gamut.len = 0;
+		set_bit(SDE_DSPP_GAMUT, &dspp->features);
+	}
+
+	sblk->dither.id = SDE_DSPP_DITHER;
+	if (prop_exists[DSPP_DITHER_PROP]) {
+		sblk->dither.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_DITHER_PROP, 0);
+		sblk->dither.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_DITHER_PROP, 1);
+		sblk->dither.len = 0;
+		set_bit(SDE_DSPP_DITHER, &dspp->features);
+	}
+
+	sblk->hist.id = SDE_DSPP_HIST;
+	if (prop_exists[DSPP_HIST_PROP]) {
+		sblk->hist.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HIST_PROP, 0);
+		sblk->hist.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HIST_PROP, 1);
+		sblk->hist.len = 0;
+		set_bit(SDE_DSPP_HIST, &dspp->features);
+	}
+
+	sblk->hsic.id = SDE_DSPP_HSIC;
+	if (prop_exists[DSPP_HSIC_PROP]) {
+		sblk->hsic.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HSIC_PROP, 0);
+		sblk->hsic.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HSIC_PROP, 1);
+		sblk->hsic.len = 0;
+		set_bit(SDE_DSPP_HSIC, &dspp->features);
+	}
+
+	sblk->memcolor.id = SDE_DSPP_MEMCOLOR;
+	if (prop_exists[DSPP_MEMCOLOR_PROP]) {
+		sblk->memcolor.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_MEMCOLOR_PROP, 0);
+		sblk->memcolor.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_MEMCOLOR_PROP, 1);
+		sblk->memcolor.len = 0;
+		set_bit(SDE_DSPP_MEMCOLOR, &dspp->features);
+	}
+
+	sblk->sixzone.id = SDE_DSPP_SIXZONE;
+	if (prop_exists[DSPP_SIXZONE_PROP]) {
+		sblk->sixzone.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_SIXZONE_PROP, 0);
+		sblk->sixzone.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_SIXZONE_PROP, 1);
+		sblk->sixzone.len = 0;
+		set_bit(SDE_DSPP_SIXZONE, &dspp->features);
+	}
+
+	sblk->vlut.id = SDE_DSPP_VLUT;
+	if (prop_exists[DSPP_VLUT_PROP]) {
+		sblk->vlut.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_VLUT_PROP, 0);
+		sblk->vlut.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_VLUT_PROP, 1);
+		sblk->sixzone.len = 0;
+		set_bit(SDE_DSPP_VLUT, &dspp->features);
+	}
+}
+
+static int sde_dspp_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[DSPP_PROP_MAX], i;
+	int ad_prop_count[AD_PROP_MAX];
+	bool prop_exists[DSPP_PROP_MAX], ad_prop_exists[AD_PROP_MAX];
+	bool blocks_prop_exists[DSPP_BLOCKS_PROP_MAX];
+	struct sde_prop_value *ad_prop_value = NULL;
+	int blocks_prop_count[DSPP_BLOCKS_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL, *blocks_prop_value = NULL;
+	u32 off_count, ad_off_count;
+	struct sde_dspp_cfg *dspp;
+	struct sde_dspp_sub_blks *sblk;
+	struct device_node *snp = NULL;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(DSPP_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->dspp_count = off_count;
+
+	rc = _read_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	/* Parse AD dtsi entries */
+	ad_prop_value = kzalloc(AD_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!ad_prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+	rc = _validate_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop),
+		ad_prop_count, &ad_off_count);
+	if (rc)
+		goto end;
+	rc = _read_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop), ad_prop_count,
+		ad_prop_exists, ad_prop_value);
+	if (rc)
+		goto end;
+
+	/* get DSPP feature dt properties if they exist */
+	snp = of_get_child_by_name(np, dspp_prop[DSPP_BLOCKS].prop_name);
+	if (snp) {
+		blocks_prop_value = kzalloc(DSPP_BLOCKS_PROP_MAX *
+				MAX_SDE_HW_BLK * sizeof(struct sde_prop_value),
+				GFP_KERNEL);
+		if (!blocks_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, dspp_blocks_prop,
+			ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, dspp_blocks_prop,
+			ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count,
+			blocks_prop_exists, blocks_prop_value);
+		if (rc)
+			goto end;
+	}
+
+	for (i = 0; i < off_count; i++) {
+		dspp = sde_cfg->dspp + i;
+		dspp->base = PROP_VALUE_ACCESS(prop_value, DSPP_OFF, i);
+		dspp->id = DSPP_0 + i;
+
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		dspp->sblk = sblk;
+
+		if (blocks_prop_value)
+			_sde_dspp_setup_blocks(sde_cfg, dspp, sblk,
+					blocks_prop_exists, blocks_prop_value);
+
+		sblk->ad.id = SDE_DSPP_AD;
+		if (ad_prop_value && (i < ad_off_count) &&
+		    ad_prop_exists[AD_OFF]) {
+			sblk->ad.base = PROP_VALUE_ACCESS(ad_prop_value,
+				AD_OFF, i);
+			sblk->ad.version = PROP_VALUE_ACCESS(ad_prop_value,
+				AD_VERSION, 0);
+			set_bit(SDE_DSPP_AD, &dspp->features);
+		}
+	}
+
+end:
+	kfree(prop_value);
+	kfree(ad_prop_value);
+	kfree(blocks_prop_value);
+	return rc;
+}
+
+static int sde_cdm_parse_dt(struct device_node *np,
+				struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[HW_PROP_MAX], i;
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[HW_PROP_MAX];
+	u32 off_count;
+	struct sde_cdm_cfg *cdm;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(HW_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->cdm_count = off_count;
+
+	rc = _read_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		cdm = sde_cfg->cdm + i;
+		cdm->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
+		cdm->id = CDM_0 + i;
+		cdm->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
+
+		/* intf3 and wb2 for cdm block */
+		cdm->wb_connect = sde_cfg->wb_count ? BIT(WB_2) : BIT(31);
+		cdm->intf_connect = sde_cfg->intf_count ? BIT(INTF_3) : BIT(31);
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_vbif_parse_dt(struct device_node *np,
+				struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[VBIF_PROP_MAX], i, j, k;
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[VBIF_PROP_MAX];
+	u32 off_count, vbif_len, rd_len = 0, wr_len = 0;
+	struct sde_vbif_cfg *vbif;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(VBIF_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop),
+			prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_RD_LIMIT], 1,
+			&prop_count[VBIF_DYNAMIC_OT_RD_LIMIT], &rd_len);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_WR_LIMIT], 1,
+			&prop_count[VBIF_DYNAMIC_OT_WR_LIMIT], &wr_len);
+	if (rc)
+		goto end;
+
+	sde_cfg->vbif_count = off_count;
+
+	rc = _read_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	vbif_len = PROP_VALUE_ACCESS(prop_value, VBIF_LEN, 0);
+	if (!prop_exists[VBIF_LEN])
+		vbif_len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+	for (i = 0; i < off_count; i++) {
+		vbif = sde_cfg->vbif + i;
+		vbif->base = PROP_VALUE_ACCESS(prop_value, VBIF_OFF, i);
+		vbif->len = vbif_len;
+		vbif->id = VBIF_0 + PROP_VALUE_ACCESS(prop_value, VBIF_ID, i);
+
+		SDE_DEBUG("vbif:%d\n", vbif->id - VBIF_0);
+
+		vbif->xin_halt_timeout = VBIF_XIN_HALT_TIMEOUT;
+
+		vbif->default_ot_rd_limit = PROP_VALUE_ACCESS(prop_value,
+				VBIF_DEFAULT_OT_RD_LIMIT, 0);
+		SDE_DEBUG("default_ot_rd_limit=%u\n",
+				vbif->default_ot_rd_limit);
+
+		vbif->default_ot_wr_limit = PROP_VALUE_ACCESS(prop_value,
+				VBIF_DEFAULT_OT_WR_LIMIT, 0);
+		SDE_DEBUG("default_ot_wr_limit=%u\n",
+				vbif->default_ot_wr_limit);
+
+		vbif->dynamic_ot_rd_tbl.count =
+				prop_count[VBIF_DYNAMIC_OT_RD_LIMIT] / 2;
+		SDE_DEBUG("dynamic_ot_rd_tbl.count=%u\n",
+				vbif->dynamic_ot_rd_tbl.count);
+		if (vbif->dynamic_ot_rd_tbl.count) {
+			vbif->dynamic_ot_rd_tbl.cfg = kcalloc(
+				vbif->dynamic_ot_rd_tbl.count,
+				sizeof(struct sde_vbif_dynamic_ot_cfg),
+				GFP_KERNEL);
+			if (!vbif->dynamic_ot_rd_tbl.cfg) {
+				rc = -ENOMEM;
+				goto end;
+			}
+		}
+
+		for (j = 0, k = 0; j < vbif->dynamic_ot_rd_tbl.count; j++) {
+			vbif->dynamic_ot_rd_tbl.cfg[j].pps = (u64)
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_RD_LIMIT, k++);
+			vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit =
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_RD_LIMIT, k++);
+			SDE_DEBUG("dynamic_ot_rd_tbl[%d].cfg=<%llu %u>\n", j,
+				vbif->dynamic_ot_rd_tbl.cfg[j].pps,
+				vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit);
+		}
+
+		vbif->dynamic_ot_wr_tbl.count =
+				prop_count[VBIF_DYNAMIC_OT_WR_LIMIT] / 2;
+		SDE_DEBUG("dynamic_ot_wr_tbl.count=%u\n",
+				vbif->dynamic_ot_wr_tbl.count);
+		if (vbif->dynamic_ot_wr_tbl.count) {
+			vbif->dynamic_ot_wr_tbl.cfg = kcalloc(
+				vbif->dynamic_ot_wr_tbl.count,
+				sizeof(struct sde_vbif_dynamic_ot_cfg),
+				GFP_KERNEL);
+			if (!vbif->dynamic_ot_wr_tbl.cfg) {
+				rc = -ENOMEM;
+				goto end;
+			}
+		}
+
+		for (j = 0, k = 0; j < vbif->dynamic_ot_wr_tbl.count; j++) {
+			vbif->dynamic_ot_wr_tbl.cfg[j].pps = (u64)
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_WR_LIMIT, k++);
+			vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit =
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_WR_LIMIT, k++);
+			SDE_DEBUG("dynamic_ot_wr_tbl[%d].cfg=<%llu %u>\n", j,
+				vbif->dynamic_ot_wr_tbl.cfg[j].pps,
+				vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit);
+		}
+
+		if (vbif->default_ot_rd_limit || vbif->default_ot_wr_limit ||
+				vbif->dynamic_ot_rd_tbl.count ||
+				vbif->dynamic_ot_wr_tbl.count)
+			set_bit(SDE_VBIF_QOS_OTLIM, &vbif->features);
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[PP_PROP_MAX], i;
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[PP_PROP_MAX];
+	u32 off_count;
+	struct sde_pingpong_cfg *pp;
+	struct sde_pingpong_sub_blks *sblk;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(PP_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->pingpong_count = off_count;
+
+	rc = _read_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		pp = sde_cfg->pingpong + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		pp->sblk = sblk;
+
+		pp->base = PROP_VALUE_ACCESS(prop_value, PP_OFF, i);
+		pp->id = PINGPONG_0 + i;
+		pp->len = PROP_VALUE_ACCESS(prop_value, PP_LEN, 0);
+
+		sblk->te.base = PROP_VALUE_ACCESS(prop_value, TE_OFF, i);
+		sblk->te.id = SDE_PINGPONG_TE;
+		set_bit(SDE_PINGPONG_TE, &pp->features);
+
+		sblk->te2.base = PROP_VALUE_ACCESS(prop_value, TE2_OFF, i);
+		if (sblk->te2.base) {
+			sblk->te2.id = SDE_PINGPONG_TE2;
+			set_bit(SDE_PINGPONG_TE2, &pp->features);
+			set_bit(SDE_PINGPONG_SPLIT, &pp->features);
+		}
+
+		if (PROP_VALUE_ACCESS(prop_value, PP_SLAVE, i))
+			set_bit(SDE_PINGPONG_SLAVE, &pp->features);
+
+		sblk->dsc.base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);
+		if (sblk->dsc.base) {
+			sblk->dsc.id = SDE_PINGPONG_DSC;
+			set_bit(SDE_PINGPONG_DSC, &pp->features);
+		}
+	}
+
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
+{
+	int rc, len, prop_count[SDE_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[SDE_PROP_MAX];
+	const char *type;
+
+	if (!cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(SDE_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
+		&len);
+	if (rc)
+		goto end;
+
+	rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
+		prop_exists, prop_value);
+	if (rc)
+		goto end;
+
+	cfg->mdss_count = 1;
+	cfg->mdss[0].base = MDSS_BASE_OFFSET;
+	cfg->mdss[0].id = MDP_TOP;
+
+	cfg->mdp_count = 1;
+	cfg->mdp[0].id = MDP_TOP;
+	cfg->mdp[0].base = PROP_VALUE_ACCESS(prop_value, SDE_OFF, 0);
+	cfg->mdp[0].len = PROP_VALUE_ACCESS(prop_value, SDE_LEN, 0);
+	if (!prop_exists[SDE_LEN])
+		cfg->mdp[0].len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+	cfg->max_sspp_linewidth = PROP_VALUE_ACCESS(prop_value,
+			SSPP_LINEWIDTH, 0);
+	if (!prop_exists[SSPP_LINEWIDTH])
+		cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value,
+			MIXER_LINEWIDTH, 0);
+	if (!prop_exists[MIXER_LINEWIDTH])
+		cfg->max_mixer_width = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->max_mixer_blendstages = PROP_VALUE_ACCESS(prop_value,
+			MIXER_BLEND, 0);
+	if (!prop_exists[MIXER_BLEND])
+		cfg->max_mixer_blendstages = DEFAULT_SDE_MIXER_BLENDSTAGES;
+
+	cfg->max_wb_linewidth = PROP_VALUE_ACCESS(prop_value, WB_LINEWIDTH, 0);
+	if (!prop_exists[WB_LINEWIDTH])
+		cfg->max_wb_linewidth = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value,
+			BANK_BIT, 0);
+	if (!prop_exists[BANK_BIT])
+		cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;
+
+	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
+	if (!rc && !strcmp(type, "qseedv3"))
+		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;
+	else if (!rc && !strcmp(type, "qseedv2"))
+		cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
+
+	rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type);
+	if (!rc && !strcmp(type, "csc"))
+		cfg->csc_type = SDE_SSPP_CSC;
+	else if (!rc && !strcmp(type, "csc-10bit"))
+		cfg->csc_type = SDE_SSPP_CSC_10BIT;
+
+	cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);
+end:
+	kfree(prop_value);
+	return rc;
+}
+
+static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
+{
+	int rc, len, prop_count[PERF_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[PERF_PROP_MAX];
+
+	if (!cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(SDE_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
+			prop_count, &len);
+	if (rc)
+		goto freeprop;
+
+	rc = _read_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
+			prop_count, prop_exists, prop_value);
+	if (rc)
+		goto freeprop;
+
+	cfg->perf.max_bw_low =
+			PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_LOW, 0);
+	cfg->perf.max_bw_high =
+			PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_HIGH, 0);
+
+freeprop:
+	kfree(prop_value);
+end:
+	return rc;
+}
+
+static void sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
+{
+	switch (hw_rev) {
+	case SDE_HW_VER_170:
+	case SDE_HW_VER_171:
+	case SDE_HW_VER_172:
+		/* update msm8996 target here */
+		break;
+	case SDE_HW_VER_300:
+	case SDE_HW_VER_400:
+		/* update cobalt and skunk target here */
+		break;
+	}
+}
+
+void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
+{
+	int i;
+
+	if (!sde_cfg)
+		return;
+
+	for (i = 0; i < sde_cfg->sspp_count; i++)
+		kfree(sde_cfg->sspp[i].sblk);
+
+	for (i = 0; i < sde_cfg->mixer_count; i++)
+		kfree(sde_cfg->mixer[i].sblk);
+
+	for (i = 0; i < sde_cfg->wb_count; i++)
+		kfree(sde_cfg->wb[i].sblk);
+
+	for (i = 0; i < sde_cfg->dspp_count; i++)
+		kfree(sde_cfg->dspp[i].sblk);
+
+	for (i = 0; i < sde_cfg->pingpong_count; i++)
+		kfree(sde_cfg->pingpong[i].sblk);
+
+	for (i = 0; i < sde_cfg->vbif_count; i++) {
+		kfree(sde_cfg->vbif[i].dynamic_ot_rd_tbl.cfg);
+		kfree(sde_cfg->vbif[i].dynamic_ot_wr_tbl.cfg);
+	}
+	kfree(sde_cfg);
+}
+
+/*************************************************************
+ * hardware catalog init
+ *************************************************************/
+struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
+{
+	int rc;
+	struct sde_mdss_cfg *sde_cfg;
+	struct device_node *np = dev->dev->of_node;
+
+	sde_cfg = kzalloc(sizeof(*sde_cfg), GFP_KERNEL);
+	if (!sde_cfg)
+		return ERR_PTR(-ENOMEM);
+
+	sde_cfg->hwversion = hw_rev;
+
+	rc = sde_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_ctl_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_sspp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_dspp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_pp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	/* mixer parsing should be done after dspp and pp for mapping setup */
+	rc = sde_mixer_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_intf_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_wb_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	/* cdm parsing should be done after intf and wb for mapping setup */
+	rc = sde_cdm_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_vbif_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_perf_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	sde_hardware_caps(sde_cfg, hw_rev);
+
+	return sde_cfg;
+
+end:
+	sde_hw_catalog_deinit(sde_cfg);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
new file mode 100644
index 0000000000000000000000000000000000000000..a8f9169aaf3563936c47bf85fdc67e9fca61fe25
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -0,0 +1,716 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_CATALOG_H
+#define _SDE_HW_CATALOG_H
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/bitmap.h>
+#include <linux/err.h>
+#include <linux/msm-bus.h>
+#include <drm/drmP.h>
+
+/**
+ * Max hardware block count: For ex: max 12 SSPP pipes or
+ * 5 ctl paths. In all cases, it can have max 12 hardware blocks
+ * based on current design
+ */
+#define MAX_BLOCKS    12
+
+#define SDE_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28)    |\
+		((MINOR & 0xFFF) << 16)  |\
+		(STEP & 0xFFFF))
+
+#define SDE_HW_MAJOR(rev)		((rev) >> 28)
+#define SDE_HW_MINOR(rev)		(((rev) >> 16) & 0xFFF)
+#define SDE_HW_STEP(rev)		((rev) & 0xFFFF)
+#define SDE_HW_MAJOR_MINOR(rev)		((rev) >> 16)
+
+#define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2)   \
+	(SDE_HW_MAJOR_MINOR((rev1)) == SDE_HW_MAJOR_MINOR((rev2)))
+
+#define SDE_HW_VER_170	SDE_HW_VER(1, 7, 0) /* 8996 v1.0 */
+#define SDE_HW_VER_171	SDE_HW_VER(1, 7, 1) /* 8996 v2.0 */
+#define SDE_HW_VER_172	SDE_HW_VER(1, 7, 2) /* 8996 v3.0 */
+#define SDE_HW_VER_300	SDE_HW_VER(3, 0, 0) /* cobalt v1.0 */
+#define SDE_HW_VER_400	SDE_HW_VER(4, 0, 0) /* msmskunk v1.0 */
+
+#define IS_MSMSKUNK_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_400)
+
+#define MAX_IMG_WIDTH 0x3fff
+#define MAX_IMG_HEIGHT 0x3fff
+
+#define CRTC_DUAL_MIXERS	2
+
+#define SDE_COLOR_PROCESS_VER(MAJOR, MINOR) \
+		((((MAJOR) & 0xFFFF) << 16) | (((MINOR) & 0xFFFF)))
+#define SDE_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16)
+#define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)
+
+/**
+ * MDP TOP BLOCK features
+ * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
+ * @SDE_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
+ * @SDE_MDP_BWC,           MDSS HW supports Bandwidth compression.
+ * @SDE_MDP_UBWC_1_0,      This chipsets supports Universal Bandwidth
+ *                         compression initial revision
+ * @SDE_MDP_UBWC_1_5,      Universal Bandwidth compression version 1.5
+ * @SDE_MDP_CDP,           Client driven prefetch
+ * @SDE_MDP_MAX            Maximum value
+
+ */
+enum {
+	SDE_MDP_PANIC_PER_PIPE = 0x1,
+	SDE_MDP_10BIT_SUPPORT,
+	SDE_MDP_BWC,
+	SDE_MDP_UBWC_1_0,
+	SDE_MDP_UBWC_1_5,
+	SDE_MDP_CDP,
+	SDE_MDP_MAX
+};
+
+/**
+ * SSPP sub-blocks/features
+ * @SDE_SSPP_SRC             Src and fetch part of the pipes,
+ * @SDE_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
+ * @SDE_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
+ * @SDE_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
+ * @SDE_SSPP_CSC,            Support of Color space converion
+ * @SDE_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
+ * @SDE_SSPP_HSIC,           Global HSIC control
+ * @SDE_SSPP_MEMCOLOR        Memory Color Support
+ * @SDE_SSPP_IGC,            Inverse gamma correction
+ * @SDE_SSPP_PCC,            Color correction support
+ * @SDE_SSPP_CURSOR,         SSPP can be used as a cursor layer
+ * @SDE_SSPP_QOS,            SSPP support QoS control, danger/safe/creq
+ * @SDE_SSPP_MAX             maximum value
+ */
+enum {
+	SDE_SSPP_SRC = 0x1,
+	SDE_SSPP_SCALER_QSEED2,
+	SDE_SSPP_SCALER_QSEED3,
+	SDE_SSPP_SCALER_RGB,
+	SDE_SSPP_CSC,
+	SDE_SSPP_CSC_10BIT,
+	SDE_SSPP_HSIC,
+	SDE_SSPP_MEMCOLOR,
+	SDE_SSPP_IGC,
+	SDE_SSPP_PCC,
+	SDE_SSPP_CURSOR,
+	SDE_SSPP_QOS,
+	SDE_SSPP_MAX
+};
+
+/*
+ * MIXER sub-blocks/features
+ * @SDE_MIXER_LAYER           Layer mixer layer blend configuration,
+ * @SDE_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
+ * @SDE_MIXER_GC              Gamma correction block
+ * @SDE_MIXER_MAX             maximum value
+ */
+enum {
+	SDE_MIXER_LAYER = 0x1,
+	SDE_MIXER_SOURCESPLIT,
+	SDE_MIXER_GC,
+	SDE_MIXER_MAX
+};
+
+/**
+ * DSPP sub-blocks
+ * @SDE_DSPP_IGC             DSPP Inverse gamma correction block
+ * @SDE_DSPP_PCC             Panel color correction block
+ * @SDE_DSPP_GC              Gamma correction block
+ * @SDE_DSPP_HSIC            Global HSIC block
+ * @SDE_DSPP_MEMCOLOR        Memory Color block
+ * @SDE_DSPP_SIXZONE         Six zone block
+ * @SDE_DSPP_GAMUT           Gamut bloc
+ * @SDE_DSPP_DITHER          Dither block
+ * @SDE_DSPP_HIST            Histogram block
+ * @SDE_DSPP_VLUT            PA VLUT block
+ * @SDE_DSPP_AD              AD block
+ * @SDE_DSPP_MAX             maximum value
+ */
+enum {
+	SDE_DSPP_IGC = 0x1,
+	SDE_DSPP_PCC,
+	SDE_DSPP_GC,
+	SDE_DSPP_HSIC,
+	SDE_DSPP_MEMCOLOR,
+	SDE_DSPP_SIXZONE,
+	SDE_DSPP_GAMUT,
+	SDE_DSPP_DITHER,
+	SDE_DSPP_HIST,
+	SDE_DSPP_VLUT,
+	SDE_DSPP_AD,
+	SDE_DSPP_MAX
+};
+
+/**
+ * PINGPONG sub-blocks
+ * @SDE_PINGPONG_TE         Tear check block
+ * @SDE_PINGPONG_TE2        Additional tear check block for split pipes
+ * @SDE_PINGPONG_SPLIT      PP block supports split fifo
+ * @SDE_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
+ * @SDE_PINGPONG_DSC,       Display stream compression blocks
+ * @SDE_PINGPONG_MAX
+ */
+enum {
+	SDE_PINGPONG_TE = 0x1,
+	SDE_PINGPONG_TE2,
+	SDE_PINGPONG_SPLIT,
+	SDE_PINGPONG_SLAVE,
+	SDE_PINGPONG_DSC,
+	SDE_PINGPONG_MAX
+};
+
+/**
+ * CTL sub-blocks
+ * @SDE_CTL_SPLIT_DISPLAY       CTL supports video mode split display
+ * @SDE_CTL_PINGPONG_SPLIT      CTL supports pingpong split
+ * @SDE_CTL_MAX
+ */
+enum {
+	SDE_CTL_SPLIT_DISPLAY = 0x1,
+	SDE_CTL_PINGPONG_SPLIT,
+	SDE_CTL_MAX
+};
+
+/**
+ * WB sub-blocks and features
+ * @SDE_WB_LINE_MODE        Writeback module supports line/linear mode
+ * @SDE_WB_BLOCK_MODE       Writeback module supports block mode read
+ * @SDE_WB_ROTATE           rotation support,this is available if writeback
+ *                          supports block mode read
+ * @SDE_WB_CSC              Writeback color conversion block support
+ * @SDE_WB_CHROMA_DOWN,     Writeback chroma down block,
+ * @SDE_WB_DOWNSCALE,       Writeback integer downscaler,
+ * @SDE_WB_DITHER,          Dither block
+ * @SDE_WB_TRAFFIC_SHAPER,  Writeback traffic shaper bloc
+ * @SDE_WB_UBWC_1_0,        Writeback Universal bandwidth compression 1.0
+ *                          support
+ * @SDE_WB_UBWC_1_5         UBWC 1.5 support
+ * @SDE_WB_YUV_CONFIG       Writeback supports output of YUV colorspace
+ * @SDE_WB_PIPE_ALPHA       Writeback supports pipe alpha
+ * @SDE_WB_XY_ROI_OFFSET    Writeback supports x/y-offset of out ROI in
+ *                          the destination image
+ * @SDE_WB_MAX              maximum value
+ */
+enum {
+	SDE_WB_LINE_MODE = 0x1,
+	SDE_WB_BLOCK_MODE,
+	SDE_WB_ROTATE = SDE_WB_BLOCK_MODE,
+	SDE_WB_CSC,
+	SDE_WB_CHROMA_DOWN,
+	SDE_WB_DOWNSCALE,
+	SDE_WB_DITHER,
+	SDE_WB_TRAFFIC_SHAPER,
+	SDE_WB_UBWC_1_0,
+	SDE_WB_YUV_CONFIG,
+	SDE_WB_PIPE_ALPHA,
+	SDE_WB_XY_ROI_OFFSET,
+	SDE_WB_MAX
+};
+
+/**
+ * VBIF sub-blocks and features
+ * @SDE_VBIF_QOS_OTLIM        VBIF supports OT Limit
+ * @SDE_VBIF_MAX              maximum value
+ */
+enum {
+	SDE_VBIF_QOS_OTLIM = 0x1,
+	SDE_VBIF_MAX
+};
+
+/**
+ * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE
+ * @id:                enum identifying this block
+ * @base:              register base offset to mdss
+ * @len:               length of hardware block
+ * @features           bit mask identifying sub-blocks/features
+ */
+#define SDE_HW_BLK_INFO \
+	u32 id; \
+	u32 base; \
+	u32 len; \
+	unsigned long features; \
+
+/**
+ * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE
+ * @id:                enum identifying this sub-block
+ * @base:              offset of this sub-block relative to the block
+ *                     offset
+ * @len                register block length of this sub-block
+ */
+#define SDE_HW_SUBBLK_INFO \
+	u32 id; \
+	u32 base; \
+	u32 len
+
+/**
+ * struct sde_src_blk: SSPP part of the source pipes
+ * @info:   HW register and features supported by this sub-blk
+ */
+struct sde_src_blk {
+	SDE_HW_SUBBLK_INFO;
+};
+
+/**
+ * struct sde_scaler_blk: Scaler information
+ * @info:   HW register and features supported by this sub-blk
+ * @version: qseed block revision
+ */
+struct sde_scaler_blk {
+	SDE_HW_SUBBLK_INFO;
+	u32 version;
+};
+
+struct sde_csc_blk {
+	SDE_HW_SUBBLK_INFO;
+};
+
+/**
+ * struct sde_pp_blk : Pixel processing sub-blk information
+ * @info:   HW register and features supported by this sub-blk
+ * @version: HW Algorithm version
+ */
+struct sde_pp_blk {
+	SDE_HW_SUBBLK_INFO;
+	u32 version;
+};
+
+/**
+ * struct sde_format_extended - define sde specific pixel format+modifier
+ * @fourcc_format: Base FOURCC pixel format code
+ * @modifier: 64-bit drm format modifier, same modifier must be applied to all
+ *            framebuffer planes
+ */
+struct sde_format_extended {
+	uint32_t fourcc_format;
+	uint64_t modifier;
+};
+
+/**
+ * struct sde_sspp_sub_blks : SSPP sub-blocks
+ * @maxdwnscale: max downscale ratio supported(without DECIMATION)
+ * @maxupscale:  maxupscale ratio supported
+ * @maxwidth:    max pixelwidth supported by this pipe
+ * @danger_lut_linear: LUT to generate danger signals for linear format
+ * @safe_lut_linear: LUT to generate safe signals for linear format
+ * @danger_lut_tile: LUT to generate danger signals for tile format
+ * @safe_lut_tile: LUT to generate safe signals for tile format
+ * @danger_lut_nrt: LUT to generate danger signals for non-realtime use case
+ * @safe_lut_nrt: LUT to generate safe signals for non-realtime use case
+ * @creq_lut_nrt: LUT to generate creq signals for non-realtime use case
+ * @creq_vblank: creq priority during vertical blanking
+ * @danger_vblank: danger priority during vertical blanking
+ * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
+ * @src_blk:
+ * @scaler_blk:
+ * @csc_blk:
+ * @hsic:
+ * @memcolor:
+ * @pcc_blk:
+ * @igc_blk:
+ * @format_list: Pointer to list of supported formats
+ */
+struct sde_sspp_sub_blks {
+	u32 maxlinewidth;
+	u32 danger_lut_linear;
+	u32 safe_lut_linear;
+	u32 danger_lut_tile;
+	u32 safe_lut_tile;
+	u32 danger_lut_nrt;
+	u32 safe_lut_nrt;
+	u32 creq_lut_nrt;
+	u32 creq_vblank;
+	u32 danger_vblank;
+	u32 pixel_ram_size;
+	u32 maxdwnscale;
+	u32 maxupscale;
+	u32 maxhdeciexp; /* max decimation is 2^value */
+	u32 maxvdeciexp; /* max decimation is 2^value */
+	struct sde_src_blk src_blk;
+	struct sde_scaler_blk scaler_blk;
+	struct sde_pp_blk csc_blk;
+	struct sde_pp_blk hsic_blk;
+	struct sde_pp_blk memcolor_blk;
+	struct sde_pp_blk pcc_blk;
+	struct sde_pp_blk igc_blk;
+
+	const struct sde_format_extended *format_list;
+};
+
+/**
+ * struct sde_lm_sub_blks:      information of mixer block
+ * @maxwidth:               Max pixel width supported by this mixer
+ * @maxblendstages:         Max number of blend-stages supported
+ * @blendstage_base:        Blend-stage register base offset
+ * @gc: gamma correction block
+ */
+struct sde_lm_sub_blks {
+	u32 maxwidth;
+	u32 maxblendstages;
+	u32 blendstage_base[MAX_BLOCKS];
+	struct sde_pp_blk gc;
+};
+
+struct sde_dspp_sub_blks {
+	struct sde_pp_blk igc;
+	struct sde_pp_blk pcc;
+	struct sde_pp_blk gc;
+	struct sde_pp_blk hsic;
+	struct sde_pp_blk memcolor;
+	struct sde_pp_blk sixzone;
+	struct sde_pp_blk gamut;
+	struct sde_pp_blk dither;
+	struct sde_pp_blk hist;
+	struct sde_pp_blk ad;
+	struct sde_pp_blk vlut;
+};
+
+struct sde_pingpong_sub_blks {
+	struct sde_pp_blk te;
+	struct sde_pp_blk te2;
+	struct sde_pp_blk dsc;
+};
+
+struct sde_wb_sub_blocks {
+	u32 maxlinewidth;
+};
+
+struct sde_mdss_base_cfg {
+	SDE_HW_BLK_INFO;
+};
+
+/**
+ * sde_clk_ctrl_type - Defines top level clock control signals
+ */
+enum sde_clk_ctrl_type {
+	SDE_CLK_CTRL_NONE,
+	SDE_CLK_CTRL_VIG0,
+	SDE_CLK_CTRL_VIG1,
+	SDE_CLK_CTRL_VIG2,
+	SDE_CLK_CTRL_VIG3,
+	SDE_CLK_CTRL_VIG4,
+	SDE_CLK_CTRL_RGB0,
+	SDE_CLK_CTRL_RGB1,
+	SDE_CLK_CTRL_RGB2,
+	SDE_CLK_CTRL_RGB3,
+	SDE_CLK_CTRL_DMA0,
+	SDE_CLK_CTRL_DMA1,
+	SDE_CLK_CTRL_CURSOR0,
+	SDE_CLK_CTRL_CURSOR1,
+	SDE_CLK_CTRL_WB0,
+	SDE_CLK_CTRL_WB1,
+	SDE_CLK_CTRL_WB2,
+	SDE_CLK_CTRL_MAX,
+};
+
+/* struct sde_clk_ctrl_reg : Clock control register
+ * @reg_off:           register offset
+ * @bit_off:           bit offset
+ */
+struct sde_clk_ctrl_reg {
+	u32 reg_off;
+	u32 bit_off;
+};
+
+/* struct sde_mdp_cfg : MDP TOP-BLK instance info
+ * @id:                index identifying this block
+ * @base:              register base offset to mdss
+ * @features           bit mask identifying sub-blocks/features
+ * @highest_bank_bit:  UBWC parameter
+ * @clk_ctrls          clock control register definition
+ */
+struct sde_mdp_cfg {
+	SDE_HW_BLK_INFO;
+	u32 highest_bank_bit;
+	struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX];
+};
+
+/* struct sde_mdp_cfg : MDP TOP-BLK instance info
+ * @id:                index identifying this block
+ * @base:              register base offset to mdss
+ * @features           bit mask identifying sub-blocks/features
+ */
+struct sde_ctl_cfg {
+	SDE_HW_BLK_INFO;
+};
+
+/**
+ * struct sde_sspp_cfg - information of source pipes
+ * @id:                index identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @sblk:              SSPP sub-blocks information
+ * @xin_id:            bus client identifier
+ * @clk_ctrl           clock control identifier
+ */
+struct sde_sspp_cfg {
+	SDE_HW_BLK_INFO;
+	const struct sde_sspp_sub_blks *sblk;
+	u32 xin_id;
+	enum sde_clk_ctrl_type clk_ctrl;
+};
+
+/**
+ * struct sde_lm_cfg - information of layer mixer blocks
+ * @id:                index identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @sblk:              LM Sub-blocks information
+ * @dspp:              ID of connected DSPP, DSPP_MAX if unsupported
+ * @pingpong:          ID of connected PingPong, PINGPONG_MAX if unsupported
+ * @lm_pair_mask:      Bitmask of LMs that can be controlled by same CTL
+ */
+struct sde_lm_cfg {
+	SDE_HW_BLK_INFO;
+	const struct sde_lm_sub_blks *sblk;
+	u32 dspp;
+	u32 pingpong;
+	unsigned long lm_pair_mask;
+};
+
+/**
+ * struct sde_dspp_cfg - information of DSPP blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ *                     supported by this block
+ * @sblk               sub-blocks information
+ */
+struct sde_dspp_cfg  {
+	SDE_HW_BLK_INFO;
+	const struct sde_dspp_sub_blks *sblk;
+};
+
+/**
+ * struct sde_pingpong_cfg - information of PING-PONG blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @sblk               sub-blocks information
+ */
+struct sde_pingpong_cfg  {
+	SDE_HW_BLK_INFO;
+	const struct sde_pingpong_sub_blks *sblk;
+};
+
+/**
+ * struct sde_cdm_cfg - information of chroma down blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @intf_connect       Bitmask of INTF IDs this CDM can connect to
+ * @wb_connect:        Bitmask of Writeback IDs this CDM can connect to
+ */
+struct sde_cdm_cfg   {
+	SDE_HW_BLK_INFO;
+	unsigned long intf_connect;
+	unsigned long wb_connect;
+};
+
+/**
+ * struct sde_intf_cfg - information of timing engine blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @type:              Interface type(DSI, DP, HDMI)
+ * @controller_id:     Controller Instance ID in case of multiple of intf type
+ * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
+ */
+struct sde_intf_cfg  {
+	SDE_HW_BLK_INFO;
+	u32 type;   /* interface type*/
+	u32 controller_id;
+	u32 prog_fetch_lines_worst_case;
+};
+
+/**
+ * struct sde_wb_cfg - information of writeback blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @sblk               sub-block information
+ * @format_list: Pointer to list of supported formats
+ * @vbif_idx           vbif identifier
+ * @xin_id             client interface identifier
+ * @clk_ctrl           clock control identifier
+ */
+struct sde_wb_cfg {
+	SDE_HW_BLK_INFO;
+	const struct sde_wb_sub_blocks *sblk;
+	const struct sde_format_extended *format_list;
+	u32 vbif_idx;
+	u32 xin_id;
+	enum sde_clk_ctrl_type clk_ctrl;
+};
+
+/**
+ * struct sde_vbif_dynamic_ot_cfg - dynamic OT setting
+ * @pps                pixel per seconds
+ * @ot_limit           OT limit to use up to specified pixel per second
+ */
+struct sde_vbif_dynamic_ot_cfg {
+	u64 pps;
+	u32 ot_limit;
+};
+
+/**
+ * struct sde_vbif_dynamic_ot_tbl - dynamic OT setting table
+ * @count              length of cfg
+ * @cfg                pointer to array of configuration settings with
+ *                     ascending requirements
+ */
+struct sde_vbif_dynamic_ot_tbl {
+	u32 count;
+	struct sde_vbif_dynamic_ot_cfg *cfg;
+};
+
+/**
+ * struct sde_vbif_cfg - information of VBIF blocks
+ * @id                 enum identifying this block
+ * @base               register offset of this block
+ * @features           bit mask identifying sub-blocks/features
+ * @ot_rd_limit        default OT read limit
+ * @ot_wr_limit        default OT write limit
+ * @xin_halt_timeout   maximum time (in usec) for xin to halt
+ * @dynamic_ot_rd_tbl  dynamic OT read configuration table
+ * @dynamic_ot_wr_tbl  dynamic OT write configuration table
+ */
+struct sde_vbif_cfg {
+	SDE_HW_BLK_INFO;
+	u32 default_ot_rd_limit;
+	u32 default_ot_wr_limit;
+	u32 xin_halt_timeout;
+	struct sde_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
+	struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
+};
+
+/**
+ * struct sde_perf_cfg - performance control settings
+ * @max_bw_low         low threshold of maximum bandwidth (kbps)
+ * @max_bw_high        high threshold of maximum bandwidth (kbps)
+ */
+struct sde_perf_cfg {
+	u32 max_bw_low;
+	u32 max_bw_high;
+};
+
+/**
+ * struct sde_mdss_cfg - information of MDSS HW
+ * This is the main catalog data structure representing
+ * this HW version. Contains number of instances,
+ * register offsets, capabilities of the all MDSS HW sub-blocks.
+ *
+ * @max_sspp_linewidth max source pipe line width support.
+ * @max_mixer_width    max layer mixer line width support.
+ * @max_mixer_blendstages max layer mixer blend stages or
+ *                       supported z order
+ * @max_wb_linewidth   max writeback line width support.
+ * @highest_bank_bit   highest memory bit setting for tile buffers.
+ * @qseed_type         qseed2 or qseed3 support.
+ * @csc_type           csc or csc_10bit support.
+ * @has_src_split      source split feature status
+ * @has_cdp            Client driver prefetch feature status
+ */
+struct sde_mdss_cfg {
+	u32 hwversion;
+
+	u32 max_sspp_linewidth;
+	u32 max_mixer_width;
+	u32 max_mixer_blendstages;
+	u32 max_wb_linewidth;
+	u32 highest_bank_bit;
+	u32 qseed_type;
+	u32 csc_type;
+	bool has_src_split;
+	bool has_cdp;
+
+	u32 mdss_count;
+	struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
+
+	u32 mdp_count;
+	struct sde_mdp_cfg mdp[MAX_BLOCKS];
+
+	u32 ctl_count;
+	struct sde_ctl_cfg ctl[MAX_BLOCKS];
+
+	u32 sspp_count;
+	struct sde_sspp_cfg sspp[MAX_BLOCKS];
+
+	u32 mixer_count;
+	struct sde_lm_cfg mixer[MAX_BLOCKS];
+
+	u32 dspp_count;
+	struct sde_dspp_cfg dspp[MAX_BLOCKS];
+
+	u32 pingpong_count;
+	struct sde_pingpong_cfg pingpong[MAX_BLOCKS];
+
+	u32 cdm_count;
+	struct sde_cdm_cfg cdm[MAX_BLOCKS];
+
+	u32 intf_count;
+	struct sde_intf_cfg intf[MAX_BLOCKS];
+
+	u32 wb_count;
+	struct sde_wb_cfg wb[MAX_BLOCKS];
+
+	u32 vbif_count;
+	struct sde_vbif_cfg vbif[MAX_BLOCKS];
+	/* Add additional block data structures here */
+
+	struct sde_perf_cfg perf;
+};
+
+struct sde_mdss_hw_cfg_handler {
+	u32 major;
+	u32 minor;
+	struct sde_mdss_cfg* (*cfg_init)(u32);
+};
+
+/*
+ * Access Macros
+ */
+#define BLK_MDP(s) ((s)->mdp)
+#define BLK_CTL(s) ((s)->ctl)
+#define BLK_VIG(s) ((s)->vig)
+#define BLK_RGB(s) ((s)->rgb)
+#define BLK_DMA(s) ((s)->dma)
+#define BLK_CURSOR(s) ((s)->cursor)
+#define BLK_MIXER(s) ((s)->mixer)
+#define BLK_DSPP(s) ((s)->dspp)
+#define BLK_PINGPONG(s) ((s)->pingpong)
+#define BLK_CDM(s) ((s)->cdm)
+#define BLK_INTF(s) ((s)->intf)
+#define BLK_WB(s) ((s)->wb)
+#define BLK_AD(s) ((s)->ad)
+
+/**
+ * sde_hw_catalog_init - sde hardware catalog init API parses dtsi property
+ * and stores all parsed offset, hardware capabilities in config structure.
+ * @dev:          drm device node.
+ * @hw_rev:       caller needs provide the hardware revision before parsing.
+ *
+ * Return: parsed sde config structure
+ */
+struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev);
+
+/**
+ * sde_hw_catalog_deinit - sde hardware catalog cleanup
+ * @sde_cfg:      pointer returned from init function
+ */
+void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg);
+
+#endif /* _SDE_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h
new file mode 100644
index 0000000000000000000000000000000000000000..2966944226531caa0c18f7e7d7cf26aba87930cb
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h
@@ -0,0 +1,134 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_mdss.h"
+
+static const struct sde_format_extended plane_formats[] = {
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_XBGR8888, 0},
+	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{0, 0},
+};
+
+static const struct sde_format_extended plane_formats_yuv[] = {
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_XBGR8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_NV21, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_NV61, 0},
+	{DRM_FORMAT_VYUY, 0},
+	{DRM_FORMAT_UYVY, 0},
+	{DRM_FORMAT_YUYV, 0},
+	{DRM_FORMAT_YVYU, 0},
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_YVU420, 0},
+	{0, 0},
+};
+
+static const struct sde_format_extended wb2_formats[] = {
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_XBGR8888, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_YUYV, 0},
+
+	{0, 0},
+};
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_cdm.c b/drivers/gpu/drm/msm/sde/sde_hw_cdm.c
new file mode 100644
index 0000000000000000000000000000000000000000..c7cbb93bece4990382d8609ce620ec6f695a0f86
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_cdm.c
@@ -0,0 +1,342 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_mdss.h"
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_cdm.h"
+
+#define CDM_CSC_10_OPMODE                  0x000
+#define CDM_CSC_10_BASE                    0x004
+
+#define CDM_CDWN2_OP_MODE                  0x100
+#define CDM_CDWN2_CLAMP_OUT                0x104
+#define CDM_CDWN2_PARAMS_3D_0              0x108
+#define CDM_CDWN2_PARAMS_3D_1              0x10C
+#define CDM_CDWN2_COEFF_COSITE_H_0         0x110
+#define CDM_CDWN2_COEFF_COSITE_H_1         0x114
+#define CDM_CDWN2_COEFF_COSITE_H_2         0x118
+#define CDM_CDWN2_COEFF_OFFSITE_H_0        0x11C
+#define CDM_CDWN2_COEFF_OFFSITE_H_1        0x120
+#define CDM_CDWN2_COEFF_OFFSITE_H_2        0x124
+#define CDM_CDWN2_COEFF_COSITE_V           0x128
+#define CDM_CDWN2_COEFF_OFFSITE_V          0x12C
+#define CDM_CDWN2_OUT_SIZE                 0x130
+
+#define CDM_HDMI_PACK_OP_MODE              0x200
+#define CDM_CSC_10_MATRIX_COEFF_0          0x004
+
+/**
+ * Horizontal coefficients for cosite chroma downscale
+ * s13 representation of coefficients
+ */
+static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
+
+/**
+ * Horizontal coefficients for offsite chroma downscale
+ */
+static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
+
+/**
+ * Vertical coefficients for cosite chroma downscale
+ */
+static u32 cosite_v_coeff[] = {0x00080004};
+/**
+ * Vertical coefficients for offsite chroma downscale
+ */
+static u32 offsite_v_coeff[] = {0x00060002};
+
+/* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */
+static struct sde_csc_cfg rgb2yuv_cfg = {
+	{
+		0x0083, 0x0102, 0x0032,
+		0x1fb5, 0x1f6c, 0x00e1,
+		0x00e1, 0x1f45, 0x1fdc
+	},
+	{ 0x00, 0x00, 0x00 },
+	{ 0x0040, 0x0200, 0x0200 },
+	{ 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
+	{ 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
+};
+
+static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->cdm_count; i++) {
+		if (cdm == m->cdm[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->cdm[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_CDM;
+			return &m->cdm[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static void sde_hw_cdm_setup_csc_10bit(struct sde_hw_cdm *ctx,
+		struct sde_csc_cfg *data)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 csc_reg_off = CDM_CSC_10_MATRIX_COEFF_0;
+	u32 val;
+
+	/* matrix coeff */
+	val = data->csc_mv[0] | (data->csc_mv[1] << 16);
+	SDE_REG_WRITE(c, csc_reg_off,  val);
+	val = data->csc_mv[2] | (data->csc_mv[3] << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0x4, val);
+	val = data->csc_mv[4] | (data->csc_mv[5] << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0x8, val);
+	val = data->csc_mv[6] | (data->csc_mv[7] << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0xc, val);
+	val = data->csc_mv[8];
+	SDE_REG_WRITE(c, csc_reg_off + 0x10, val);
+
+	/* Pre clamp */
+	val = (data->csc_pre_lv[0] << 16) | data->csc_pre_lv[1];
+	SDE_REG_WRITE(c, csc_reg_off + 0x14,  val);
+	val = (data->csc_pre_lv[2] << 16) | data->csc_pre_lv[3];
+	SDE_REG_WRITE(c, csc_reg_off  + 0x18, val);
+	val = (data->csc_pre_lv[4] << 16) | data->csc_pre_lv[5];
+	SDE_REG_WRITE(c, csc_reg_off  + 0x1c, val);
+
+	/* Post clamp */
+	val = (data->csc_post_lv[0] << 16) | data->csc_post_lv[1];
+	SDE_REG_WRITE(c, csc_reg_off + 0x20,  val);
+	val = (data->csc_post_lv[2] << 16) | data->csc_post_lv[3];
+	SDE_REG_WRITE(c, csc_reg_off  + 0x24, val);
+	val = (data->csc_post_lv[4] << 16) | data->csc_post_lv[5];
+	SDE_REG_WRITE(c, csc_reg_off  + 0x28, val);
+
+	/* Pre-Bias */
+	SDE_REG_WRITE(c, csc_reg_off + 0x2c,  data->csc_pre_bv[0]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
+
+	/* Post-Bias */
+	SDE_REG_WRITE(c, csc_reg_off + 0x38,  data->csc_post_bv[0]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
+}
+
+static int sde_hw_cdm_setup_cdwn(struct sde_hw_cdm *ctx,
+		struct sde_hw_cdm_cfg *cfg)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 opmode = 0;
+	u32 out_size = 0;
+
+	if (cfg->output_bit_depth == CDM_CDWN_OUTPUT_10BIT)
+		opmode &= ~BIT(7);
+	else
+		opmode |= BIT(7);
+
+	/* ENABLE DWNS_H bit */
+	opmode |= BIT(1);
+
+	switch (cfg->h_cdwn_type) {
+	case CDM_CDWN_DISABLE:
+		/* CLEAR METHOD_H field */
+		opmode &= ~(0x18);
+		/* CLEAR DWNS_H bit */
+		opmode &= ~BIT(1);
+		break;
+	case CDM_CDWN_PIXEL_DROP:
+		/* Clear METHOD_H field (pixel drop is 0) */
+		opmode &= ~(0x18);
+		break;
+	case CDM_CDWN_AVG:
+		/* Clear METHOD_H field (Average is 0x1) */
+		opmode &= ~(0x18);
+		opmode |= (0x1 << 0x3);
+		break;
+	case CDM_CDWN_COSITE:
+		/* Clear METHOD_H field (Average is 0x2) */
+		opmode &= ~(0x18);
+		opmode |= (0x2 << 0x3);
+		/* Co-site horizontal coefficients */
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
+				cosite_h_coeff[0]);
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
+				cosite_h_coeff[1]);
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
+				cosite_h_coeff[2]);
+		break;
+	case CDM_CDWN_OFFSITE:
+		/* Clear METHOD_H field (Average is 0x3) */
+		opmode &= ~(0x18);
+		opmode |= (0x3 << 0x3);
+
+		/* Off-site horizontal coefficients */
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
+				offsite_h_coeff[0]);
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
+				offsite_h_coeff[1]);
+		SDE_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
+				offsite_h_coeff[2]);
+		break;
+	default:
+		pr_err("%s invalid horz down sampling type\n", __func__);
+		return -EINVAL;
+	}
+
+	/* ENABLE DWNS_V bit */
+	opmode |= BIT(2);
+
+	switch (cfg->v_cdwn_type) {
+	case CDM_CDWN_DISABLE:
+		/* CLEAR METHOD_V field */
+		opmode &= ~(0x60);
+		/* CLEAR DWNS_V bit */
+		opmode &= ~BIT(2);
+		break;
+	case CDM_CDWN_PIXEL_DROP:
+		/* Clear METHOD_V field (pixel drop is 0) */
+		opmode &= ~(0x60);
+		break;
+	case CDM_CDWN_AVG:
+		/* Clear METHOD_V field (Average is 0x1) */
+		opmode &= ~(0x60);
+		opmode |= (0x1 << 0x5);
+		break;
+	case CDM_CDWN_COSITE:
+		/* Clear METHOD_V field (Average is 0x2) */
+		opmode &= ~(0x60);
+		opmode |= (0x2 << 0x5);
+		/* Co-site vertical coefficients */
+		SDE_REG_WRITE(c,
+				CDM_CDWN2_COEFF_COSITE_V,
+				cosite_v_coeff[0]);
+		break;
+	case CDM_CDWN_OFFSITE:
+		/* Clear METHOD_V field (Average is 0x3) */
+		opmode &= ~(0x60);
+		opmode |= (0x3 << 0x5);
+
+		/* Off-site vertical coefficients */
+		SDE_REG_WRITE(c,
+				CDM_CDWN2_COEFF_OFFSITE_V,
+				offsite_v_coeff[0]);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (cfg->v_cdwn_type || cfg->h_cdwn_type)
+		opmode |= BIT(0); /* EN CDWN module */
+	else
+		opmode &= ~BIT(0);
+
+	out_size = (cfg->output_width & 0xFFFF) |
+		((cfg->output_height & 0xFFFF) << 16);
+	SDE_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
+	SDE_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
+	SDE_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT,
+			((0x3FF << 16) | 0x0));
+
+	return 0;
+}
+
+int sde_hw_cdm_enable(struct sde_hw_cdm *ctx,
+		struct sde_hw_cdm_cfg *cdm)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	const struct sde_format *fmt = cdm->output_fmt;
+	struct cdm_output_cfg cdm_cfg = { 0 };
+	u32 opmode = 0;
+	u32 csc = 0;
+
+	if (!SDE_FORMAT_IS_YUV(fmt))
+		return -EINVAL;
+
+	if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
+		if (fmt->chroma_sample != SDE_CHROMA_H1V2)
+			return -EINVAL; /*unsupported format */
+		opmode = BIT(0);
+		opmode |= (fmt->chroma_sample << 1);
+		cdm_cfg.intf_en = true;
+	} else {
+		opmode = 0;
+		cdm_cfg.wb_en = true;
+	}
+
+	csc |= BIT(2);
+	csc &= ~BIT(1);
+	csc |= BIT(0);
+
+	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
+		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
+
+	SDE_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
+	SDE_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
+	return 0;
+}
+
+void sde_hw_cdm_disable(struct sde_hw_cdm *ctx)
+{
+	struct cdm_output_cfg cdm_cfg = { 0 };
+
+	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
+		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
+}
+
+static void _setup_cdm_ops(struct sde_hw_cdm_ops *ops,
+	unsigned long features)
+{
+	ops->setup_csc_data = sde_hw_cdm_setup_csc_10bit;
+	ops->setup_cdwn = sde_hw_cdm_setup_cdwn;
+	ops->enable = sde_hw_cdm_enable;
+	ops->disable = sde_hw_cdm_disable;
+}
+
+struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m,
+		struct sde_hw_mdp *hw_mdp)
+{
+	struct sde_hw_cdm *c;
+	struct sde_cdm_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _cdm_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	c->idx = idx;
+	c->cdm_hw_cap = cfg;
+	_setup_cdm_ops(&c->ops, c->cdm_hw_cap->features);
+	c->hw_mdp = hw_mdp;
+
+	/*
+	 * Perform any default initialization for the chroma down module
+	 * @setup default csc coefficients
+	 */
+	sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
+
+	return c;
+}
+
+void sde_hw_cdm_destroy(struct sde_hw_cdm *cdm)
+{
+	kfree(cdm);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_cdm.h b/drivers/gpu/drm/msm/sde/sde_hw_cdm.h
new file mode 100644
index 0000000000000000000000000000000000000000..264b8a418573e31917c5d1aedb69ca2e2667e57c
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_cdm.h
@@ -0,0 +1,127 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_CDM_H
+#define _SDE_HW_CDM_H
+
+#include "sde_hw_mdss.h"
+#include "sde_hw_top.h"
+
+struct sde_hw_cdm;
+
+struct sde_hw_cdm_cfg {
+	u32 output_width;
+	u32 output_height;
+	u32 output_bit_depth;
+	u32 h_cdwn_type;
+	u32 v_cdwn_type;
+	const struct sde_format *output_fmt;
+	u32 output_type;
+	int flags;
+};
+
+enum sde_hw_cdwn_type {
+	CDM_CDWN_DISABLE,
+	CDM_CDWN_PIXEL_DROP,
+	CDM_CDWN_AVG,
+	CDM_CDWN_COSITE,
+	CDM_CDWN_OFFSITE,
+};
+
+enum sde_hw_cdwn_output_type {
+	CDM_CDWN_OUTPUT_HDMI,
+	CDM_CDWN_OUTPUT_WB,
+};
+
+enum sde_hw_cdwn_output_bit_depth {
+	CDM_CDWN_OUTPUT_8BIT,
+	CDM_CDWN_OUTPUT_10BIT,
+};
+
+/**
+ * struct sde_hw_cdm_ops : Interface to the chroma down Hw driver functions
+ *                         Assumption is these functions will be called after
+ *                         clocks are enabled
+ *  @setup_csc:            Programs the csc matrix
+ *  @setup_cdwn:           Sets up the chroma down sub module
+ *  @enable:               Enables the output to interface and programs the
+ *                         output packer
+ *  @disable:              Puts the cdm in bypass mode
+ */
+struct sde_hw_cdm_ops {
+	/**
+	 * Programs the CSC matrix for conversion from RGB space to YUV space,
+	 * it is optional to call this function as this matrix is automatically
+	 * set during initialization, user should call this if it wants
+	 * to program a different matrix than default matrix.
+	 * @cdm:          Pointer to the chroma down context structure
+	 * @data          Pointer to CSC configuration data
+	 */
+	void (*setup_csc_data)(struct sde_hw_cdm *cdm,
+			struct sde_csc_cfg *data);
+
+	/**
+	 * Programs the Chroma downsample part.
+	 * @cdm         Pointer to chroma down context
+	 */
+	int (*setup_cdwn)(struct sde_hw_cdm *cdm,
+	struct sde_hw_cdm_cfg *cfg);
+
+	/**
+	 * Enable the CDM module
+	 * @cdm         Pointer to chroma down context
+	 */
+	int (*enable)(struct sde_hw_cdm *cdm,
+	struct sde_hw_cdm_cfg *cfg);
+
+	/**
+	 * Disable the CDM module
+	 * @cdm         Pointer to chroma down context
+	 */
+	void (*disable)(struct sde_hw_cdm *cdm);
+};
+
+struct sde_hw_cdm {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* chroma down */
+	const struct sde_cdm_cfg   *cdm_hw_cap;
+	enum  sde_cdm  idx;
+
+	/* mdp top hw driver */
+	struct sde_hw_mdp *hw_mdp;
+
+	/* ops */
+	struct sde_hw_cdm_ops ops;
+};
+
+/**
+ * sde_hw_cdm_init - initializes the cdm hw driver object.
+ * should be called once before accessing every cdm.
+ * @idx:  cdm index for which driver object is required
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ * @hw_mdp:  pointer to mdp top hw driver object
+ */
+struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m,
+		struct sde_hw_mdp *hw_mdp);
+
+/**
+ * sde_hw_cdm_destroy - destroys CDM driver context
+ * @cdm:   pointer to CDM driver context
+ */
+void sde_hw_cdm_destroy(struct sde_hw_cdm *cdm);
+
+#endif /*_SDE_HW_CDM_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing.h b/drivers/gpu/drm/msm/sde/sde_hw_color_processing.h
new file mode 100644
index 0000000000000000000000000000000000000000..a30e1a52b04636fbc78d50b11c0d202322863578
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing.h
@@ -0,0 +1,18 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_COLOR_PROCESSING_H
+#define _SDE_HW_COLOR_PROCESSING_H
+
+#include "sde_hw_color_processing_v1_7.h"
+
+#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
new file mode 100644
index 0000000000000000000000000000000000000000..f1f66f37ba6a572c897f165d01a95f03e4202598
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
@@ -0,0 +1,453 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <drm/msm_drm_pp.h>
+#include "sde_hw_color_processing_v1_7.h"
+
+#define PA_HUE_VIG_OFF		0x110
+#define PA_SAT_VIG_OFF		0x114
+#define PA_VAL_VIG_OFF		0x118
+#define PA_CONT_VIG_OFF		0x11C
+
+#define PA_HUE_DSPP_OFF		0x238
+#define PA_SAT_DSPP_OFF		0x23C
+#define PA_VAL_DSPP_OFF		0x240
+#define PA_CONT_DSPP_OFF	0x244
+
+#define PA_LUTV_DSPP_OFF	0x1400
+#define PA_LUT_SWAP_OFF		0x234
+
+#define PA_HUE_MASK		0xFFF
+#define PA_SAT_MASK		0xFFFF
+#define PA_VAL_MASK		0xFF
+#define PA_CONT_MASK		0xFF
+
+#define MEMCOL_PWL0_OFF		0x88
+#define MEMCOL_PWL0_MASK	0xFFFF07FF
+#define MEMCOL_PWL1_OFF		0x8C
+#define MEMCOL_PWL1_MASK	0xFFFFFFFF
+#define MEMCOL_HUE_REGION_OFF	0x90
+#define MEMCOL_HUE_REGION_MASK	0x7FF07FF
+#define MEMCOL_SAT_REGION_OFF	0x94
+#define MEMCOL_SAT_REGION_MASK	0xFFFFFF
+#define MEMCOL_VAL_REGION_OFF	0x98
+#define MEMCOL_VAL_REGION_MASK	0xFFFFFF
+#define MEMCOL_P0_LEN		0x14
+#define MEMCOL_P1_LEN		0x8
+#define MEMCOL_PWL2_OFF		0x218
+#define MEMCOL_PWL2_MASK	0xFFFFFFFF
+#define MEMCOL_BLEND_GAIN_OFF	0x21C
+#define MEMCOL_PWL_HOLD_OFF	0x214
+
+#define VIG_OP_PA_EN		BIT(4)
+#define VIG_OP_PA_SKIN_EN	BIT(5)
+#define VIG_OP_PA_FOL_EN	BIT(6)
+#define VIG_OP_PA_SKY_EN	BIT(7)
+#define VIG_OP_PA_HUE_EN	BIT(25)
+#define VIG_OP_PA_SAT_EN	BIT(26)
+#define VIG_OP_PA_VAL_EN	BIT(27)
+#define VIG_OP_PA_CONT_EN	BIT(28)
+
+#define DSPP_OP_SZ_VAL_EN	BIT(31)
+#define DSPP_OP_SZ_SAT_EN	BIT(30)
+#define DSPP_OP_SZ_HUE_EN	BIT(29)
+#define DSPP_OP_PA_HUE_EN	BIT(25)
+#define DSPP_OP_PA_SAT_EN	BIT(26)
+#define DSPP_OP_PA_VAL_EN	BIT(27)
+#define DSPP_OP_PA_CONT_EN	BIT(28)
+#define DSPP_OP_PA_EN		BIT(20)
+#define DSPP_OP_PA_LUTV_EN	BIT(19)
+#define DSPP_OP_PA_SKIN_EN	BIT(5)
+#define DSPP_OP_PA_FOL_EN	BIT(6)
+#define DSPP_OP_PA_SKY_EN	BIT(7)
+
+#define REG_MASK(n) ((BIT(n)) - 1)
+
+#define PA_VIG_DISABLE_REQUIRED(x) \
+			!((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
+			VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
+			VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
+			VIG_OP_PA_CONT_EN))
+
+
+#define PA_DSPP_DISABLE_REQUIRED(x) \
+			!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \
+			DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \
+			DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \
+			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))
+
+#define DSPP_OP_PCC_ENABLE	BIT(0)
+#define PCC_OP_MODE_OFF		0
+#define PCC_CONST_COEFF_OFF	4
+#define PCC_R_COEFF_OFF		0x10
+#define PCC_G_COEFF_OFF		0x1C
+#define PCC_B_COEFF_OFF		0x28
+#define PCC_RG_COEFF_OFF	0x34
+#define PCC_RB_COEFF_OFF	0x40
+#define PCC_GB_COEFF_OFF	0x4C
+#define PCC_RGB_COEFF_OFF	0x58
+#define PCC_CONST_COEFF_MASK	0xFFFF
+#define PCC_COEFF_MASK		0x3FFFF
+
+#define SSPP	0
+#define DSPP	1
+
+static void __setup_pa_hue(struct sde_hw_blk_reg_map *hw,
+			const struct sde_pp_blk *blk, uint32_t hue,
+			int location)
+{
+	u32 base = blk->base;
+	u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
+	u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :
+					VIG_OP_PA_HUE_EN;
+	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+	u32 disable_req;
+	u32 opmode;
+
+	SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
+
+	opmode = SDE_REG_READ(hw, base);
+
+	if (!hue) {
+		opmode &= ~op_hue_en;
+		disable_req = (location == DSPP) ?
+			PA_DSPP_DISABLE_REQUIRED(opmode) :
+			PA_VIG_DISABLE_REQUIRED(opmode);
+		if (disable_req)
+			opmode &= ~op_pa_en;
+	} else {
+		opmode |= op_hue_en | op_pa_en;
+	}
+
+	SDE_REG_WRITE(hw, base, opmode);
+}
+
+void sde_setup_pipe_pa_hue_v1_7(struct sde_hw_pipe *ctx, void *cfg)
+{
+	uint32_t hue = *((uint32_t *)cfg);
+
+	__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);
+}
+
+void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+	uint32_t hue = *((uint32_t *)cfg);
+
+	__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
+}
+
+static void __setup_pa_sat(struct sde_hw_blk_reg_map *hw,
+			const struct sde_pp_blk *blk, uint32_t sat,
+			int location)
+{
+	u32 base = blk->base;
+	u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
+	u32 op_sat_en = (location == DSPP) ?
+			DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
+	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+	u32 disable_req;
+	u32 opmode;
+
+	SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
+
+	opmode = SDE_REG_READ(hw, base);
+
+	if (!sat) {
+		opmode &= ~op_sat_en;
+		disable_req = (location == DSPP) ?
+			PA_DSPP_DISABLE_REQUIRED(opmode) :
+			PA_VIG_DISABLE_REQUIRED(opmode);
+		if (disable_req)
+			opmode &= ~op_pa_en;
+	} else {
+		opmode |= op_sat_en | op_pa_en;
+	}
+
+	SDE_REG_WRITE(hw, base, opmode);
+}
+
+void sde_setup_pipe_pa_sat_v1_7(struct sde_hw_pipe *ctx, void *cfg)
+{
+	uint32_t sat = *((uint32_t *)cfg);
+
+	__setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic_blk, sat, SSPP);
+}
+
+static void __setup_pa_val(struct sde_hw_blk_reg_map *hw,
+			const struct sde_pp_blk *blk, uint32_t value,
+			int location)
+{
+	u32 base = blk->base;
+	u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
+	u32 op_val_en = (location == DSPP) ?
+			DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
+	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+	u32 disable_req;
+	u32 opmode;
+
+	SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
+
+	opmode = SDE_REG_READ(hw, base);
+
+	if (!value) {
+		opmode &= ~op_val_en;
+		disable_req = (location == DSPP) ?
+			PA_DSPP_DISABLE_REQUIRED(opmode) :
+			PA_VIG_DISABLE_REQUIRED(opmode);
+		if (disable_req)
+			opmode &= ~op_pa_en;
+	} else {
+		opmode |= op_val_en | op_pa_en;
+	}
+
+	SDE_REG_WRITE(hw, base, opmode);
+}
+
+void sde_setup_pipe_pa_val_v1_7(struct sde_hw_pipe *ctx, void *cfg)
+{
+	uint32_t value = *((uint32_t *)cfg);
+
+	__setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic_blk, value, SSPP);
+}
+
+static void __setup_pa_cont(struct sde_hw_blk_reg_map *hw,
+			const struct sde_pp_blk *blk, uint32_t contrast,
+			int location)
+{
+	u32 base = blk->base;
+	u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
+	u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :
+					VIG_OP_PA_CONT_EN;
+	u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+	u32 disable_req;
+	u32 opmode;
+
+	SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
+
+	opmode = SDE_REG_READ(hw, base);
+
+	if (!contrast) {
+		opmode &= ~op_cont_en;
+		disable_req = (location == DSPP) ?
+			PA_DSPP_DISABLE_REQUIRED(opmode) :
+			PA_VIG_DISABLE_REQUIRED(opmode);
+		if (disable_req)
+			opmode &= ~op_pa_en;
+	} else {
+		opmode |= op_cont_en | op_pa_en;
+	}
+
+	SDE_REG_WRITE(hw, base, opmode);
+}
+
+void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg)
+{
+	uint32_t contrast = *((uint32_t *)cfg);
+
+	__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);
+}
+
+void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,
+				   enum sde_memcolor_type type,
+				   void *cfg)
+{
+	struct drm_msm_memcol *mc = cfg;
+	u32 base = ctx->cap->sblk->memcolor_blk.base;
+	u32 off, op, mc_en, hold = 0;
+	u32 mc_i = 0;
+
+	switch (type) {
+	case MEMCOLOR_SKIN:
+		mc_en = VIG_OP_PA_SKIN_EN;
+		mc_i = 0;
+		break;
+	case MEMCOLOR_SKY:
+		mc_en = VIG_OP_PA_SKY_EN;
+		mc_i = 1;
+		break;
+	case MEMCOLOR_FOLIAGE:
+		mc_en = VIG_OP_PA_FOL_EN;
+		mc_i = 2;
+		break;
+	default:
+		DRM_ERROR("Invalid memory color type %d\n", type);
+		return;
+	}
+
+	op = SDE_REG_READ(&ctx->hw, base);
+	if (!mc) {
+		op &= ~mc_en;
+		if (PA_VIG_DISABLE_REQUIRED(op))
+			op &= ~VIG_OP_PA_EN;
+		SDE_REG_WRITE(&ctx->hw, base, op);
+		return;
+	}
+
+	off = base + (mc_i * MEMCOL_P0_LEN);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL0_OFF),
+		      mc->color_adjust_p0 & MEMCOL_PWL0_MASK);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL1_OFF),
+		      mc->color_adjust_p1 & MEMCOL_PWL1_MASK);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_HUE_REGION_OFF),
+		      mc->hue_region & MEMCOL_HUE_REGION_MASK);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_SAT_REGION_OFF),
+		      mc->sat_region & MEMCOL_SAT_REGION_MASK);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_VAL_REGION_OFF),
+		      mc->val_region & MEMCOL_VAL_REGION_MASK);
+
+	off = base + (mc_i * MEMCOL_P1_LEN);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL2_OFF),
+		      mc->color_adjust_p2 & MEMCOL_PWL2_MASK);
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_BLEND_GAIN_OFF), mc->blend_gain);
+
+	hold = SDE_REG_READ(&ctx->hw, off + MEMCOL_PWL_HOLD_OFF);
+	hold &= ~(0xF << (mc_i * 4));
+	hold |= ((mc->sat_hold & 0x3) << (mc_i * 4));
+	hold |= ((mc->val_hold & 0x3) << ((mc_i * 4) + 2));
+	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL_HOLD_OFF), hold);
+
+	op |= VIG_OP_PA_EN | mc_en;
+	SDE_REG_WRITE(&ctx->hw, base, op);
+}
+
+void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+	struct sde_hw_cp_cfg *hw_cfg = cfg;
+	struct drm_msm_pcc *pcc;
+	void  __iomem *base;
+
+	if (!hw_cfg  || (hw_cfg->len != sizeof(*pcc)  && hw_cfg->payload)) {
+		DRM_ERROR("invalid params hw %p payload %p payloadsize %d \"\
+			  exp size %zd\n",
+			   hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
+			   ((hw_cfg) ? hw_cfg->len : 0), sizeof(*pcc));
+		return;
+	}
+	base = ctx->hw.base_off + ctx->cap->base;
+
+	/* Turn off feature */
+	if (!hw_cfg->payload) {
+		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base,
+			      PCC_OP_MODE_OFF);
+		return;
+	}
+	DRM_DEBUG_DRIVER("Enable PCC feature\n");
+	pcc = hw_cfg->payload;
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF,
+				  pcc->r.c & PCC_CONST_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw,
+		      ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 4,
+		      pcc->g.c & PCC_CONST_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw,
+		      ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 8,
+		      pcc->b.c & PCC_CONST_COEFF_MASK);
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF,
+				  pcc->r.r & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 4,
+				  pcc->g.r & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 8,
+				  pcc->b.r & PCC_COEFF_MASK);
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF,
+				  pcc->r.g & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 4,
+				  pcc->g.g & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 8,
+				  pcc->b.g & PCC_COEFF_MASK);
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF,
+				  pcc->r.b & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 4,
+				  pcc->g.b & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 8,
+				  pcc->b.b & PCC_COEFF_MASK);
+
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF,
+				  pcc->r.rg & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 4,
+				  pcc->g.rg & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 8,
+				  pcc->b.rg & PCC_COEFF_MASK);
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF,
+				  pcc->r.rb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 4,
+				  pcc->g.rb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 8,
+				  pcc->b.rb & PCC_COEFF_MASK);
+
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF,
+				  pcc->r.gb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 4,
+				  pcc->g.gb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 8,
+				  pcc->b.gb & PCC_COEFF_MASK);
+
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF,
+				  pcc->r.rgb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw,
+		      ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 4,
+		      pcc->g.rgb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw,
+		      ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 8,
+		      pcc->b.rgb & PCC_COEFF_MASK);
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, DSPP_OP_PCC_ENABLE);
+}
+
+void sde_setup_dspp_pa_vlut_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+	struct drm_msm_pa_vlut *payload = NULL;
+	struct sde_hw_cp_cfg *hw_cfg = cfg;
+	u32 base = ctx->cap->sblk->vlut.base;
+	u32 offset = base + PA_LUTV_DSPP_OFF;
+	u32 op_mode, tmp;
+	int i = 0, j = 0;
+
+	if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
+			sizeof(struct drm_msm_pa_vlut))) {
+		DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
+			  hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
+			  ((hw_cfg) ? hw_cfg->len : 0),
+			  sizeof(struct drm_msm_pa_vlut));
+		return;
+	}
+	op_mode = SDE_REG_READ(&ctx->hw, base);
+	if (!hw_cfg->payload) {
+		DRM_DEBUG_DRIVER("Disable vlut feature\n");
+		/**
+		 * In the PA_VLUT disable case, remove PA_VLUT enable bit(19)
+		 * first, then check whether any other PA sub-features are
+		 * enabled or not. If none of the sub-features are enabled,
+		 * remove the PA global enable bit(20).
+		 */
+		op_mode &= ~((u32)DSPP_OP_PA_LUTV_EN);
+		if (PA_DSPP_DISABLE_REQUIRED(op_mode))
+			op_mode &= ~((u32)DSPP_OP_PA_EN);
+		SDE_REG_WRITE(&ctx->hw, base, op_mode);
+		return;
+	}
+	payload = hw_cfg->payload;
+	DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
+	for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j += 4) {
+		tmp = (payload->val[i] & REG_MASK(10)) |
+			((payload->val[i + 1] & REG_MASK(10)) << 16);
+		SDE_REG_WRITE(&ctx->hw, (offset + j),
+			     tmp);
+	}
+	SDE_REG_WRITE(&ctx->hw, (base + PA_LUT_SWAP_OFF), 1);
+	op_mode |= DSPP_OP_PA_EN | DSPP_OP_PA_LUTV_EN;
+	SDE_REG_WRITE(&ctx->hw, base, op_mode);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
new file mode 100644
index 0000000000000000000000000000000000000000..0f9bc0e38322eb37f125373aadab130226db982e
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
@@ -0,0 +1,78 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_COLOR_PROCESSING_V1_7_H
+#define _SDE_HW_COLOR_PROCESSING_V1_7_H
+
+#include "sde_hw_sspp.h"
+#include "sde_hw_dspp.h"
+
+/**
+ * sde_setup_pipe_pa_hue_v1_7 - setup SSPP hue feature in v1.7 hardware
+ * @ctx: Pointer to pipe context
+ * @cfg: Pointer to hue data
+ */
+void sde_setup_pipe_pa_hue_v1_7(struct sde_hw_pipe *ctx, void *cfg);
+
+/**
+ * sde_setup_pipe_pa_sat_v1_7 - setup SSPP saturation feature in v1.7 hardware
+ * @ctx: Pointer to pipe context
+ * @cfg: Pointer to saturation data
+ */
+void sde_setup_pipe_pa_sat_v1_7(struct sde_hw_pipe *ctx, void *cfg);
+
+/**
+ * sde_setup_pipe_pa_val_v1_7 - setup SSPP value feature in v1.7 hardware
+ * @ctx: Pointer to pipe context
+ * @cfg: Pointer to value data
+ */
+void sde_setup_pipe_pa_val_v1_7(struct sde_hw_pipe *ctx, void *cfg);
+
+/**
+ * sde_setup_pipe_pa_cont_v1_7 - setup SSPP contrast feature in v1.7 hardware
+ * @ctx: Pointer to pipe context
+ * @cfg: Pointer to contrast data
+ */
+void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg);
+
+/**
+ * sde_setup_pipe_pa_memcol_v1_7 - setup SSPP memory color in v1.7 hardware
+ * @ctx: Pointer to pipe context
+ * @type: Memory color type (Skin, sky, or foliage)
+ * @cfg: Pointer to memory color config data
+ */
+void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,
+				   enum sde_memcolor_type type,
+				   void *cfg);
+
+/**
+ * sde_setup_dspp_pcc_v1_7 - setup DSPP PCC veature in v1.7 hardware
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to PCC data
+ */
+void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to hue data
+ */
+void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to vLUT data
+ */
+void sde_setup_dspp_pa_vlut_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
+#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
new file mode 100644
index 0000000000000000000000000000000000000000..56d9f2a4a9b8d86a95e9b6245282bb193b586f90
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
@@ -0,0 +1,461 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include "sde_hwio.h"
+#include "sde_hw_ctl.h"
+
+#define   CTL_LAYER(lm)                 \
+	(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
+#define   CTL_LAYER_EXT(lm)             \
+	(0x40 + (((lm) - LM_0) * 0x004))
+#define   CTL_LAYER_EXT2(lm)             \
+	(0x70 + (((lm) - LM_0) * 0x004))
+#define   CTL_TOP                       0x014
+#define   CTL_FLUSH                     0x018
+#define   CTL_START                     0x01C
+#define   CTL_SW_RESET                  0x030
+#define   CTL_LAYER_EXTN_OFFSET         0x40
+
+#define SDE_REG_RESET_TIMEOUT_COUNT    20
+
+static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->ctl_count; i++) {
+		if (ctl == m->ctl[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->ctl[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_CTL;
+			return &m->ctl[i];
+		}
+	}
+	return ERR_PTR(-ENOMEM);
+}
+
+static int _mixer_stages(const struct sde_lm_cfg *mixer, int count,
+		enum sde_lm lm)
+{
+	int i;
+	int stages = -EINVAL;
+
+	for (i = 0; i < count; i++) {
+		if (lm == mixer[i].id) {
+			stages = mixer[i].sblk->maxblendstages;
+			break;
+		}
+	}
+
+	return stages;
+}
+
+static inline void sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx)
+{
+	SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
+}
+
+static inline void sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx)
+{
+	ctx->pending_flush_mask = 0x0;
+}
+
+static inline void sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx,
+		u32 flushbits)
+{
+	ctx->pending_flush_mask |= flushbits;
+}
+
+static u32 sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx)
+{
+	if (!ctx)
+		return 0x0;
+
+	return ctx->pending_flush_mask;
+}
+
+static inline void sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx)
+{
+	SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
+}
+
+
+static inline uint32_t sde_hw_ctl_get_bitmask_sspp(struct sde_hw_ctl *ctx,
+	enum sde_sspp sspp)
+{
+	uint32_t flushbits = 0;
+
+	switch (sspp) {
+	case SSPP_VIG0:
+		flushbits =  BIT(0);
+		break;
+	case SSPP_VIG1:
+		flushbits = BIT(1);
+		break;
+	case SSPP_VIG2:
+		flushbits = BIT(2);
+		break;
+	case SSPP_VIG3:
+		flushbits = BIT(18);
+		break;
+	case SSPP_RGB0:
+		flushbits = BIT(3);
+		break;
+	case SSPP_RGB1:
+		flushbits = BIT(4);
+		break;
+	case SSPP_RGB2:
+		flushbits = BIT(5);
+		break;
+	case SSPP_RGB3:
+		flushbits = BIT(19);
+		break;
+	case SSPP_DMA0:
+		flushbits = BIT(11);
+		break;
+	case SSPP_DMA1:
+		flushbits = BIT(12);
+		break;
+	case SSPP_DMA2:
+		flushbits = BIT(24);
+		break;
+	case SSPP_DMA3:
+		flushbits = BIT(25);
+		break;
+	case SSPP_CURSOR0:
+		flushbits = BIT(22);
+		break;
+	case SSPP_CURSOR1:
+		flushbits = BIT(23);
+		break;
+	default:
+		break;
+	}
+
+	return flushbits;
+}
+
+static inline uint32_t sde_hw_ctl_get_bitmask_mixer(struct sde_hw_ctl *ctx,
+	enum sde_lm lm)
+{
+	uint32_t flushbits = 0;
+
+	switch (lm) {
+	case LM_0:
+		flushbits = BIT(6);
+		break;
+	case LM_1:
+		flushbits = BIT(7);
+		break;
+	case LM_2:
+		flushbits = BIT(8);
+		break;
+	case LM_3:
+		flushbits = BIT(9);
+		break;
+	case LM_4:
+		flushbits = BIT(10);
+		break;
+	case LM_5:
+		flushbits = BIT(20);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	flushbits |= BIT(17); /* CTL */
+
+	return flushbits;
+}
+
+static inline int sde_hw_ctl_get_bitmask_dspp(struct sde_hw_ctl *ctx,
+		u32 *flushbits, enum sde_dspp dspp)
+{
+	switch (dspp) {
+	case DSPP_0:
+		*flushbits |= BIT(13);
+		break;
+	case DSPP_1:
+		*flushbits |= BIT(14);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline int sde_hw_ctl_get_bitmask_intf(struct sde_hw_ctl *ctx,
+		u32 *flushbits, enum sde_intf intf)
+{
+	switch (intf) {
+	case INTF_0:
+		*flushbits |= BIT(31);
+		break;
+	case INTF_1:
+		*flushbits |= BIT(30);
+		break;
+	case INTF_2:
+		*flushbits |= BIT(29);
+		break;
+	case INTF_3:
+		*flushbits |= BIT(28);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline int sde_hw_ctl_get_bitmask_wb(struct sde_hw_ctl *ctx,
+		u32 *flushbits, enum sde_wb wb)
+{
+	switch (wb) {
+	case WB_0:
+	case WB_1:
+	case WB_2:
+		*flushbits |= BIT(16);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline int sde_hw_ctl_get_bitmask_cdm(struct sde_hw_ctl *ctx,
+		u32 *flushbits, enum sde_cdm cdm)
+{
+	switch (cdm) {
+	case CDM_0:
+		*flushbits |= BIT(26);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	int count = SDE_REG_RESET_TIMEOUT_COUNT;
+	int reset;
+
+	SDE_REG_WRITE(c, CTL_SW_RESET, 0x1);
+
+	for (; count > 0; count--) {
+		/* insert small delay to avoid spinning the cpu while waiting */
+		usleep_range(20, 50);
+		reset = SDE_REG_READ(c, CTL_SW_RESET);
+		if (reset == 0)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	int i;
+
+	for (i = 0; i < ctx->mixer_count; i++) {
+		SDE_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0);
+		SDE_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0);
+	}
+}
+
+static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
+	enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg, u32 index)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 mixercfg, mixercfg_ext, mix, ext, mixercfg_ext2;
+	int i, j;
+	u8 stages;
+	int pipes_per_stage;
+
+	if (index >= CRTC_DUAL_MIXERS)
+		return;
+
+	stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
+	if (stages < 0)
+		return;
+
+	if (test_bit(SDE_MIXER_SOURCESPLIT,
+		&ctx->mixer_hw_caps->features))
+		pipes_per_stage = PIPES_PER_STAGE;
+	else
+		pipes_per_stage = 1;
+
+	mixercfg = BIT(24); /* always set BORDER_OUT */
+	mixercfg_ext = 0;
+	mixercfg_ext2 = 0;
+
+	for (i = 0; i <= stages; i++) {
+		/* overflow to ext register if 'i + 1 > 7' */
+		mix = (i + 1) & 0x7;
+		ext = i >= 7;
+
+		for (j = 0 ; j < pipes_per_stage; j++) {
+			switch (stage_cfg->stage[index][i][j]) {
+			case SSPP_VIG0:
+				mixercfg |= mix << 0;
+				mixercfg_ext |= ext << 0;
+				break;
+			case SSPP_VIG1:
+				mixercfg |= mix << 3;
+				mixercfg_ext |= ext << 2;
+				break;
+			case SSPP_VIG2:
+				mixercfg |= mix << 6;
+				mixercfg_ext |= ext << 4;
+				break;
+			case SSPP_VIG3:
+				mixercfg |= mix << 26;
+				mixercfg_ext |= ext << 6;
+				break;
+			case SSPP_RGB0:
+				mixercfg |= mix << 9;
+				mixercfg_ext |= ext << 8;
+				break;
+			case SSPP_RGB1:
+				mixercfg |= mix << 12;
+				mixercfg_ext |= ext << 10;
+				break;
+			case SSPP_RGB2:
+				mixercfg |= mix << 15;
+				mixercfg_ext |= ext << 12;
+				break;
+			case SSPP_RGB3:
+				mixercfg |= mix << 29;
+				mixercfg_ext |= ext << 14;
+				break;
+			case SSPP_DMA0:
+				mixercfg |= mix << 18;
+				mixercfg_ext |= ext << 16;
+				break;
+			case SSPP_DMA1:
+				mixercfg |= mix << 21;
+				mixercfg_ext |= ext << 18;
+				break;
+			case SSPP_DMA2:
+				mix = (i + 1) & 0xf;
+				mixercfg_ext2 |= mix << 0;
+				break;
+			case SSPP_DMA3:
+				mix = (i + 1) & 0xf;
+				mixercfg_ext2 |= mix << 4;
+				break;
+			case SSPP_CURSOR0:
+				mixercfg_ext |= ((i + 1) & 0xF) << 20;
+				break;
+			case SSPP_CURSOR1:
+				mixercfg_ext |= ((i + 1) & 0xF) << 26;
+				break;
+			default:
+				break;
+			}
+		}
+	}
+
+	SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
+	SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
+	SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
+}
+
+static void sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx,
+		struct sde_hw_intf_cfg *cfg)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 intf_cfg = 0;
+
+	intf_cfg |= (cfg->intf & 0xF) << 4;
+
+	if (cfg->wb)
+		intf_cfg |= (cfg->wb & 0x3) + 2;
+
+	if (cfg->mode_3d) {
+		intf_cfg |= BIT(19);
+		intf_cfg |= (cfg->mode_3d - 0x1) << 20;
+	}
+
+	switch (cfg->intf_mode_sel) {
+	case SDE_CTL_MODE_SEL_VID:
+		intf_cfg &= ~BIT(17);
+		intf_cfg &= ~(0x3 << 15);
+		break;
+	case SDE_CTL_MODE_SEL_CMD:
+		intf_cfg |= BIT(17);
+		intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
+		break;
+	default:
+		pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
+		return;
+	}
+
+	SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
+}
+
+static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
+		unsigned long cap)
+{
+	ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
+	ops->update_pending_flush = sde_hw_ctl_update_pending_flush;
+	ops->get_pending_flush = sde_hw_ctl_get_pending_flush;
+	ops->trigger_flush = sde_hw_ctl_trigger_flush;
+	ops->trigger_start = sde_hw_ctl_trigger_start;
+	ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
+	ops->reset = sde_hw_ctl_reset_control;
+	ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages;
+	ops->setup_blendstage = sde_hw_ctl_setup_blendstage;
+	ops->get_bitmask_sspp = sde_hw_ctl_get_bitmask_sspp;
+	ops->get_bitmask_mixer = sde_hw_ctl_get_bitmask_mixer;
+	ops->get_bitmask_dspp = sde_hw_ctl_get_bitmask_dspp;
+	ops->get_bitmask_intf = sde_hw_ctl_get_bitmask_intf;
+	ops->get_bitmask_cdm = sde_hw_ctl_get_bitmask_cdm;
+	ops->get_bitmask_wb = sde_hw_ctl_get_bitmask_wb;
+};
+
+struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m)
+{
+	struct sde_hw_ctl *c;
+	struct sde_ctl_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _ctl_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		pr_err("failed to create sde_hw_ctl %d\n", idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	c->caps = cfg;
+	_setup_ctl_ops(&c->ops, c->caps->features);
+	c->idx = idx;
+	c->mixer_count = m->mixer_count;
+	c->mixer_hw_caps = m->mixer;
+
+	return c;
+}
+
+void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx)
+{
+	kfree(ctx);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
new file mode 100644
index 0000000000000000000000000000000000000000..2fb7b377e51d7ab9abf2fe9781a6049053623372
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
@@ -0,0 +1,186 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_CTL_H
+#define _SDE_HW_CTL_H
+
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+#include "sde_hw_catalog.h"
+
+/**
+ * sde_ctl_mode_sel: Interface mode selection
+ * SDE_CTL_MODE_SEL_VID:    Video mode interface
+ * SDE_CTL_MODE_SEL_CMD:    Command mode interface
+ */
+enum sde_ctl_mode_sel {
+	SDE_CTL_MODE_SEL_VID = 0,
+	SDE_CTL_MODE_SEL_CMD
+};
+
+struct sde_hw_ctl;
+/**
+ * struct sde_hw_stage_cfg - blending stage cfg
+ * @stage
+ */
+struct sde_hw_stage_cfg {
+	enum sde_sspp stage[CRTC_DUAL_MIXERS][SDE_STAGE_MAX][PIPES_PER_STAGE];
+};
+
+/**
+ * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface
+ * @intf :                 Interface id
+ * @wb:                    Writeback id
+ * @mode_3d:               3d mux configuration
+ * @intf_mode_sel:         Interface mode, cmd / vid
+ * @stream_sel:            Stream selection for multi-stream interfaces
+ */
+struct sde_hw_intf_cfg {
+	enum sde_intf intf;
+	enum sde_wb wb;
+	enum sde_3d_blend_mode mode_3d;
+	enum sde_ctl_mode_sel intf_mode_sel;
+	int stream_sel;
+};
+
+/**
+ * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions
+ * Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_ctl_ops {
+	/**
+	 * kickoff hw operation for Sw controlled interfaces
+	 * DSI cmd mode and WB interface are SW controlled
+	 * @ctx       : ctl path ctx pointer
+	 */
+	void (*trigger_start)(struct sde_hw_ctl *ctx);
+
+	/**
+	 * Clear the value of the cached pending_flush_mask
+	 * No effect on hardware
+	 * @ctx       : ctl path ctx pointer
+	 */
+	void (*clear_pending_flush)(struct sde_hw_ctl *ctx);
+
+	/**
+	 * Query the value of the cached pending_flush_mask
+	 * No effect on hardware
+	 * @ctx       : ctl path ctx pointer
+	 */
+	u32 (*get_pending_flush)(struct sde_hw_ctl *ctx);
+
+	/**
+	 * OR in the given flushbits to the cached pending_flush_mask
+	 * No effect on hardware
+	 * @ctx       : ctl path ctx pointer
+	 * @flushbits : module flushmask
+	 */
+	void (*update_pending_flush)(struct sde_hw_ctl *ctx,
+		u32 flushbits);
+
+	/**
+	 * Write the value of the pending_flush_mask to hardware
+	 * @ctx       : ctl path ctx pointer
+	 */
+	void (*trigger_flush)(struct sde_hw_ctl *ctx);
+
+	/**
+	 * Setup ctl_path interface config
+	 * @ctx
+	 * @cfg    : interface config structure pointer
+	 */
+	void (*setup_intf_cfg)(struct sde_hw_ctl *ctx,
+		struct sde_hw_intf_cfg *cfg);
+
+	int (*reset)(struct sde_hw_ctl *c);
+
+	uint32_t (*get_bitmask_sspp)(struct sde_hw_ctl *ctx,
+		enum sde_sspp blk);
+
+	uint32_t (*get_bitmask_mixer)(struct sde_hw_ctl *ctx,
+		enum sde_lm blk);
+
+	int (*get_bitmask_dspp)(struct sde_hw_ctl *ctx,
+		u32 *flushbits,
+		enum sde_dspp blk);
+
+	int (*get_bitmask_intf)(struct sde_hw_ctl *ctx,
+		u32 *flushbits,
+		enum sde_intf blk);
+
+	int (*get_bitmask_cdm)(struct sde_hw_ctl *ctx,
+		u32 *flushbits,
+		enum sde_cdm blk);
+
+	int (*get_bitmask_wb)(struct sde_hw_ctl *ctx,
+		u32 *flushbits,
+		enum sde_wb blk);
+
+	/**
+	 * Set all blend stages to disabled
+	 * @ctx       : ctl path ctx pointer
+	 */
+	void (*clear_all_blendstages)(struct sde_hw_ctl *ctx);
+
+	/**
+	 * Configure layer mixer to pipe configuration
+	 * @ctx       : ctl path ctx pointer
+	 * @lm        : layer mixer enumeration
+	 * @cfg       : blend stage configuration
+	 */
+	void (*setup_blendstage)(struct sde_hw_ctl *ctx,
+		enum sde_lm lm, struct sde_hw_stage_cfg *cfg, u32 index);
+};
+
+/**
+ * struct sde_hw_ctl : CTL PATH driver object
+ * @hw: block register map object
+ * @idx: control path index
+ * @ctl_hw_caps: control path capabilities
+ * @mixer_count: number of mixers
+ * @mixer_hw_caps: mixer hardware capabilities
+ * @pending_flush_mask: storage for pending ctl_flush managed via ops
+ * @ops: operation list
+ */
+struct sde_hw_ctl {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* ctl path */
+	int idx;
+	const struct sde_ctl_cfg *caps;
+	int mixer_count;
+	const struct sde_lm_cfg *mixer_hw_caps;
+	u32 pending_flush_mask;
+
+	/* ops */
+	struct sde_hw_ctl_ops ops;
+};
+
+/**
+ * sde_hw_ctl_init(): Initializes the ctl_path hw driver object.
+ * should be called before accessing every ctl path registers.
+ * @idx:  ctl_path index for which driver object is required
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ */
+struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_ctl_destroy(): Destroys ctl driver context
+ * should be called to free the context
+ */
+void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx);
+
+#endif /*_SDE_HW_CTL_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
new file mode 100644
index 0000000000000000000000000000000000000000..d6250b07b4f02cdd3838b39570e7f9d0230cfb51
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -0,0 +1,120 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <drm/msm_drm_pp.h>
+#include "sde_hw_mdss.h"
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_dspp.h"
+#include "sde_hw_color_processing.h"
+
+static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->dspp_count; i++) {
+		if (dspp == m->dspp[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->dspp[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_DSPP;
+			return &m->dspp[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+void sde_dspp_setup_histogram(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+void sde_dspp_read_histogram(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+void sde_dspp_update_igc(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+void sde_dspp_setup_sharpening(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+void sde_dspp_setup_danger_safe(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+void sde_dspp_setup_dither(struct sde_hw_dspp *ctx, void *cfg)
+{
+}
+
+static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
+{
+	int i = 0;
+
+	for (i = 0; i < SDE_DSPP_MAX; i++) {
+		if (!test_bit(i, &features))
+			continue;
+		switch (i) {
+		case SDE_DSPP_PCC:
+			if (c->cap->sblk->pcc.version ==
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
+				c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;
+			break;
+		case SDE_DSPP_HSIC:
+			if (c->cap->sblk->hsic.version ==
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
+				c->ops.setup_hue = sde_setup_dspp_pa_hue_v1_7;
+			break;
+		case SDE_DSPP_VLUT:
+			if (c->cap->sblk->vlut.version ==
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
+				c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;
+			}
+		default:
+			break;
+		}
+	}
+}
+
+struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
+			void __iomem *addr,
+			struct sde_mdss_cfg *m)
+{
+	struct sde_hw_dspp *c;
+	struct sde_dspp_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _dspp_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Assign ops */
+	c->idx = idx;
+	c->cap = cfg;
+	_setup_dspp_ops(c, c->cap->features);
+
+	return c;
+}
+
+void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp)
+{
+	kfree(dspp);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e6ad2f8d0e5e29f7d4660bd29f4b8a9f79be177
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
@@ -0,0 +1,183 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_DSPP_H
+#define _SDE_HW_DSPP_H
+
+struct sde_hw_dspp;
+
+/**
+ * struct sde_hw_dspp_ops - interface to the dspp hardware driver functions
+ * Caller must call the init function to get the dspp context for each dspp
+ * Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_dspp_ops {
+	/**
+	 * setup_histogram - setup dspp histogram
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_histogram)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * read_histogram - read dspp histogram
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*read_histogram)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_igc - update dspp igc
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_igc)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_pa - setup dspp pa
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_pa)(struct sde_hw_dspp *dspp, void *cfg);
+
+	/**
+	 * setup_pcc - setup dspp pcc
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_pcc)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_sharpening - setup dspp sharpening
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_sharpening)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_pa_memcolor - setup dspp memcolor
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_pa_memcolor)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_sixzone - setup dspp six zone
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_sixzone)(struct sde_hw_dspp *dspp, void *cfg);
+
+	/**
+	 * setup_danger_safe - setup danger safe LUTS
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_danger_safe)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_dither - setup dspp dither
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_dither)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_hue - setup dspp PA hue
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_hue)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_sat - setup dspp PA saturation
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_sat)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_val - setup dspp PA value
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_val)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_cont - setup dspp PA contrast
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_cont)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_vlut - setup dspp PA VLUT
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_vlut)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_gc - update dspp gc
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_gc)(struct sde_hw_dspp *ctx, void *cfg);
+
+	/**
+	 * setup_gamut - update dspp gamut
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_gamut)(struct sde_hw_dspp *ctx, void *cfg);
+};
+
+/**
+ * struct sde_hw_dspp - dspp description
+ * @base_off:     MDP register mapped offset
+ * @blk_off:      DSPP offset relative to mdss offset
+ * @length        Length of register block offset
+ * @hwversion     Mdss hw version number
+ * @idx:          DSPP index
+ * @dspp_hw_cap:  Pointer to layer_cfg
+ * @highest_bank_bit:
+ * @ops:          Pointer to operations possible for this dspp
+ */
+struct sde_hw_dspp {
+	/* base */
+	 struct sde_hw_blk_reg_map hw;
+
+	/* dspp */
+	enum sde_dspp idx;
+	const struct sde_dspp_cfg *cap;
+
+	/* Ops */
+	struct sde_hw_dspp_ops ops;
+};
+
+/**
+ * sde_hw_dspp_init - initializes the dspp hw driver object.
+ * should be called once before accessing every dspp.
+ * @idx:  DSPP index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ */
+struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
+			void __iomem *addr,
+			struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_dspp_destroy(): Destroys DSPP driver context
+ * @dspp:   Pointer to DSPP driver context
+ */
+void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp);
+
+#endif /*_SDE_HW_DSPP_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_hwio.h b/drivers/gpu/drm/msm/sde/sde_hw_hwio.h
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
new file mode 100644
index 0000000000000000000000000000000000000000..49930365d98996422c218114519b04358e03b221
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
@@ -0,0 +1,991 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/slab.h>
+
+#include "sde_kms.h"
+#include "sde_hw_interrupts.h"
+#include "sde_hw_util.h"
+#include "sde_hw_mdss.h"
+
+/**
+ * Register offsets in MDSS register file for the interrupt registers
+ * w.r.t. to the MDSS base
+ */
+#define HW_INTR_STATUS			0x0010
+#define MDP_SSPP_TOP0_OFF		0x1000
+#define MDP_INTF_0_OFF			0x6B000
+#define MDP_INTF_1_OFF			0x6B800
+#define MDP_INTF_2_OFF			0x6C000
+#define MDP_INTF_3_OFF			0x6C800
+#define MDP_INTF_4_OFF			0x6D000
+
+/**
+ * WB interrupt status bit definitions
+ */
+#define SDE_INTR_WB_0_DONE BIT(0)
+#define SDE_INTR_WB_1_DONE BIT(1)
+#define SDE_INTR_WB_2_DONE BIT(4)
+
+/**
+ * WDOG timer interrupt status bit definitions
+ */
+#define SDE_INTR_WD_TIMER_0_DONE BIT(2)
+#define SDE_INTR_WD_TIMER_1_DONE BIT(3)
+#define SDE_INTR_WD_TIMER_2_DONE BIT(5)
+#define SDE_INTR_WD_TIMER_3_DONE BIT(6)
+#define SDE_INTR_WD_TIMER_4_DONE BIT(7)
+
+/**
+ * Pingpong interrupt status bit definitions
+ */
+#define SDE_INTR_PING_PONG_0_DONE BIT(8)
+#define SDE_INTR_PING_PONG_1_DONE BIT(9)
+#define SDE_INTR_PING_PONG_2_DONE BIT(10)
+#define SDE_INTR_PING_PONG_3_DONE BIT(11)
+#define SDE_INTR_PING_PONG_0_RD_PTR BIT(12)
+#define SDE_INTR_PING_PONG_1_RD_PTR BIT(13)
+#define SDE_INTR_PING_PONG_2_RD_PTR BIT(14)
+#define SDE_INTR_PING_PONG_3_RD_PTR BIT(15)
+#define SDE_INTR_PING_PONG_0_WR_PTR BIT(16)
+#define SDE_INTR_PING_PONG_1_WR_PTR BIT(17)
+#define SDE_INTR_PING_PONG_2_WR_PTR BIT(18)
+#define SDE_INTR_PING_PONG_3_WR_PTR BIT(19)
+#define SDE_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
+#define SDE_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
+#define SDE_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
+#define SDE_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
+
+/**
+ * Interface interrupt status bit definitions
+ */
+#define SDE_INTR_INTF_0_UNDERRUN BIT(24)
+#define SDE_INTR_INTF_1_UNDERRUN BIT(26)
+#define SDE_INTR_INTF_2_UNDERRUN BIT(28)
+#define SDE_INTR_INTF_3_UNDERRUN BIT(30)
+#define SDE_INTR_INTF_0_VSYNC BIT(25)
+#define SDE_INTR_INTF_1_VSYNC BIT(27)
+#define SDE_INTR_INTF_2_VSYNC BIT(29)
+#define SDE_INTR_INTF_3_VSYNC BIT(31)
+
+/**
+ * Pingpong Secondary interrupt status bit definitions
+ */
+#define SDE_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
+#define	SDE_INTR_PING_PONG_S0_WR_PTR BIT(4)
+#define SDE_INTR_PING_PONG_S0_RD_PTR BIT(8)
+#define SDE_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
+#define SDE_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
+
+/**
+ * Pingpong TEAR detection interrupt status bit definitions
+ */
+#define SDE_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
+#define SDE_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
+#define SDE_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
+#define SDE_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
+
+/**
+ * Pingpong TE detection interrupt status bit definitions
+ */
+#define SDE_INTR_PING_PONG_0_TE_DETECTED BIT(24)
+#define SDE_INTR_PING_PONG_1_TE_DETECTED BIT(25)
+#define SDE_INTR_PING_PONG_2_TE_DETECTED BIT(26)
+#define SDE_INTR_PING_PONG_3_TE_DETECTED BIT(27)
+
+/**
+ * Concurrent WB overflow interrupt status bit definitions
+ */
+#define SDE_INTR_CWB_2_OVERFLOW BIT(14)
+#define SDE_INTR_CWB_3_OVERFLOW BIT(15)
+
+/**
+ * Histogram VIG done interrupt status bit definitions
+ */
+#define SDE_INTR_HIST_VIG_0_DONE BIT(0)
+#define SDE_INTR_HIST_VIG_1_DONE BIT(4)
+#define SDE_INTR_HIST_VIG_2_DONE BIT(8)
+#define SDE_INTR_HIST_VIG_3_DONE BIT(10)
+
+/**
+ * Histogram VIG reset Sequence done interrupt status bit definitions
+ */
+#define SDE_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
+#define SDE_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
+#define SDE_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
+#define SDE_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
+
+/**
+ * Histogram DSPP done interrupt status bit definitions
+ */
+#define SDE_INTR_HIST_DSPP_0_DONE BIT(12)
+#define SDE_INTR_HIST_DSPP_1_DONE BIT(16)
+#define SDE_INTR_HIST_DSPP_2_DONE BIT(20)
+#define SDE_INTR_HIST_DSPP_3_DONE BIT(22)
+
+/**
+ * Histogram DSPP reset Sequence done interrupt status bit definitions
+ */
+#define SDE_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
+#define SDE_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
+#define SDE_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
+#define SDE_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
+
+/**
+ * INTF interrupt status bit definitions
+ */
+#define SDE_INTR_VIDEO_INTO_STATIC BIT(0)
+#define SDE_INTR_VIDEO_OUTOF_STATIC BIT(1)
+#define SDE_INTR_DSICMD_0_INTO_STATIC BIT(2)
+#define SDE_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
+#define SDE_INTR_DSICMD_1_INTO_STATIC BIT(4)
+#define SDE_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
+#define SDE_INTR_DSICMD_2_INTO_STATIC BIT(6)
+#define SDE_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
+#define SDE_INTR_PROG_LINE BIT(8)
+
+/**
+ * struct sde_intr_reg - array of SDE register sets
+ * @clr_off:	offset to CLEAR reg
+ * @en_off:	offset to ENABLE reg
+ * @status_off:	offset to STATUS reg
+ */
+struct sde_intr_reg {
+	u32 clr_off;
+	u32 en_off;
+	u32 status_off;
+};
+
+/**
+ * struct sde_irq_type - maps each irq with i/f
+ * @intr_type:		type of interrupt listed in sde_intr_type
+ * @instance_idx:	instance index of the associated HW block in SDE
+ * @irq_mask:		corresponding bit in the interrupt status reg
+ * @reg_idx:		which reg set to use
+ */
+struct sde_irq_type {
+	u32 intr_type;
+	u32 instance_idx;
+	u32 irq_mask;
+	u32 reg_idx;
+};
+
+/**
+ * List of SDE interrupt registers
+ */
+static const struct sde_intr_reg sde_intr_set[] = {
+	{
+		MDP_SSPP_TOP0_OFF+INTR_CLEAR,
+		MDP_SSPP_TOP0_OFF+INTR_EN,
+		MDP_SSPP_TOP0_OFF+INTR_STATUS
+	},
+	{
+		MDP_SSPP_TOP0_OFF+INTR2_CLEAR,
+		MDP_SSPP_TOP0_OFF+INTR2_EN,
+		MDP_SSPP_TOP0_OFF+INTR2_STATUS
+	},
+	{
+		MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR,
+		MDP_SSPP_TOP0_OFF+HIST_INTR_EN,
+		MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS
+	},
+	{
+		MDP_INTF_0_OFF+INTF_INTR_CLEAR,
+		MDP_INTF_0_OFF+INTF_INTR_EN,
+		MDP_INTF_0_OFF+INTF_INTR_STATUS
+	},
+	{
+		MDP_INTF_1_OFF+INTF_INTR_CLEAR,
+		MDP_INTF_1_OFF+INTF_INTR_EN,
+		MDP_INTF_1_OFF+INTF_INTR_STATUS
+	},
+	{
+		MDP_INTF_2_OFF+INTF_INTR_CLEAR,
+		MDP_INTF_2_OFF+INTF_INTR_EN,
+		MDP_INTF_2_OFF+INTF_INTR_STATUS
+	},
+	{
+		MDP_INTF_3_OFF+INTF_INTR_CLEAR,
+		MDP_INTF_3_OFF+INTF_INTR_EN,
+		MDP_INTF_3_OFF+INTF_INTR_STATUS
+	},
+	{
+		MDP_INTF_4_OFF+INTF_INTR_CLEAR,
+		MDP_INTF_4_OFF+INTF_INTR_EN,
+		MDP_INTF_4_OFF+INTF_INTR_STATUS
+	}
+};
+
+/**
+ * IRQ mapping table - use for lookup an irq_idx in this table that have
+ *                     a matching interface type and instance index.
+ */
+static const struct sde_irq_type sde_irq_map[] = {
+	/* BEGIN MAP_RANGE: 0-31, INTR */
+	/* irq_idx: 0-3 */
+	{ SDE_IRQ_TYPE_WB_ROT_COMP, WB_0, SDE_INTR_WB_0_DONE, 0},
+	{ SDE_IRQ_TYPE_WB_ROT_COMP, WB_1, SDE_INTR_WB_1_DONE, 0},
+	{ SDE_IRQ_TYPE_WD_TIMER, WD_TIMER_0, SDE_INTR_WD_TIMER_0_DONE, 0},
+	{ SDE_IRQ_TYPE_WD_TIMER, WD_TIMER_1, SDE_INTR_WD_TIMER_1_DONE, 0},
+	/* irq_idx: 4-7 */
+	{ SDE_IRQ_TYPE_WB_WFD_COMP, WB_2, SDE_INTR_WB_2_DONE, 0},
+	{ SDE_IRQ_TYPE_WD_TIMER, WD_TIMER_2, SDE_INTR_WD_TIMER_2_DONE, 0},
+	{ SDE_IRQ_TYPE_WD_TIMER, WD_TIMER_3, SDE_INTR_WD_TIMER_3_DONE, 0},
+	{ SDE_IRQ_TYPE_WD_TIMER, WD_TIMER_4, SDE_INTR_WD_TIMER_4_DONE, 0},
+	/* irq_idx: 8-11 */
+	{ SDE_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_DONE, 0},
+	/* irq_idx: 12-15 */
+	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_RD_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_RD_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_RD_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_RD_PTR, 0},
+	/* irq_idx: 16-19 */
+	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_WR_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_WR_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_WR_PTR, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_WR_PTR, 0},
+	/* irq_idx: 20-23 */
+	{ SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
+	{ SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
+	/* irq_idx: 24-27 */
+	{ SDE_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, SDE_INTR_INTF_0_UNDERRUN, 0},
+	{ SDE_IRQ_TYPE_INTF_VSYNC, INTF_0, SDE_INTR_INTF_0_VSYNC, 0},
+	{ SDE_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, SDE_INTR_INTF_1_UNDERRUN, 0},
+	{ SDE_IRQ_TYPE_INTF_VSYNC, INTF_1, SDE_INTR_INTF_1_VSYNC, 0},
+	/* irq_idx: 28-31 */
+	{ SDE_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, SDE_INTR_INTF_2_UNDERRUN, 0},
+	{ SDE_IRQ_TYPE_INTF_VSYNC, INTF_2, SDE_INTR_INTF_2_VSYNC, 0},
+	{ SDE_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, SDE_INTR_INTF_3_UNDERRUN, 0},
+	{ SDE_IRQ_TYPE_INTF_VSYNC, INTF_3, SDE_INTR_INTF_3_VSYNC, 0},
+
+	/* BEGIN MAP_RANGE: 32-64, INTR2 */
+	/* irq_idx: 32-35 */
+	{ SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
+		SDE_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	/* irq_idx: 36-39 */
+	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
+		SDE_INTR_PING_PONG_S0_WR_PTR, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	/* irq_idx: 40-43 */
+	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
+		SDE_INTR_PING_PONG_S0_RD_PTR, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	/* irq_idx: 44-47 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_2, SDE_INTR_CWB_2_OVERFLOW, 1},
+	{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_3, SDE_INTR_CWB_3_OVERFLOW, 1},
+	/* irq_idx: 48-51 */
+	{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_TEAR_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_TEAR_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_TEAR_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_TEAR_DETECTED, 1},
+	/* irq_idx: 52-55 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
+		SDE_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	/* irq_idx: 56-59 */
+	{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
+		SDE_INTR_PING_PONG_0_TE_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
+		SDE_INTR_PING_PONG_1_TE_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
+		SDE_INTR_PING_PONG_2_TE_DETECTED, 1},
+	{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
+		SDE_INTR_PING_PONG_3_TE_DETECTED, 1},
+	/* irq_idx: 60-63 */
+	{ SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
+		SDE_INTR_PING_PONG_S0_TE_DETECTED, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+
+	/* BEGIN MAP_RANGE: 64-95 HIST */
+	/* irq_idx: 64-67 */
+	{ SDE_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, SDE_INTR_HIST_VIG_0_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
+		SDE_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 68-71 */
+	{ SDE_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, SDE_INTR_HIST_VIG_1_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
+		SDE_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 68-71 */
+	{ SDE_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, SDE_INTR_HIST_VIG_2_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
+		SDE_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, SDE_INTR_HIST_VIG_3_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
+		SDE_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
+	/* irq_idx: 72-75 */
+	{ SDE_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, SDE_INTR_HIST_DSPP_0_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
+		SDE_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 76-79 */
+	{ SDE_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, SDE_INTR_HIST_DSPP_1_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
+		SDE_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 80-83 */
+	{ SDE_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, SDE_INTR_HIST_DSPP_2_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
+		SDE_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, SDE_INTR_HIST_DSPP_3_DONE, 2},
+	{ SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
+		SDE_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
+	/* irq_idx: 84-87 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 88-91 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	/* irq_idx: 92-95 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 2},
+
+	/* BEGIN MAP_RANGE: 96-127 INTF_0_INTR */
+	/* irq_idx: 96-99 */
+	{ SDE_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
+		SDE_INTR_VIDEO_INTO_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
+		SDE_INTR_VIDEO_OUTOF_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
+		SDE_INTR_DSICMD_0_INTO_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
+		SDE_INTR_DSICMD_0_OUTOF_STATIC, 3},
+	/* irq_idx: 100-103 */
+	{ SDE_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
+		SDE_INTR_DSICMD_1_INTO_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
+		SDE_INTR_DSICMD_1_OUTOF_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
+		SDE_INTR_DSICMD_2_INTO_STATIC, 3},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
+		SDE_INTR_DSICMD_2_OUTOF_STATIC, 3},
+	/* irq_idx: 104-107 */
+	{ SDE_IRQ_TYPE_PROG_LINE, INTF_0, SDE_INTR_PROG_LINE, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	/* irq_idx: 108-111 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	/* irq_idx: 112-115 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	/* irq_idx: 116-119 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	/* irq_idx: 120-123 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	/* irq_idx: 124-127 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 3},
+
+	/* BEGIN MAP_RANGE: 128-159 INTF_1_INTR */
+	/* irq_idx: 128-131 */
+	{ SDE_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
+		SDE_INTR_VIDEO_INTO_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
+		SDE_INTR_VIDEO_OUTOF_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
+		SDE_INTR_DSICMD_0_INTO_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
+		SDE_INTR_DSICMD_0_OUTOF_STATIC, 4},
+	/* irq_idx: 132-135 */
+	{ SDE_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
+		SDE_INTR_DSICMD_1_INTO_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
+		SDE_INTR_DSICMD_1_OUTOF_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
+		SDE_INTR_DSICMD_2_INTO_STATIC, 4},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
+		SDE_INTR_DSICMD_2_OUTOF_STATIC, 4},
+	/* irq_idx: 136-139 */
+	{ SDE_IRQ_TYPE_PROG_LINE, INTF_1, SDE_INTR_PROG_LINE, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	/* irq_idx: 140-143 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	/* irq_idx: 144-147 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	/* irq_idx: 148-151 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	/* irq_idx: 152-155 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	/* irq_idx: 156-159 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 4},
+
+	/* BEGIN MAP_RANGE: 160-191 INTF_2_INTR */
+	/* irq_idx: 160-163 */
+	{ SDE_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
+		SDE_INTR_VIDEO_INTO_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
+		SDE_INTR_VIDEO_OUTOF_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
+		SDE_INTR_DSICMD_0_INTO_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
+		SDE_INTR_DSICMD_0_OUTOF_STATIC, 5},
+	/* irq_idx: 164-167 */
+	{ SDE_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
+		SDE_INTR_DSICMD_1_INTO_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
+		SDE_INTR_DSICMD_1_OUTOF_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
+		SDE_INTR_DSICMD_2_INTO_STATIC, 5},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
+		SDE_INTR_DSICMD_2_OUTOF_STATIC, 5},
+	/* irq_idx: 168-171 */
+	{ SDE_IRQ_TYPE_PROG_LINE, INTF_2, SDE_INTR_PROG_LINE, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	/* irq_idx: 172-175 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	/* irq_idx: 176-179 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	/* irq_idx: 180-183 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	/* irq_idx: 184-187 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	/* irq_idx: 188-191 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 5},
+
+	/* BEGIN MAP_RANGE: 192-223 INTF_3_INTR */
+	/* irq_idx: 192-195 */
+	{ SDE_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
+		SDE_INTR_VIDEO_INTO_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
+		SDE_INTR_VIDEO_OUTOF_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
+		SDE_INTR_DSICMD_0_INTO_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
+		SDE_INTR_DSICMD_0_OUTOF_STATIC, 6},
+	/* irq_idx: 196-199 */
+	{ SDE_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
+		SDE_INTR_DSICMD_1_INTO_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
+		SDE_INTR_DSICMD_1_OUTOF_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
+		SDE_INTR_DSICMD_2_INTO_STATIC, 6},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
+		SDE_INTR_DSICMD_2_OUTOF_STATIC, 6},
+	/* irq_idx: 200-203 */
+	{ SDE_IRQ_TYPE_PROG_LINE, INTF_3, SDE_INTR_PROG_LINE, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	/* irq_idx: 204-207 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	/* irq_idx: 208-211 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	/* irq_idx: 212-215 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	/* irq_idx: 216-219 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	/* irq_idx: 220-223 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 6},
+
+	/* BEGIN MAP_RANGE: 224-255 INTF_4_INTR */
+	/* irq_idx: 224-227 */
+	{ SDE_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
+		SDE_INTR_VIDEO_INTO_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
+		SDE_INTR_VIDEO_OUTOF_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
+		SDE_INTR_DSICMD_0_INTO_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
+		SDE_INTR_DSICMD_0_OUTOF_STATIC, 7},
+	/* irq_idx: 228-231 */
+	{ SDE_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
+		SDE_INTR_DSICMD_1_INTO_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
+		SDE_INTR_DSICMD_1_OUTOF_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
+		SDE_INTR_DSICMD_2_INTO_STATIC, 7},
+	{ SDE_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
+		SDE_INTR_DSICMD_2_OUTOF_STATIC, 7},
+	/* irq_idx: 232-235 */
+	{ SDE_IRQ_TYPE_PROG_LINE, INTF_4, SDE_INTR_PROG_LINE, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	/* irq_idx: 236-239 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	/* irq_idx: 240-243 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	/* irq_idx: 244-247 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	/* irq_idx: 248-251 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	/* irq_idx: 252-255 */
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},
+};
+
+static int sde_hw_intr_irqidx_lookup(enum sde_intr_type intr_type,
+		u32 instance_idx)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sde_irq_map); i++) {
+		if (intr_type == sde_irq_map[i].intr_type &&
+			instance_idx == sde_irq_map[i].instance_idx)
+			return i;
+	}
+
+	pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
+			intr_type, instance_idx);
+	return -EINVAL;
+}
+
+static void sde_hw_intr_set_mask(struct sde_hw_intr *intr, uint32_t reg_off,
+		uint32_t mask)
+{
+	SDE_REG_WRITE(&intr->hw, reg_off, mask);
+}
+
+static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr,
+		void (*cbfunc)(void *, int),
+		void *arg)
+{
+	int reg_idx;
+	int irq_idx;
+	int start_idx;
+	int end_idx;
+	u32 irq_status;
+	unsigned long irq_flags;
+
+	/*
+	 * The dispatcher will save the IRQ status before calling here.
+	 * Now need to go through each IRQ status and find matching
+	 * irq lookup index.
+	 */
+	spin_lock_irqsave(&intr->status_lock, irq_flags);
+	for (reg_idx = 0; reg_idx < ARRAY_SIZE(sde_intr_set); reg_idx++) {
+		irq_status = intr->save_irq_status[reg_idx];
+
+		/*
+		 * Each Interrupt register has a range of 32 indexes, and
+		 * that is static for sde_irq_map.
+		 */
+		start_idx = reg_idx * 32;
+		end_idx = start_idx + 32;
+
+		/*
+		 * Search through matching intr status from irq map.
+		 * start_idx and end_idx defined the search range in
+		 * the sde_irq_map.
+		 */
+		for (irq_idx = start_idx;
+				(irq_idx < end_idx) && irq_status;
+				irq_idx++)
+			if ((irq_status & sde_irq_map[irq_idx].irq_mask) &&
+				(sde_irq_map[irq_idx].reg_idx == reg_idx)) {
+				/*
+				 * Once a match on irq mask, perform a callback
+				 * to the given cbfunc. cbfunc will take care
+				 * the interrupt status clearing. If cbfunc is
+				 * not provided, then the interrupt clearing
+				 * is here.
+				 */
+				if (cbfunc)
+					cbfunc(arg, irq_idx);
+				else
+					intr->ops.clear_interrupt_status(
+							intr, irq_idx);
+
+				/*
+				 * When callback finish, clear the irq_status
+				 * with the matching mask. Once irq_status
+				 * is all cleared, the search can be stopped.
+				 */
+				irq_status &= ~sde_irq_map[irq_idx].irq_mask;
+			}
+	}
+	spin_unlock_irqrestore(&intr->status_lock, irq_flags);
+}
+
+static int sde_hw_intr_enable_irq(struct sde_hw_intr *intr, int irq_idx)
+{
+	int reg_idx;
+	unsigned long irq_flags;
+	const struct sde_intr_reg *reg;
+	const struct sde_irq_type *irq;
+	const char *dbgstr = NULL;
+	uint32_t cache_irq_mask;
+
+	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(sde_irq_map)) {
+		pr_err("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	irq = &sde_irq_map[irq_idx];
+	reg_idx = irq->reg_idx;
+	reg = &sde_intr_set[reg_idx];
+
+	spin_lock_irqsave(&intr->mask_lock, irq_flags);
+	cache_irq_mask = intr->cache_irq_mask[reg_idx];
+	if (cache_irq_mask & irq->irq_mask) {
+		dbgstr = "SDE IRQ already set:";
+	} else {
+		dbgstr = "SDE IRQ enabled:";
+
+		cache_irq_mask |= irq->irq_mask;
+		/* Cleaning any pending interrupt */
+		SDE_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
+		/* Enabling interrupts with the new mask */
+		SDE_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
+
+		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
+	}
+	spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+
+	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
+			irq->irq_mask, cache_irq_mask);
+
+	return 0;
+}
+
+static int sde_hw_intr_disable_irq(struct sde_hw_intr *intr, int irq_idx)
+{
+	int reg_idx;
+	unsigned long irq_flags;
+	const struct sde_intr_reg *reg;
+	const struct sde_irq_type *irq;
+	const char *dbgstr = NULL;
+	uint32_t cache_irq_mask;
+
+	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(sde_irq_map)) {
+		pr_err("invalid IRQ index: [%d]\n", irq_idx);
+		return -EINVAL;
+	}
+
+	irq = &sde_irq_map[irq_idx];
+	reg_idx = irq->reg_idx;
+	reg = &sde_intr_set[reg_idx];
+
+	spin_lock_irqsave(&intr->mask_lock, irq_flags);
+	cache_irq_mask = intr->cache_irq_mask[reg_idx];
+	if ((cache_irq_mask & irq->irq_mask) == 0) {
+		dbgstr = "SDE IRQ is already cleared:";
+	} else {
+		dbgstr = "SDE IRQ mask disable:";
+
+		cache_irq_mask &= ~irq->irq_mask;
+		/* Disable interrupts based on the new mask */
+		SDE_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
+		/* Cleaning any pending interrupt */
+		SDE_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
+
+		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
+	}
+	spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+
+	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
+			irq->irq_mask, cache_irq_mask);
+
+	return 0;
+}
+
+static int sde_hw_intr_clear_irqs(struct sde_hw_intr *intr)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
+		SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off, 0xffffffff);
+
+	return 0;
+}
+
+static int sde_hw_intr_disable_irqs(struct sde_hw_intr *intr)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
+		SDE_REG_WRITE(&intr->hw, sde_intr_set[i].en_off, 0x00000000);
+
+	return 0;
+}
+
+static int sde_hw_intr_get_valid_interrupts(struct sde_hw_intr *intr,
+		uint32_t *mask)
+{
+	*mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
+		| IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
+	return 0;
+}
+
+static int sde_hw_intr_get_interrupt_sources(struct sde_hw_intr *intr,
+		uint32_t *sources)
+{
+	*sources = SDE_REG_READ(&intr->hw, HW_INTR_STATUS);
+	return 0;
+}
+
+static void sde_hw_intr_get_interrupt_statuses(struct sde_hw_intr *intr)
+{
+	int i;
+	u32 enable_mask;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&intr->status_lock, irq_flags);
+	for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) {
+		/* Read interrupt status */
+		intr->save_irq_status[i] = SDE_REG_READ(&intr->hw,
+				sde_intr_set[i].status_off);
+
+		/* Read enable mask */
+		enable_mask = SDE_REG_READ(&intr->hw, sde_intr_set[i].en_off);
+
+		/* and clear the interrupt */
+		if (intr->save_irq_status[i])
+			SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off,
+					intr->save_irq_status[i]);
+
+		/* Finally update IRQ status based on enable mask */
+		intr->save_irq_status[i] &= enable_mask;
+	}
+	spin_unlock_irqrestore(&intr->status_lock, irq_flags);
+}
+
+static void sde_hw_intr_clear_interrupt_status(struct sde_hw_intr *intr,
+		int irq_idx)
+{
+	int reg_idx;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&intr->mask_lock, irq_flags);
+
+	reg_idx = sde_irq_map[irq_idx].reg_idx;
+	SDE_REG_WRITE(&intr->hw, sde_intr_set[reg_idx].clr_off,
+			sde_irq_map[irq_idx].irq_mask);
+
+	spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+}
+
+static u32 sde_hw_intr_get_interrupt_status(struct sde_hw_intr *intr,
+		int irq_idx, bool clear)
+{
+	int reg_idx;
+	unsigned long irq_flags;
+	u32 intr_status;
+
+	spin_lock_irqsave(&intr->mask_lock, irq_flags);
+
+	reg_idx = sde_irq_map[irq_idx].reg_idx;
+	intr_status = SDE_REG_READ(&intr->hw,
+			sde_intr_set[reg_idx].status_off) &
+					sde_irq_map[irq_idx].irq_mask;
+	if (intr_status && clear)
+		SDE_REG_WRITE(&intr->hw, sde_intr_set[irq_idx].clr_off,
+				intr_status);
+
+	spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+
+	return intr_status;
+}
+
+static void __setup_intr_ops(struct sde_hw_intr_ops *ops)
+{
+	ops->set_mask = sde_hw_intr_set_mask;
+	ops->irq_idx_lookup = sde_hw_intr_irqidx_lookup;
+	ops->enable_irq = sde_hw_intr_enable_irq;
+	ops->disable_irq = sde_hw_intr_disable_irq;
+	ops->dispatch_irqs = sde_hw_intr_dispatch_irq;
+	ops->clear_all_irqs = sde_hw_intr_clear_irqs;
+	ops->disable_all_irqs = sde_hw_intr_disable_irqs;
+	ops->get_valid_interrupts = sde_hw_intr_get_valid_interrupts;
+	ops->get_interrupt_sources = sde_hw_intr_get_interrupt_sources;
+	ops->get_interrupt_statuses = sde_hw_intr_get_interrupt_statuses;
+	ops->clear_interrupt_status = sde_hw_intr_clear_interrupt_status;
+	ops->get_interrupt_status = sde_hw_intr_get_interrupt_status;
+}
+
+static struct sde_mdss_base_cfg *__intr_offset(struct sde_mdss_cfg *m,
+		void __iomem *addr, struct sde_hw_blk_reg_map *hw)
+{
+	if (m->mdp_count == 0)
+		return NULL;
+
+	hw->base_off = addr;
+	hw->blk_off = m->mdss[0].base;
+	hw->hwversion = m->hwversion;
+	return &m->mdss[0];
+}
+
+struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr,
+		struct sde_mdss_cfg *m)
+{
+	struct sde_hw_intr *intr = kzalloc(sizeof(*intr), GFP_KERNEL);
+	struct sde_mdss_base_cfg *cfg;
+
+	if (!intr)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = __intr_offset(m, addr, &intr->hw);
+	if (!cfg) {
+		kfree(intr);
+		return ERR_PTR(-EINVAL);
+	}
+	__setup_intr_ops(&intr->ops);
+
+	intr->irq_idx_tbl_size = ARRAY_SIZE(sde_irq_map);
+
+	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(sde_intr_set), sizeof(u32),
+			GFP_KERNEL);
+	if (intr->cache_irq_mask == NULL) {
+		kfree(intr);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	intr->save_irq_status = kcalloc(ARRAY_SIZE(sde_intr_set), sizeof(u32),
+			GFP_KERNEL);
+	if (intr->save_irq_status == NULL) {
+		kfree(intr->cache_irq_mask);
+		kfree(intr);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	spin_lock_init(&intr->mask_lock);
+	spin_lock_init(&intr->status_lock);
+
+	return intr;
+}
+
+void sde_hw_intr_destroy(struct sde_hw_intr *intr)
+{
+	if (intr) {
+		kfree(intr->cache_irq_mask);
+		kfree(intr->save_irq_status);
+		kfree(intr);
+	}
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
new file mode 100644
index 0000000000000000000000000000000000000000..261ef64c0065f645f8bb08d21b3c539e046393d5
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
@@ -0,0 +1,257 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_INTERRUPTS_H
+#define _SDE_HW_INTERRUPTS_H
+
+#include <linux/types.h>
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_util.h"
+#include "sde_hw_mdss.h"
+
+#define IRQ_SOURCE_MDP		BIT(0)
+#define IRQ_SOURCE_DSI0		BIT(4)
+#define IRQ_SOURCE_DSI1		BIT(5)
+#define IRQ_SOURCE_HDMI		BIT(8)
+#define IRQ_SOURCE_EDP		BIT(12)
+#define	IRQ_SOURCE_MHL		BIT(16)
+
+/**
+ * sde_intr_type - HW Interrupt Type
+ * @SDE_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
+ * @SDE_IRQ_TYPE_WB_WFD_COMP:		WB WFD done
+ * @SDE_IRQ_TYPE_PING_PONG_COMP:	PingPong done
+ * @SDE_IRQ_TYPE_PING_PONG_RD_PTR:	PingPong read pointer
+ * @SDE_IRQ_TYPE_PING_PONG_WR_PTR:	PingPong write pointer
+ * @SDE_IRQ_TYPE_PING_PONG_AUTO_REF:	PingPong auto refresh
+ * @SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK:	PingPong Tear check
+ * @SDE_IRQ_TYPE_PING_PONG_TE_CHECK:	PingPong TE detection
+ * @SDE_IRQ_TYPE_INTF_UNDER_RUN:	INTF underrun
+ * @SDE_IRQ_TYPE_INTF_VSYNC:		INTF VSYNC
+ * @SDE_IRQ_TYPE_CWB_OVERFLOW:		Concurrent WB overflow
+ * @SDE_IRQ_TYPE_HIST_VIG_DONE:		VIG Histogram done
+ * @SDE_IRQ_TYPE_HIST_VIG_RSTSEQ:	VIG Histogram reset
+ * @SDE_IRQ_TYPE_HIST_DSPP_DONE:	DSPP Histogram done
+ * @SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ:	DSPP Histogram reset
+ * @SDE_IRQ_TYPE_WD_TIMER:		Watchdog timer
+ * @SDE_IRQ_TYPE_SFI_VIDEO_IN:		Video static frame INTR into static
+ * @SDE_IRQ_TYPE_SFI_VIDEO_OUT:		Video static frame INTR out-of static
+ * @SDE_IRQ_TYPE_SFI_CMD_0_IN:		DSI CMD0 static frame INTR into static
+ * @SDE_IRQ_TYPE_SFI_CMD_0_OUT:		DSI CMD0 static frame INTR out-of static
+ * @SDE_IRQ_TYPE_SFI_CMD_1_IN:		DSI CMD1 static frame INTR into static
+ * @SDE_IRQ_TYPE_SFI_CMD_1_OUT:		DSI CMD1 static frame INTR out-of static
+ * @SDE_IRQ_TYPE_SFI_CMD_2_IN:		DSI CMD2 static frame INTR into static
+ * @SDE_IRQ_TYPE_SFI_CMD_2_OUT:		DSI CMD2 static frame INTR out-of static
+ * @SDE_IRQ_TYPE_PROG_LINE:		Programmable Line interrupt
+ * @SDE_IRQ_TYPE_RESERVED:		Reserved for expansion
+ */
+enum sde_intr_type {
+	SDE_IRQ_TYPE_WB_ROT_COMP,
+	SDE_IRQ_TYPE_WB_WFD_COMP,
+	SDE_IRQ_TYPE_PING_PONG_COMP,
+	SDE_IRQ_TYPE_PING_PONG_RD_PTR,
+	SDE_IRQ_TYPE_PING_PONG_WR_PTR,
+	SDE_IRQ_TYPE_PING_PONG_AUTO_REF,
+	SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK,
+	SDE_IRQ_TYPE_PING_PONG_TE_CHECK,
+	SDE_IRQ_TYPE_INTF_UNDER_RUN,
+	SDE_IRQ_TYPE_INTF_VSYNC,
+	SDE_IRQ_TYPE_CWB_OVERFLOW,
+	SDE_IRQ_TYPE_HIST_VIG_DONE,
+	SDE_IRQ_TYPE_HIST_VIG_RSTSEQ,
+	SDE_IRQ_TYPE_HIST_DSPP_DONE,
+	SDE_IRQ_TYPE_HIST_DSPP_RSTSEQ,
+	SDE_IRQ_TYPE_WD_TIMER,
+	SDE_IRQ_TYPE_SFI_VIDEO_IN,
+	SDE_IRQ_TYPE_SFI_VIDEO_OUT,
+	SDE_IRQ_TYPE_SFI_CMD_0_IN,
+	SDE_IRQ_TYPE_SFI_CMD_0_OUT,
+	SDE_IRQ_TYPE_SFI_CMD_1_IN,
+	SDE_IRQ_TYPE_SFI_CMD_1_OUT,
+	SDE_IRQ_TYPE_SFI_CMD_2_IN,
+	SDE_IRQ_TYPE_SFI_CMD_2_OUT,
+	SDE_IRQ_TYPE_PROG_LINE,
+	SDE_IRQ_TYPE_RESERVED,
+};
+
+struct sde_hw_intr;
+
+/**
+ * Interrupt operations.
+ */
+struct sde_hw_intr_ops {
+	/**
+	 * set_mask - Programs the given interrupt register with the
+	 *            given interrupt mask. Register value will get overwritten.
+	 * @intr:	HW interrupt handle
+	 * @reg_off:	MDSS HW register offset
+	 * @irqmask:	IRQ mask value
+	 */
+	void (*set_mask)(
+			struct sde_hw_intr *intr,
+			uint32_t reg,
+			uint32_t irqmask);
+
+	/**
+	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
+	 *                 Used for all irq related ops
+	 * @intr_type:		Interrupt type defined in sde_intr_type
+	 * @instance_idx:	HW interrupt block instance
+	 * @return:		irq_idx or -EINVAL for lookup fail
+	 */
+	int (*irq_idx_lookup)(
+			enum sde_intr_type intr_type,
+			u32 instance_idx);
+
+	/**
+	 * enable_irq - Enable IRQ based on lookup IRQ index
+	 * @intr:	HW interrupt handle
+	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*enable_irq)(
+			struct sde_hw_intr *intr,
+			int irq_idx);
+
+	/**
+	 * disable_irq - Disable IRQ based on lookup IRQ index
+	 * @intr:	HW interrupt handle
+	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*disable_irq)(
+			struct sde_hw_intr *intr,
+			int irq_idx);
+
+	/**
+	 * clear_all_irqs - Clears all the interrupts (i.e. acknowledges
+	 *                  any asserted IRQs). Useful during reset.
+	 * @intr:	HW interrupt handle
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*clear_all_irqs)(
+			struct sde_hw_intr *intr);
+
+	/**
+	 * disable_all_irqs - Disables all the interrupts. Useful during reset.
+	 * @intr:	HW interrupt handle
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*disable_all_irqs)(
+			struct sde_hw_intr *intr);
+
+	/**
+	 * dispatch_irqs - IRQ dispatcher will call the given callback
+	 *                 function when a matching interrupt status bit is
+	 *                 found in the irq mapping table.
+	 * @intr:	HW interrupt handle
+	 * @cbfunc:	Callback function pointer
+	 * @arg:	Argument to pass back during callback
+	 */
+	void (*dispatch_irqs)(
+			struct sde_hw_intr *intr,
+			void (*cbfunc)(void *arg, int irq_idx),
+			void *arg);
+
+	/**
+	 * get_interrupt_statuses - Gets and store value from all interrupt
+	 *                          status registers that are currently fired.
+	 * @intr:	HW interrupt handle
+	 */
+	void (*get_interrupt_statuses)(
+			struct sde_hw_intr *intr);
+
+	/**
+	 * clear_interrupt_status - Clears HW interrupt status based on given
+	 *                          lookup IRQ index.
+	 * @intr:	HW interrupt handle
+	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
+	 */
+	void (*clear_interrupt_status)(
+			struct sde_hw_intr *intr,
+			int irq_idx);
+
+	/**
+	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
+	 *                        based on given lookup IRQ index.
+	 * @intr:	HW interrupt handle
+	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
+	 * @clear:	True to clear irq after read
+	 */
+	u32 (*get_interrupt_status)(
+			struct sde_hw_intr *intr,
+			int irq_idx,
+			bool clear);
+
+	/**
+	 * get_valid_interrupts - Gets a mask of all valid interrupt sources
+	 *                        within SDE. These are actually status bits
+	 *                        within interrupt registers that specify the
+	 *                        source of the interrupt in IRQs. For example,
+	 *                        valid interrupt sources can be MDP, DSI,
+	 *                        HDMI etc.
+	 * @intr:	HW interrupt handle
+	 * @mask:	Returning the interrupt source MASK
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*get_valid_interrupts)(
+			struct sde_hw_intr *intr,
+			uint32_t *mask);
+
+	/**
+	 * get_interrupt_sources - Gets the bitmask of the SDE interrupt
+	 *                         source that are currently fired.
+	 * @intr:	HW interrupt handle
+	 * @sources:	Returning the SDE interrupt source status bit mask
+	 * @return:	0 for success, otherwise failure
+	 */
+	int (*get_interrupt_sources)(
+			struct sde_hw_intr *intr,
+			uint32_t *sources);
+};
+
+/**
+ * struct sde_hw_intr: hw interrupts handling data structure
+ * @hw:               virtual address mapping
+ * @ops:              function pointer mapping for IRQ handling
+ * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
+ * @save_irq_status:  array of IRQ status reg storage created during init
+ * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
+ * @mask_lock:        spinlock for accessing IRQ mask
+ * @status_lock:      spinlock for accessing IRQ status
+ */
+struct sde_hw_intr {
+	struct sde_hw_blk_reg_map hw;
+	struct sde_hw_intr_ops ops;
+	u32 *cache_irq_mask;
+	u32 *save_irq_status;
+	u32 irq_idx_tbl_size;
+	spinlock_t mask_lock;
+	spinlock_t status_lock;
+};
+
+/**
+ * sde_hw_intr_init(): Initializes the interrupts hw object
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ */
+struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr,
+		struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_intr_destroy(): Cleanup interrutps hw object
+ * @intr: pointer to interrupts hw object
+ */
+void sde_hw_intr_destroy(struct sde_hw_intr *intr);
+#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_intf.c b/drivers/gpu/drm/msm/sde/sde_hw_intf.c
new file mode 100644
index 0000000000000000000000000000000000000000..3b34719e9971f0371295a884843f0961e50c1dc8
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_intf.c
@@ -0,0 +1,342 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_intf.h"
+
+#define INTF_TIMING_ENGINE_EN           0x000
+#define INTF_CONFIG                     0x004
+#define INTF_HSYNC_CTL                  0x008
+#define INTF_VSYNC_PERIOD_F0            0x00C
+#define INTF_VSYNC_PERIOD_F1            0x010
+#define INTF_VSYNC_PULSE_WIDTH_F0       0x014
+#define INTF_VSYNC_PULSE_WIDTH_F1       0x018
+#define INTF_DISPLAY_V_START_F0         0x01C
+#define INTF_DISPLAY_V_START_F1         0x020
+#define INTF_DISPLAY_V_END_F0           0x024
+#define INTF_DISPLAY_V_END_F1           0x028
+#define INTF_ACTIVE_V_START_F0          0x02C
+#define INTF_ACTIVE_V_START_F1          0x030
+#define INTF_ACTIVE_V_END_F0            0x034
+#define INTF_ACTIVE_V_END_F1            0x038
+#define INTF_DISPLAY_HCTL               0x03C
+#define INTF_ACTIVE_HCTL                0x040
+#define INTF_BORDER_COLOR               0x044
+#define INTF_UNDERFLOW_COLOR            0x048
+#define INTF_HSYNC_SKEW                 0x04C
+#define INTF_POLARITY_CTL               0x050
+#define INTF_TEST_CTL                   0x054
+#define INTF_TP_COLOR0                  0x058
+#define INTF_TP_COLOR1                  0x05C
+#define INTF_FRAME_LINE_COUNT_EN        0x0A8
+#define INTF_FRAME_COUNT                0x0AC
+#define   INTF_LINE_COUNT               0x0B0
+
+#define   INTF_DEFLICKER_CONFIG         0x0F0
+#define   INTF_DEFLICKER_STRNG_COEFF    0x0F4
+#define   INTF_DEFLICKER_WEAK_COEFF     0x0F8
+
+#define   INTF_DSI_CMD_MODE_TRIGGER_EN  0x084
+#define   INTF_PANEL_FORMAT             0x090
+#define   INTF_TPG_ENABLE               0x100
+#define   INTF_TPG_MAIN_CONTROL         0x104
+#define   INTF_TPG_VIDEO_CONFIG         0x108
+#define   INTF_TPG_COMPONENT_LIMITS     0x10C
+#define   INTF_TPG_RECTANGLE            0x110
+#define   INTF_TPG_INITIAL_VALUE        0x114
+#define   INTF_TPG_BLK_WHITE_PATTERN_FRAMES   0x118
+#define   INTF_TPG_RGB_MAPPING          0x11C
+#define   INTF_PROG_FETCH_START         0x170
+
+#define   INTF_FRAME_LINE_COUNT_EN      0x0A8
+#define   INTF_FRAME_COUNT              0x0AC
+#define   INTF_LINE_COUNT               0x0B0
+
+#define INTF_MISR_CTRL			0x180
+#define INTF_MISR_SIGNATURE		0x184
+
+#define MISR_FRAME_COUNT_MASK		0xFF
+#define MISR_CTRL_ENABLE		BIT(8)
+#define MISR_CTRL_STATUS		BIT(9)
+#define MISR_CTRL_STATUS_CLEAR		BIT(10)
+#define INTF_MISR_CTRL_FREE_RUN_MASK	BIT(31)
+
+static struct sde_intf_cfg *_intf_offset(enum sde_intf intf,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->intf_count; i++) {
+		if ((intf == m->intf[i].id) &&
+		(m->intf[i].type != INTF_NONE)) {
+			b->base_off = addr;
+			b->blk_off = m->intf[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_INTF;
+			return &m->intf[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
+		const struct intf_timing_params *p,
+		const struct sde_format *fmt)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 hsync_period, vsync_period;
+	u32 display_v_start, display_v_end;
+	u32 hsync_start_x, hsync_end_x;
+	u32 active_h_start, active_h_end;
+	u32 active_v_start, active_v_end;
+	u32 active_hctl, display_hctl, hsync_ctl;
+	u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
+	u32 panel_format;
+	u32 intf_cfg;
+
+	/* read interface_cfg */
+	intf_cfg = SDE_REG_READ(c, INTF_CONFIG);
+	hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
+	p->h_front_porch;
+	vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
+	p->v_front_porch;
+
+	display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
+	hsync_period) + p->hsync_skew;
+	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
+	p->hsync_skew - 1;
+
+	if (ctx->cap->type == INTF_EDP) {
+		display_v_start += p->hsync_pulse_width + p->h_back_porch;
+		display_v_end -= p->h_front_porch;
+	}
+
+	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
+	hsync_end_x = hsync_period - p->h_front_porch - 1;
+
+	if (p->width != p->xres) {
+		active_h_start = hsync_start_x;
+		active_h_end = active_h_start + p->xres - 1;
+	} else {
+		active_h_start = 0;
+		active_h_end = 0;
+	}
+
+	if (p->height != p->yres) {
+		active_v_start = display_v_start;
+		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
+	} else {
+		active_v_start = 0;
+		active_v_end = 0;
+	}
+
+	if (active_h_end) {
+		active_hctl = (active_h_end << 16) | active_h_start;
+		intf_cfg |= BIT(29);	/* ACTIVE_H_ENABLE */
+	} else {
+		active_hctl = 0;
+	}
+
+	if (active_v_end)
+		intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
+
+	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
+	display_hctl = (hsync_end_x << 16) | hsync_start_x;
+
+	den_polarity = 0;
+	if (ctx->cap->type == INTF_HDMI) {
+		hsync_polarity = p->yres >= 720 ? 0 : 1;
+		vsync_polarity = p->yres >= 720 ? 0 : 1;
+	} else {
+		hsync_polarity = 0;
+		vsync_polarity = 0;
+	}
+	polarity_ctl = (den_polarity << 2) | /*  DEN Polarity  */
+		(vsync_polarity << 1) | /* VSYNC Polarity */
+		(hsync_polarity << 0);  /* HSYNC Polarity */
+
+	if (!SDE_FORMAT_IS_YUV(fmt))
+		panel_format = (fmt->bits[C0_G_Y] |
+				(fmt->bits[C1_B_Cb] << 2) |
+				(fmt->bits[C2_R_Cr] << 4) |
+				(0x21 << 8));
+	 else
+		/* Interface treats all the pixel data in RGB888 format */
+		panel_format = (COLOR_8BIT |
+				(COLOR_8BIT << 2) |
+				(COLOR_8BIT << 4) |
+				(0x21 << 8));
+
+	SDE_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
+	SDE_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
+	SDE_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
+			p->vsync_pulse_width * hsync_period);
+	SDE_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
+	SDE_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
+	SDE_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
+	SDE_REG_WRITE(c, INTF_ACTIVE_HCTL,  active_hctl);
+	SDE_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
+	SDE_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
+	SDE_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
+	SDE_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
+	SDE_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
+	SDE_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
+	SDE_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
+	SDE_REG_WRITE(c, INTF_CONFIG, intf_cfg);
+	SDE_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
+}
+
+static void sde_hw_intf_enable_timing_engine(
+		struct sde_hw_intf *intf,
+		u8 enable)
+{
+	struct sde_hw_blk_reg_map *c = &intf->hw;
+	/* Note: Display interface select is handled in top block hw layer */
+	SDE_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
+}
+
+static void sde_hw_intf_setup_prg_fetch(
+		struct sde_hw_intf *intf,
+		const struct intf_prog_fetch *fetch)
+{
+	struct sde_hw_blk_reg_map *c = &intf->hw;
+	int fetch_enable;
+
+	/*
+	 * Fetch should always be outside the active lines. If the fetching
+	 * is programmed within active region, hardware behavior is unknown.
+	 */
+
+	fetch_enable = SDE_REG_READ(c, INTF_CONFIG);
+	if (fetch->enable) {
+		fetch_enable |= BIT(31);
+		SDE_REG_WRITE(c, INTF_PROG_FETCH_START,
+				fetch->fetch_start);
+	} else {
+		fetch_enable &= ~BIT(31);
+	}
+
+	SDE_REG_WRITE(c, INTF_CONFIG, fetch_enable);
+}
+
+static void sde_hw_intf_get_status(
+		struct sde_hw_intf *intf,
+		struct intf_status *s)
+{
+	struct sde_hw_blk_reg_map *c = &intf->hw;
+
+	s->is_en = SDE_REG_READ(c, INTF_TIMING_ENGINE_EN);
+	if (s->is_en) {
+		s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
+		s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT);
+	} else {
+		s->line_count = 0;
+		s->frame_count = 0;
+	}
+}
+
+static void sde_hw_intf_set_misr(struct sde_hw_intf *intf,
+		struct sde_misr_params *misr_map)
+{
+	struct sde_hw_blk_reg_map *c = &intf->hw;
+	u32 config = 0;
+
+	if (!misr_map)
+		return;
+
+	SDE_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
+	/* Clear data */
+	wmb();
+
+	if (misr_map->enable) {
+		config = (MISR_FRAME_COUNT_MASK & 1) |
+			(MISR_CTRL_ENABLE);
+
+		SDE_REG_WRITE(c, INTF_MISR_CTRL, config);
+	} else {
+		SDE_REG_WRITE(c, INTF_MISR_CTRL, 0);
+	}
+}
+
+static void sde_hw_intf_collect_misr(struct sde_hw_intf *intf,
+		struct sde_misr_params *misr_map)
+{
+	struct sde_hw_blk_reg_map *c = &intf->hw;
+
+	if (!misr_map)
+		return;
+
+	if (misr_map->enable) {
+		if (misr_map->last_idx < misr_map->frame_count &&
+			misr_map->last_idx < SDE_CRC_BATCH_SIZE)
+			misr_map->crc_value[misr_map->last_idx] =
+				SDE_REG_READ(c, INTF_MISR_SIGNATURE);
+	}
+
+	misr_map->enable =
+		misr_map->enable & (misr_map->last_idx <= SDE_CRC_BATCH_SIZE);
+
+	misr_map->last_idx++;
+}
+
+static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
+		unsigned long cap)
+{
+	ops->setup_timing_gen = sde_hw_intf_setup_timing_engine;
+	ops->setup_prg_fetch  = sde_hw_intf_setup_prg_fetch;
+	ops->get_status = sde_hw_intf_get_status;
+	ops->enable_timing = sde_hw_intf_enable_timing_engine;
+	ops->setup_misr = sde_hw_intf_set_misr;
+	ops->collect_misr = sde_hw_intf_collect_misr;
+}
+
+struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m)
+{
+	struct sde_hw_intf *c;
+	struct sde_intf_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _intf_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		pr_err("failed to create sde_hw_intf %d\n", idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/*
+	 * Assign ops
+	 */
+	c->idx = idx;
+	c->cap = cfg;
+	c->mdss = m;
+	_setup_intf_ops(&c->ops, c->cap->features);
+
+	/*
+	 * Perform any default initialization for the intf
+	 */
+	return c;
+}
+
+void sde_hw_intf_destroy(struct sde_hw_intf *intf)
+{
+	kfree(intf);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_intf.h b/drivers/gpu/drm/msm/sde/sde_hw_intf.h
new file mode 100644
index 0000000000000000000000000000000000000000..f4a01cb64d7f1d994d357279e43d8a7634f5e580
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_intf.h
@@ -0,0 +1,133 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_INTF_H
+#define _SDE_HW_INTF_H
+
+#include "sde_hw_catalog.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+
+struct sde_hw_intf;
+
+/* Batch size of frames for collecting MISR data */
+#define SDE_CRC_BATCH_SIZE 16
+
+/**
+ * struct sde_misr_params : Interface for getting and setting MISR data
+ *  Assumption is these functions will be called after clocks are enabled
+ * @ enable : enables/disables MISR
+ * @ frame_count : represents number of frames for which MISR is enabled
+ * @ last_idx: number of frames for which MISR data is collected
+ * @ crc_value: stores the collected MISR data
+ */
+struct sde_misr_params {
+	bool enable;
+	u32 frame_count;
+	u32 last_idx;
+	u32 crc_value[SDE_CRC_BATCH_SIZE];
+};
+
+/* intf timing settings */
+struct intf_timing_params {
+	u32 width;		/* active width */
+	u32 height;		/* active height */
+	u32 xres;		/* Display panel width */
+	u32 yres;		/* Display panel height */
+
+	u32 h_back_porch;
+	u32 h_front_porch;
+	u32 v_back_porch;
+	u32 v_front_porch;
+	u32 hsync_pulse_width;
+	u32 vsync_pulse_width;
+	u32 hsync_polarity;
+	u32 vsync_polarity;
+	u32 border_clr;
+	u32 underflow_clr;
+	u32 hsync_skew;
+};
+
+struct intf_prog_fetch {
+	u8 enable;
+	/* vsync counter for the front porch pixel line */
+	u32 fetch_start;
+};
+
+struct intf_status {
+	u8 is_en;		/* interface timing engine is enabled or not */
+	u32 frame_count;	/* frame count since timing engine enabled */
+	u32 line_count;		/* current line count including blanking */
+};
+
+/**
+ * struct sde_hw_intf_ops : Interface to the interface Hw driver functions
+ *  Assumption is these functions will be called after clocks are enabled
+ * @ setup_timing_gen : programs the timing engine
+ * @ setup_prog_fetch : enables/disables the programmable fetch logic
+ * @ enable_timing: enable/disable timing engine
+ * @ get_status: returns if timing engine is enabled or not
+ * @ setup_misr: enables/disables MISR in HW register
+ * @ collect_misr: reads and stores MISR data from HW register
+ */
+struct sde_hw_intf_ops {
+	void (*setup_timing_gen)(struct sde_hw_intf *intf,
+			const struct intf_timing_params *p,
+			const struct sde_format *fmt);
+
+	void (*setup_prg_fetch)(struct sde_hw_intf *intf,
+			const struct intf_prog_fetch *fetch);
+
+	void (*enable_timing)(struct sde_hw_intf *intf,
+			u8 enable);
+
+	void (*get_status)(struct sde_hw_intf *intf,
+			struct intf_status *status);
+
+	void (*setup_misr)(struct sde_hw_intf *intf,
+			struct sde_misr_params *misr_map);
+
+	void (*collect_misr)(struct sde_hw_intf *intf,
+			struct sde_misr_params *misr_map);
+};
+
+struct sde_hw_intf {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* intf */
+	enum sde_intf idx;
+	const struct sde_intf_cfg *cap;
+	const struct sde_mdss_cfg *mdss;
+
+	/* ops */
+	struct sde_hw_intf_ops ops;
+};
+
+/**
+ * sde_hw_intf_init(): Initializes the intf driver for the passed
+ * interface idx.
+ * @idx:  interface index for which driver object is required
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ */
+struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_intf_destroy(): Destroys INTF driver context
+ * @intf:   Pointer to INTF driver context
+ */
+void sde_hw_intf_destroy(struct sde_hw_intf *intf);
+
+#endif /*_SDE_HW_INTF_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_lm.c b/drivers/gpu/drm/msm/sde/sde_hw_lm.c
new file mode 100644
index 0000000000000000000000000000000000000000..365b9b17715de885ca47bc57781ec202050b3516
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_lm.c
@@ -0,0 +1,207 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_catalog.h"
+#include "sde_hwio.h"
+#include "sde_hw_lm.h"
+#include "sde_hw_mdss.h"
+
+#define LM_OP_MODE                        0x00
+#define LM_OUT_SIZE                       0x04
+#define LM_BORDER_COLOR_0                 0x08
+#define LM_BORDER_COLOR_1                 0x010
+
+/* These register are offset to mixer base + stage base */
+#define LM_BLEND0_OP                     0x00
+#define LM_BLEND0_CONST_ALPHA            0x04
+#define LM_BLEND0_FG_ALPHA               0x04
+#define LM_BLEND0_BG_ALPHA               0x08
+
+static struct sde_lm_cfg *_lm_offset(enum sde_lm mixer,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->mixer_count; i++) {
+		if (mixer == m->mixer[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->mixer[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_LM;
+			return &m->mixer[i];
+		}
+	}
+
+	return ERR_PTR(-ENOMEM);
+}
+
+/**
+ * _stage_offset(): returns the relative offset of the blend registers
+ * for the stage to be setup
+ * @c:     mixer ctx contains the mixer to be programmed
+ * @stage: stage index to setup
+ */
+static inline int _stage_offset(struct sde_hw_mixer *ctx, enum sde_stage stage)
+{
+	const struct sde_lm_sub_blks *sblk = ctx->cap->sblk;
+	int rc;
+
+	if (stage == SDE_STAGE_BASE)
+		rc = -EINVAL;
+	else if (stage <= sblk->maxblendstages)
+		rc = sblk->blendstage_base[stage - 1];
+	else
+		rc = -EINVAL;
+
+	return rc;
+}
+
+static void sde_hw_lm_setup_out(struct sde_hw_mixer *ctx,
+		struct sde_hw_mixer_cfg *mixer)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 outsize;
+	u32 op_mode;
+
+	op_mode = SDE_REG_READ(c, LM_OP_MODE);
+
+	outsize = mixer->out_height << 16 | mixer->out_width;
+	SDE_REG_WRITE(c, LM_OUT_SIZE, outsize);
+
+	/* SPLIT_LEFT_RIGHT */
+	if (mixer->right_mixer)
+		op_mode |= BIT(31);
+	else
+		op_mode &= ~BIT(31);
+	SDE_REG_WRITE(c, LM_OP_MODE, op_mode);
+}
+
+static void sde_hw_lm_setup_border_color(struct sde_hw_mixer *ctx,
+		struct sde_mdss_color *color,
+		u8 border_en)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+
+	if (border_en) {
+		SDE_REG_WRITE(c, LM_BORDER_COLOR_0,
+			(color->color_0 & 0xFFF) |
+			((color->color_1 & 0xFFF) << 0x10));
+		SDE_REG_WRITE(c, LM_BORDER_COLOR_1,
+			(color->color_2 & 0xFFF) |
+			((color->color_3 & 0xFFF) << 0x10));
+	}
+}
+
+static void sde_hw_lm_setup_blend_config_msmskunk(struct sde_hw_mixer *ctx,
+	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	int stage_off;
+	u32 const_alpha;
+
+	if (stage == SDE_STAGE_BASE)
+		return;
+
+	stage_off = _stage_offset(ctx, stage);
+	if (WARN_ON(stage_off < 0))
+		return;
+
+	const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
+	SDE_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
+	SDE_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
+}
+
+static void sde_hw_lm_setup_blend_config(struct sde_hw_mixer *ctx,
+	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	int stage_off;
+
+	if (stage == SDE_STAGE_BASE)
+		return;
+
+	stage_off = _stage_offset(ctx, stage);
+	if (WARN_ON(stage_off < 0))
+		return;
+
+	SDE_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
+	SDE_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
+	SDE_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
+}
+
+static void sde_hw_lm_setup_color3(struct sde_hw_mixer *ctx,
+	uint32_t mixer_op_mode)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	int op_mode;
+
+	/* read the existing op_mode configuration */
+	op_mode = SDE_REG_READ(c, LM_OP_MODE);
+
+	op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
+
+	SDE_REG_WRITE(c, LM_OP_MODE, op_mode);
+}
+
+static void sde_hw_lm_gc(struct sde_hw_mixer *mixer,
+			void *cfg)
+{
+}
+
+static void _setup_mixer_ops(struct sde_mdss_cfg *m,
+		struct sde_hw_lm_ops *ops,
+		unsigned long cap)
+{
+	ops->setup_mixer_out = sde_hw_lm_setup_out;
+	if (IS_MSMSKUNK_TARGET(m->hwversion))
+		ops->setup_blend_config = sde_hw_lm_setup_blend_config_msmskunk;
+	else
+		ops->setup_blend_config = sde_hw_lm_setup_blend_config;
+	ops->setup_alpha_out = sde_hw_lm_setup_color3;
+	ops->setup_border_color = sde_hw_lm_setup_border_color;
+	ops->setup_gc = sde_hw_lm_gc;
+};
+
+struct sde_hw_mixer *sde_hw_lm_init(enum sde_lm idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m)
+{
+	struct sde_hw_mixer *c;
+	struct sde_lm_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _lm_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Assign ops */
+	c->idx = idx;
+	c->cap = cfg;
+	_setup_mixer_ops(m, &c->ops, c->cap->features);
+
+	/*
+	 * Perform any default initialization for the sspp blocks
+	 */
+	return c;
+}
+
+void sde_hw_lm_destroy(struct sde_hw_mixer *lm)
+{
+	kfree(lm);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_lm.h b/drivers/gpu/drm/msm/sde/sde_hw_lm.h
new file mode 100644
index 0000000000000000000000000000000000000000..7318c18ddaba82d46046d25a26c0c28674ecbe5f
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_lm.h
@@ -0,0 +1,102 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_LM_H
+#define _SDE_HW_LM_H
+
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+
+struct sde_hw_mixer;
+
+struct sde_hw_mixer_cfg {
+	u32 out_width;
+	u32 out_height;
+	bool right_mixer;
+	int flags;
+};
+
+struct sde_hw_color3_cfg {
+	u8 keep_fg[SDE_STAGE_MAX];
+};
+
+/**
+ *
+ * struct sde_hw_lm_ops : Interface to the mixer Hw driver functions
+ *  Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_lm_ops {
+	/*
+	 * Sets up mixer output width and height
+	 * and border color if enabled
+	 */
+	void (*setup_mixer_out)(struct sde_hw_mixer *ctx,
+		struct sde_hw_mixer_cfg *cfg);
+
+	/*
+	 * Alpha blending configuration
+	 * for the specified stage
+	 */
+	void (*setup_blend_config)(struct sde_hw_mixer *ctx, uint32_t stage,
+		uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
+
+	/*
+	 * Alpha color component selection from either fg or bg
+	 */
+	void (*setup_alpha_out)(struct sde_hw_mixer *ctx, uint32_t mixer_op);
+
+	/**
+	 * setup_border_color : enable/disable border color
+	 */
+	void (*setup_border_color)(struct sde_hw_mixer *ctx,
+		struct sde_mdss_color *color,
+		u8 border_en);
+	/**
+	 * setup_gc : enable/disable gamma correction feature
+	 */
+	void (*setup_gc)(struct sde_hw_mixer *mixer,
+			void *cfg);
+
+};
+
+struct sde_hw_mixer {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* lm */
+	enum sde_lm  idx;
+	const struct sde_lm_cfg   *cap;
+	const struct sde_mdp_cfg  *mdp;
+	const struct sde_ctl_cfg  *ctl;
+
+	/* ops */
+	struct sde_hw_lm_ops ops;
+};
+
+/**
+ * sde_hw_lm_init(): Initializes the mixer hw driver object.
+ * should be called once before accessing every mixer.
+ * @idx:  mixer index for which driver object is required
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ */
+struct sde_hw_mixer *sde_hw_lm_init(enum sde_lm idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_lm_destroy(): Destroys layer mixer driver context
+ * @lm:   Pointer to LM driver context
+ */
+void sde_hw_lm_destroy(struct sde_hw_mixer *lm);
+
+#endif /*_SDE_HW_LM_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
new file mode 100644
index 0000000000000000000000000000000000000000..dcba248d27b0cdbf9c53884b2dcdade83b8e0292
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
@@ -0,0 +1,443 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_MDSS_H
+#define _SDE_HW_MDSS_H
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+
+#include "msm_drv.h"
+
+#define SDE_NONE                        0
+
+#ifndef SDE_CSC_MATRIX_COEFF_SIZE
+#define SDE_CSC_MATRIX_COEFF_SIZE	9
+#endif
+
+#ifndef SDE_CSC_CLAMP_SIZE
+#define SDE_CSC_CLAMP_SIZE		6
+#endif
+
+#ifndef SDE_CSC_BIAS_SIZE
+#define SDE_CSC_BIAS_SIZE		3
+#endif
+
+#ifndef SDE_MAX_PLANES
+#define SDE_MAX_PLANES			4
+#endif
+
+#define PIPES_PER_STAGE			2
+#ifndef SDE_MAX_DE_CURVES
+#define SDE_MAX_DE_CURVES		3
+#endif
+
+#define SDE_FORMAT_FLAG_YUV		(1 << 0)
+#define SDE_FORMAT_FLAG_DX		(1 << 1)
+
+#define SDE_FORMAT_IS_YUV(X)		((X)->flag & SDE_FORMAT_FLAG_YUV)
+#define SDE_FORMAT_IS_DX(X)		((X)->flag & SDE_FORMAT_FLAG_DX)
+#define SDE_FORMAT_IS_LINEAR(X)		((X)->fetch_mode == SDE_FETCH_LINEAR)
+#define SDE_FORMAT_IS_UBWC(X)		((X)->fetch_mode == SDE_FETCH_UBWC)
+
+#define SDE_BLEND_FG_ALPHA_FG_CONST	(0 << 0)
+#define SDE_BLEND_FG_ALPHA_BG_CONST	(1 << 0)
+#define SDE_BLEND_FG_ALPHA_FG_PIXEL	(2 << 0)
+#define SDE_BLEND_FG_ALPHA_BG_PIXEL	(3 << 0)
+#define SDE_BLEND_FG_INV_ALPHA		(1 << 2)
+#define SDE_BLEND_FG_MOD_ALPHA		(1 << 3)
+#define SDE_BLEND_FG_INV_MOD_ALPHA	(1 << 4)
+#define SDE_BLEND_FG_TRANSP_EN		(1 << 5)
+#define SDE_BLEND_BG_ALPHA_FG_CONST	(0 << 8)
+#define SDE_BLEND_BG_ALPHA_BG_CONST	(1 << 8)
+#define SDE_BLEND_BG_ALPHA_FG_PIXEL	(2 << 8)
+#define SDE_BLEND_BG_ALPHA_BG_PIXEL	(3 << 8)
+#define SDE_BLEND_BG_INV_ALPHA		(1 << 10)
+#define SDE_BLEND_BG_MOD_ALPHA		(1 << 11)
+#define SDE_BLEND_BG_INV_MOD_ALPHA	(1 << 12)
+#define SDE_BLEND_BG_TRANSP_EN		(1 << 13)
+
+enum sde_hw_blk_type {
+	SDE_HW_BLK_TOP = 0,
+	SDE_HW_BLK_SSPP,
+	SDE_HW_BLK_LM,
+	SDE_HW_BLK_DSPP,
+	SDE_HW_BLK_CTL,
+	SDE_HW_BLK_CDM,
+	SDE_HW_BLK_PINGPONG,
+	SDE_HW_BLK_INTF,
+	SDE_HW_BLK_WB,
+	SDE_HW_BLK_MAX,
+};
+
+enum sde_mdp {
+	MDP_TOP = 0x1,
+	MDP_MAX,
+};
+
+enum sde_sspp {
+	SSPP_NONE,
+	SSPP_VIG0,
+	SSPP_VIG1,
+	SSPP_VIG2,
+	SSPP_VIG3,
+	SSPP_RGB0,
+	SSPP_RGB1,
+	SSPP_RGB2,
+	SSPP_RGB3,
+	SSPP_DMA0,
+	SSPP_DMA1,
+	SSPP_DMA2,
+	SSPP_DMA3,
+	SSPP_CURSOR0,
+	SSPP_CURSOR1,
+	SSPP_MAX
+};
+
+enum sde_sspp_type {
+	SSPP_TYPE_VIG,
+	SSPP_TYPE_RGB,
+	SSPP_TYPE_DMA,
+	SSPP_TYPE_CURSOR,
+	SSPP_TYPE_MAX
+};
+
+enum sde_lm {
+	LM_0 = 1,
+	LM_1,
+	LM_2,
+	LM_3,
+	LM_4,
+	LM_5,
+	LM_6,
+	LM_MAX
+};
+
+enum sde_stage {
+	SDE_STAGE_BASE = 0,
+	SDE_STAGE_0,
+	SDE_STAGE_1,
+	SDE_STAGE_2,
+	SDE_STAGE_3,
+	SDE_STAGE_4,
+	SDE_STAGE_5,
+	SDE_STAGE_6,
+	SDE_STAGE_MAX
+};
+enum sde_dspp {
+	DSPP_0 = 1,
+	DSPP_1,
+	DSPP_2,
+	DSPP_3,
+	DSPP_MAX
+};
+
+enum sde_ctl {
+	CTL_0 = 1,
+	CTL_1,
+	CTL_2,
+	CTL_3,
+	CTL_4,
+	CTL_MAX
+};
+
+enum sde_cdm {
+	CDM_0 = 1,
+	CDM_1,
+	CDM_MAX
+};
+
+enum sde_pingpong {
+	PINGPONG_0 = 1,
+	PINGPONG_1,
+	PINGPONG_2,
+	PINGPONG_3,
+	PINGPONG_4,
+	PINGPONG_S0,
+	PINGPONG_MAX
+};
+
+enum sde_intf {
+	INTF_0 = 1,
+	INTF_1,
+	INTF_2,
+	INTF_3,
+	INTF_4,
+	INTF_5,
+	INTF_6,
+	INTF_MAX
+};
+
+enum sde_intf_type {
+	INTF_NONE = 0x0,
+	INTF_DSI = 0x1,
+	INTF_HDMI = 0x3,
+	INTF_LCDC = 0x5,
+	INTF_EDP = 0x9,
+	INTF_DP = 0xa,
+	INTF_TYPE_MAX,
+
+	/* virtual interfaces */
+	INTF_WB = 0x100,
+};
+
+enum sde_intf_mode {
+	INTF_MODE_NONE = 0,
+	INTF_MODE_CMD,
+	INTF_MODE_VIDEO,
+	INTF_MODE_WB_BLOCK,
+	INTF_MODE_WB_LINE,
+	INTF_MODE_MAX
+};
+
+enum sde_wb {
+	WB_0 = 1,
+	WB_1,
+	WB_2,
+	WB_3,
+	WB_MAX
+};
+
+enum sde_ad {
+	AD_0 = 0x1,
+	AD_1,
+	AD_MAX
+};
+
+enum sde_cwb {
+	CWB_0 = 0x1,
+	CWB_1,
+	CWB_2,
+	CWB_3,
+	CWB_MAX
+};
+
+enum sde_wd_timer {
+	WD_TIMER_0 = 0x1,
+	WD_TIMER_1,
+	WD_TIMER_2,
+	WD_TIMER_3,
+	WD_TIMER_4,
+	WD_TIMER_5,
+	WD_TIMER_MAX
+};
+
+enum sde_vbif {
+	VBIF_0,
+	VBIF_1,
+	VBIF_MAX,
+	VBIF_RT = VBIF_0,
+	VBIF_NRT = VBIF_1
+};
+
+enum sde_iommu_domain {
+	SDE_IOMMU_DOMAIN_UNSECURE,
+	SDE_IOMMU_DOMAIN_SECURE,
+	SDE_IOMMU_DOMAIN_MAX
+};
+
+/**
+ * SDE HW,Component order color map
+ */
+enum {
+	C0_G_Y = 0,
+	C1_B_Cb = 1,
+	C2_R_Cr = 2,
+	C3_ALPHA = 3
+};
+
+/**
+ * enum sde_plane_type - defines how the color component pixel packing
+ * @SDE_PLANE_INTERLEAVED   : Color components in single plane
+ * @SDE_PLANE_PLANAR        : Color component in separate planes
+ * @SDE_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
+ */
+enum sde_plane_type {
+	SDE_PLANE_INTERLEAVED,
+	SDE_PLANE_PLANAR,
+	SDE_PLANE_PSEUDO_PLANAR,
+};
+
+/**
+ * enum sde_chroma_samp_type - chroma sub-samplng type
+ * @SDE_CHROMA_RGB   : No chroma subsampling
+ * @SDE_CHROMA_H2V1  : Chroma pixels are horizontally subsampled
+ * @SDE_CHROMA_H1V2  : Chroma pixels are vertically subsampled
+ * @SDE_CHROMA_420   : 420 subsampling
+ */
+enum sde_chroma_samp_type {
+	SDE_CHROMA_RGB,
+	SDE_CHROMA_H2V1,
+	SDE_CHROMA_H1V2,
+	SDE_CHROMA_420
+};
+
+/**
+ * sde_fetch_type - Defines How SDE HW fetches data
+ * @SDE_FETCH_LINEAR   : fetch is line by line
+ * @SDE_FETCH_TILE     : fetches data in Z order from a tile
+ * @SDE_FETCH_UBWC     : fetch and decompress data
+ */
+enum sde_fetch_type {
+	SDE_FETCH_LINEAR,
+	SDE_FETCH_TILE,
+	SDE_FETCH_UBWC
+};
+
+/**
+ * Value of enum chosen to fit the number of bits
+ * expected by the HW programming.
+ */
+enum {
+	COLOR_ALPHA_1BIT = 0,
+	COLOR_ALPHA_4BIT = 1,
+	COLOR_4BIT = 0,
+	COLOR_5BIT = 1, /* No 5-bit Alpha */
+	COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
+	COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
+};
+
+/**
+ * enum sde_3d_blend_mode
+ * Desribes how the 3d data is blended
+ * @BLEND_3D_NONE      : 3d blending not enabled
+ * @BLEND_3D_FRAME_INT : Frame interleaving
+ * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
+ * @BLEND_3D_V_ROW_INT : vertical row interleaving
+ * @BLEND_3D_COL_INT   : column interleaving
+ * @BLEND_3D_MAX       :
+ */
+enum sde_3d_blend_mode {
+	BLEND_3D_NONE = 0,
+	BLEND_3D_FRAME_INT,
+	BLEND_3D_H_ROW_INT,
+	BLEND_3D_V_ROW_INT,
+	BLEND_3D_COL_INT,
+	BLEND_3D_MAX
+};
+
+/** struct sde_format - defines the format configuration which
+ * allows SDE HW to correctly fetch and decode the format
+ * @base: base msm_format struture containing fourcc code
+ * @fetch_planes: how the color components are packed in pixel format
+ * @element: element color ordering
+ * @bits: element bit widths
+ * @chroma_sample: chroma sub-samplng type
+ * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
+ * @unpack_tight: 0 for loose, 1 for tight
+ * @unpack_count: 0 = 1 component, 1 = 2 component
+ * @bpp: bytes per pixel
+ * @alpha_enable: whether the format has an alpha channel
+ * @num_planes: number of planes (including meta data planes)
+ * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
+ * @is_yuv: is format a yuv variant
+ * @flag: usage bit flags
+ * @tile_width: format tile width
+ * @tile_height: format tile height
+ */
+struct sde_format {
+	struct msm_format base;
+	enum sde_plane_type fetch_planes;
+	u8 element[SDE_MAX_PLANES];
+	u8 bits[SDE_MAX_PLANES];
+	enum sde_chroma_samp_type chroma_sample;
+	u8 unpack_align_msb;
+	u8 unpack_tight;
+	u8 unpack_count;
+	u8 bpp;
+	u8 alpha_enable;
+	u8 num_planes;
+	enum sde_fetch_type fetch_mode;
+	u32 flag;
+	u16 tile_width;
+	u16 tile_height;
+};
+#define to_sde_format(x) container_of(x, struct sde_format, base)
+
+/**
+ * struct sde_hw_fmt_layout - format information of the source pixel data
+ * @format: pixel format parameters
+ * @num_planes: number of planes (including meta data planes)
+ * @width: image width
+ * @height: image height
+ * @total_size: total size in bytes
+ * @plane_addr: address of each plane
+ * @plane_size: length of each plane
+ * @plane_pitch: pitch of each plane
+ */
+struct sde_hw_fmt_layout {
+	const struct sde_format *format;
+	uint32_t num_planes;
+	uint32_t width;
+	uint32_t height;
+	uint32_t total_size;
+	uint32_t plane_addr[SDE_MAX_PLANES];
+	uint32_t plane_size[SDE_MAX_PLANES];
+	uint32_t plane_pitch[SDE_MAX_PLANES];
+};
+
+struct sde_rect {
+	u16 x;
+	u16 y;
+	u16 w;
+	u16 h;
+};
+
+struct sde_csc_cfg {
+	/* matrix coefficients in S15.16 format */
+	uint32_t csc_mv[SDE_CSC_MATRIX_COEFF_SIZE];
+	uint32_t csc_pre_bv[SDE_CSC_BIAS_SIZE];
+	uint32_t csc_post_bv[SDE_CSC_BIAS_SIZE];
+	uint32_t csc_pre_lv[SDE_CSC_CLAMP_SIZE];
+	uint32_t csc_post_lv[SDE_CSC_CLAMP_SIZE];
+};
+
+/**
+ * struct sde_mdss_color - mdss color description
+ * color 0 : green
+ * color 1 : blue
+ * color 2 : red
+ * color 3 : alpha
+ */
+struct sde_mdss_color {
+	u32 color_0;
+	u32 color_1;
+	u32 color_2;
+	u32 color_3;
+};
+
+/*
+ * Define bit masks for h/w logging.
+ */
+#define SDE_DBG_MASK_NONE     (1 << 0)
+#define SDE_DBG_MASK_CDM      (1 << 1)
+#define SDE_DBG_MASK_DSPP     (1 << 2)
+#define SDE_DBG_MASK_INTF     (1 << 3)
+#define SDE_DBG_MASK_LM       (1 << 4)
+#define SDE_DBG_MASK_CTL      (1 << 5)
+#define SDE_DBG_MASK_PINGPONG (1 << 6)
+#define SDE_DBG_MASK_SSPP     (1 << 7)
+#define SDE_DBG_MASK_WB       (1 << 8)
+#define SDE_DBG_MASK_TOP      (1 << 9)
+#define SDE_DBG_MASK_VBIF     (1 << 10)
+
+/**
+ * struct sde_hw_cp_cfg: hardware dspp/lm feature payload.
+ * @payload: Feature specific payload.
+ * @len: Length of the payload.
+ */
+struct sde_hw_cp_cfg {
+	void *payload;
+	u32 len;
+};
+
+#endif  /* _SDE_HW_MDSS_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c
new file mode 100644
index 0000000000000000000000000000000000000000..837edeeba4c6cc5663302f9454925aaf0dcd0ed2
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c
@@ -0,0 +1,168 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_mdss.h"
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_pingpong.h"
+
+#define PP_TEAR_CHECK_EN                0x000
+#define PP_SYNC_CONFIG_VSYNC            0x004
+#define PP_SYNC_CONFIG_HEIGHT           0x008
+#define PP_SYNC_WRCOUNT                 0x00C
+#define PP_VSYNC_INIT_VAL               0x010
+#define PP_INT_COUNT_VAL                0x014
+#define PP_SYNC_THRESH                  0x018
+#define PP_START_POS                    0x01C
+#define PP_RD_PTR_IRQ                   0x020
+#define PP_WR_PTR_IRQ                   0x024
+#define PP_OUT_LINE_COUNT               0x028
+#define PP_LINE_COUNT                   0x02C
+#define PP_AUTOREFRESH_CONFIG           0x030
+
+#define PP_FBC_MODE                     0x034
+#define PP_FBC_BUDGET_CTL               0x038
+#define PP_FBC_LOSSY_MODE               0x03C
+#define PP_DSC_MODE                     0x0a0
+#define PP_DCE_DATA_IN_SWAP             0x0ac
+#define PP_DCE_DATA_OUT_SWAP            0x0c8
+
+static struct sde_pingpong_cfg *_pingpong_offset(enum sde_pingpong pp,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->pingpong_count; i++) {
+		if (pp == m->pingpong[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->pingpong[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_PINGPONG;
+			return &m->pingpong[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int sde_hw_pp_setup_te_config(struct sde_hw_pingpong *pp,
+		struct sde_hw_tear_check *te)
+{
+	struct sde_hw_blk_reg_map *c = &pp->hw;
+	int cfg;
+
+	cfg = BIT(19); /*VSYNC_COUNTER_EN */
+	if (te->hw_vsync_mode)
+		cfg |= BIT(20);
+
+	cfg |= te->vsync_count;
+
+	SDE_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
+	SDE_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
+	SDE_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
+	SDE_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
+	SDE_REG_WRITE(c, PP_START_POS, te->start_pos);
+	SDE_REG_WRITE(c, PP_SYNC_THRESH,
+			((te->sync_threshold_continue << 16) |
+			 te->sync_threshold_start));
+	SDE_REG_WRITE(c, PP_SYNC_WRCOUNT,
+			(te->start_pos + te->sync_threshold_start + 1));
+
+	return 0;
+}
+
+int sde_hw_pp_setup_autorefresh_config(struct sde_hw_pingpong *pp,
+		struct sde_hw_autorefresh *cfg)
+{
+	struct sde_hw_blk_reg_map *c = &pp->hw;
+	u32 refresh_cfg;
+
+	if (cfg->enable)
+		refresh_cfg = BIT(31) | cfg->frame_count;
+	else
+		refresh_cfg = 0;
+
+	SDE_REG_WRITE(c, PP_AUTOREFRESH_CONFIG,
+			refresh_cfg);
+
+	return 0;
+}
+
+int sde_hw_pp_setup_dsc_compression(struct sde_hw_pingpong *pp,
+		struct sde_hw_dsc_cfg *cfg)
+{
+	return 0;
+}
+int sde_hw_pp_enable_te(struct sde_hw_pingpong *pp, bool enable)
+{
+	struct sde_hw_blk_reg_map *c = &pp->hw;
+
+	SDE_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
+	return 0;
+}
+
+int sde_hw_pp_get_vsync_info(struct sde_hw_pingpong *pp,
+		struct sde_hw_pp_vsync_info *info)
+{
+	struct sde_hw_blk_reg_map *c = &pp->hw;
+	u32 val;
+
+	val = SDE_REG_READ(c, PP_VSYNC_INIT_VAL);
+	info->init_val = val & 0xffff;
+
+	val = SDE_REG_READ(c, PP_INT_COUNT_VAL);
+	info->vsync_count = (val & 0xffff0000) >> 16;
+	info->line_count = val & 0xffff;
+
+	return 0;
+}
+
+static void _setup_pingpong_ops(struct sde_hw_pingpong_ops *ops,
+		unsigned long cap)
+{
+	ops->setup_tearcheck = sde_hw_pp_setup_te_config;
+	ops->enable_tearcheck = sde_hw_pp_enable_te;
+	ops->get_vsync_info = sde_hw_pp_get_vsync_info;
+	ops->setup_autorefresh = sde_hw_pp_setup_autorefresh_config;
+	ops->setup_dsc = sde_hw_pp_setup_dsc_compression;
+};
+
+struct sde_hw_pingpong *sde_hw_pingpong_init(enum sde_pingpong idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m)
+{
+	struct sde_hw_pingpong *c;
+	struct sde_pingpong_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _pingpong_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	c->idx = idx;
+	c->pingpong_hw_cap = cfg;
+	_setup_pingpong_ops(&c->ops, c->pingpong_hw_cap->features);
+
+	return c;
+}
+
+void sde_hw_pingpong_destroy(struct sde_hw_pingpong *pp)
+{
+	kfree(pp);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h
new file mode 100644
index 0000000000000000000000000000000000000000..fc3bea54b485d7069ef6592248dcd5ef6fd460a1
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h
@@ -0,0 +1,123 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_PINGPONG_H
+#define _SDE_HW_PINGPONG_H
+
+struct sde_hw_pingpong;
+
+struct sde_hw_tear_check {
+	/*
+	 * This is ratio of MDP VSYNC clk freq(Hz) to
+	 * refresh rate divided by no of lines
+	 */
+	u32 vsync_count;
+	u32 sync_cfg_height;
+	u32 vsync_init_val;
+	u32 sync_threshold_start;
+	u32 sync_threshold_continue;
+	u32 start_pos;
+	u32 rd_ptr_irq;
+	u8 hw_vsync_mode;
+};
+
+struct sde_hw_autorefresh {
+	bool  enable;
+	u32 frame_count;
+};
+
+struct sde_hw_pp_vsync_info {
+	u32 init_val; /* value of rd pointer at vsync edge */
+	u32 vsync_count;    /* mdp clocks to complete one line */
+	u32 line_count;   /* current line count */
+};
+
+struct sde_hw_dsc_cfg {
+	u8 enable;
+};
+
+/**
+ *
+ * struct sde_hw_pingpong_ops : Interface to the pingpong Hw driver functions
+ *  Assumption is these functions will be called after clocks are enabled
+ *  @setup_tearcheck :
+ *  @enable_tearcheck :
+ *  @get_vsync_info :
+ *  @setup_autorefresh :
+ *  #setup_dsc :
+ */
+struct sde_hw_pingpong_ops {
+	/**
+	 * enables vysnc generation and sets up init value of
+	 * read pointer and programs the tear check cofiguration
+	 */
+	int (*setup_tearcheck)(struct sde_hw_pingpong *pp,
+			struct sde_hw_tear_check *cfg);
+
+	/**
+	 * enables tear check block
+	 */
+	int (*enable_tearcheck)(struct sde_hw_pingpong *pp,
+			bool enable);
+
+	/**
+	 * provides the programmed and current
+	 * line_count
+	 */
+	int (*get_vsync_info)(struct sde_hw_pingpong *pp,
+			struct sde_hw_pp_vsync_info  *info);
+
+	/**
+	 * configure and enable the autorefresh config
+	 */
+	int (*setup_autorefresh)(struct sde_hw_pingpong *pp,
+			struct sde_hw_autorefresh *cfg);
+
+	/**
+	 * Program the dsc compression block
+	 */
+	int (*setup_dsc)(struct sde_hw_pingpong *pp,
+			struct sde_hw_dsc_cfg *cfg);
+};
+
+struct sde_hw_pingpong {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* pingpong */
+	enum sde_pingpong idx;
+	const struct sde_pingpong_cfg *pingpong_hw_cap;
+
+	/* ops */
+	struct sde_hw_pingpong_ops ops;
+};
+
+/**
+ * sde_hw_pingpong_init - initializes the pingpong driver for the passed
+ *	pingpong idx.
+ * @idx:  Pingpong index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * @m:    Pointer to mdss catalog data
+ * Returns: Error code or allocated sde_hw_pingpong context
+ */
+struct sde_hw_pingpong *sde_hw_pingpong_init(enum sde_pingpong idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m);
+
+/**
+ * sde_hw_pingpong_destroy - destroys pingpong driver context
+ *	should be called to free the context
+ * @pp:   Pointer to PP driver context returned by sde_hw_pingpong_init
+ */
+void sde_hw_pingpong_destroy(struct sde_hw_pingpong *pp);
+
+#endif /*_SDE_HW_PINGPONG_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
new file mode 100644
index 0000000000000000000000000000000000000000..882a1c84e9a28ed831ac0400fa22020b986faa4d
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -0,0 +1,943 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_lm.h"
+#include "sde_hw_sspp.h"
+#include "sde_hw_color_processing.h"
+
+#define SDE_FETCH_CONFIG_RESET_VALUE   0x00000087
+
+/* SDE_SSPP_SRC */
+#define SSPP_SRC_SIZE                      0x00
+#define SSPP_SRC_XY                        0x08
+#define SSPP_OUT_SIZE                      0x0c
+#define SSPP_OUT_XY                        0x10
+#define SSPP_SRC0_ADDR                     0x14
+#define SSPP_SRC1_ADDR                     0x18
+#define SSPP_SRC2_ADDR                     0x1C
+#define SSPP_SRC3_ADDR                     0x20
+#define SSPP_SRC_YSTRIDE0                  0x24
+#define SSPP_SRC_YSTRIDE1                  0x28
+#define SSPP_SRC_FORMAT                    0x30
+#define SSPP_SRC_UNPACK_PATTERN            0x34
+#define SSPP_SRC_OP_MODE                   0x38
+#define MDSS_MDP_OP_DEINTERLACE            BIT(22)
+
+#define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
+#define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
+#define MDSS_MDP_OP_IGC_ROM_0              BIT(17)
+#define MDSS_MDP_OP_IGC_EN                 BIT(16)
+#define MDSS_MDP_OP_FLIP_UD                BIT(14)
+#define MDSS_MDP_OP_FLIP_LR                BIT(13)
+#define MDSS_MDP_OP_BWC_EN                 BIT(0)
+#define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)
+#define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
+#define MDSS_MDP_OP_BWC_Q_HIGH             (1 << 1)
+#define MDSS_MDP_OP_BWC_Q_MED              (2 << 1)
+
+#define SSPP_SRC_CONSTANT_COLOR            0x3c
+#define SSPP_FETCH_CONFIG                  0x048
+#define SSPP_DANGER_LUT                    0x60
+#define SSPP_SAFE_LUT                      0x64
+#define SSPP_CREQ_LUT                      0x68
+#define SSPP_QOS_CTRL                      0x6C
+#define SSPP_DECIMATION_CONFIG             0xB4
+#define SSPP_SRC_ADDR_SW_STATUS            0x70
+#define SSPP_SW_PIX_EXT_C0_LR              0x100
+#define SSPP_SW_PIX_EXT_C0_TB              0x104
+#define SSPP_SW_PIX_EXT_C0_REQ_PIXELS      0x108
+#define SSPP_SW_PIX_EXT_C1C2_LR            0x110
+#define SSPP_SW_PIX_EXT_C1C2_TB            0x114
+#define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS    0x118
+#define SSPP_SW_PIX_EXT_C3_LR              0x120
+#define SSPP_SW_PIX_EXT_C3_TB              0x124
+#define SSPP_SW_PIX_EXT_C3_REQ_PIXELS      0x128
+#define SSPP_UBWC_ERROR_STATUS             0x138
+#define SSPP_VIG_OP_MODE                   0x0
+#define SSPP_VIG_CSC_10_OP_MODE            0x0
+
+/* SSPP_QOS_CTRL */
+#define SSPP_QOS_CTRL_VBLANK_EN            BIT(16)
+#define SSPP_QOS_CTRL_DANGER_SAFE_EN       BIT(0)
+#define SSPP_QOS_CTRL_DANGER_VBLANK_MASK   0x3
+#define SSPP_QOS_CTRL_DANGER_VBLANK_OFF    4
+#define SSPP_QOS_CTRL_CREQ_VBLANK_MASK     0x3
+#define SSPP_QOS_CTRL_CREQ_VBLANK_OFF      20
+
+/* SDE_SSPP_SCALER_QSEED2 */
+#define SCALE_CONFIG                       0x04
+#define COMP0_3_PHASE_STEP_X               0x10
+#define COMP0_3_PHASE_STEP_Y               0x14
+#define COMP1_2_PHASE_STEP_X               0x18
+#define COMP1_2_PHASE_STEP_Y               0x1c
+#define COMP0_3_INIT_PHASE_X               0x20
+#define COMP0_3_INIT_PHASE_Y               0x24
+#define COMP1_2_INIT_PHASE_X               0x28
+#define COMP1_2_INIT_PHASE_Y               0x2C
+#define VIG_0_QSEED2_SHARP                 0x30
+
+/* SDE_SSPP_SCALER_QSEED3 */
+#define QSEED3_HW_VERSION                  0x00
+#define QSEED3_OP_MODE                     0x04
+#define QSEED3_RGB2Y_COEFF                 0x08
+#define QSEED3_PHASE_INIT                  0x0C
+#define QSEED3_PHASE_STEP_Y_H              0x10
+#define QSEED3_PHASE_STEP_Y_V              0x14
+#define QSEED3_PHASE_STEP_UV_H             0x18
+#define QSEED3_PHASE_STEP_UV_V             0x1C
+#define QSEED3_PRELOAD                     0x20
+#define QSEED3_DE_SHARPEN                  0x24
+#define QSEED3_DE_SHARPEN_CTL              0x28
+#define QSEED3_DE_SHAPE_CTL                0x2C
+#define QSEED3_DE_THRESHOLD                0x30
+#define QSEED3_DE_ADJUST_DATA_0            0x34
+#define QSEED3_DE_ADJUST_DATA_1            0x38
+#define QSEED3_DE_ADJUST_DATA_2            0x3C
+#define QSEED3_SRC_SIZE_Y_RGB_A            0x40
+#define QSEED3_SRC_SIZE_UV                 0x44
+#define QSEED3_DST_SIZE                    0x48
+#define QSEED3_COEF_LUT_CTRL               0x4C
+#define QSEED3_COEF_LUT_SWAP_BIT           0
+#define QSEED3_COEF_LUT_DIR_BIT            1
+#define QSEED3_COEF_LUT_Y_CIR_BIT          2
+#define QSEED3_COEF_LUT_UV_CIR_BIT         3
+#define QSEED3_COEF_LUT_Y_SEP_BIT          4
+#define QSEED3_COEF_LUT_UV_SEP_BIT         5
+#define QSEED3_BUFFER_CTRL                 0x50
+#define QSEED3_CLK_CTRL0                   0x54
+#define QSEED3_CLK_CTRL1                   0x58
+#define QSEED3_CLK_STATUS                  0x5C
+#define QSEED3_MISR_CTRL                   0x70
+#define QSEED3_MISR_SIGNATURE_0            0x74
+#define QSEED3_MISR_SIGNATURE_1            0x78
+#define QSEED3_PHASE_INIT_Y_H              0x90
+#define QSEED3_PHASE_INIT_Y_V              0x94
+#define QSEED3_PHASE_INIT_UV_H             0x98
+#define QSEED3_PHASE_INIT_UV_V             0x9C
+#define QSEED3_COEF_LUT                    0x100
+#define QSEED3_FILTERS                     5
+#define QSEED3_LUT_REGIONS                 4
+#define QSEED3_CIRCULAR_LUTS               9
+#define QSEED3_SEPARABLE_LUTS              10
+#define QSEED3_LUT_SIZE                    60
+#define QSEED3_ENABLE                      2
+#define QSEED3_DIR_LUT_SIZE                (200 * sizeof(u32))
+#define QSEED3_CIR_LUT_SIZE \
+	(QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
+#define QSEED3_SEP_LUT_SIZE \
+	(QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
+
+/*
+ * Definitions for ViG op modes
+ */
+#define VIG_OP_CSC_DST_DATAFMT BIT(19)
+#define VIG_OP_CSC_SRC_DATAFMT BIT(18)
+#define VIG_OP_CSC_EN          BIT(17)
+#define VIG_OP_MEM_PROT_CONT   BIT(15)
+#define VIG_OP_MEM_PROT_VAL    BIT(14)
+#define VIG_OP_MEM_PROT_SAT    BIT(13)
+#define VIG_OP_MEM_PROT_HUE    BIT(12)
+#define VIG_OP_HIST            BIT(8)
+#define VIG_OP_SKY_COL         BIT(7)
+#define VIG_OP_FOIL            BIT(6)
+#define VIG_OP_SKIN_COL        BIT(5)
+#define VIG_OP_PA_EN           BIT(4)
+#define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
+#define VIG_OP_MEM_PROT_BLEND  BIT(1)
+
+/*
+ * Definitions for CSC 10 op modes
+ */
+#define VIG_CSC_10_SRC_DATAFMT BIT(1)
+#define VIG_CSC_10_EN          BIT(0)
+#define CSC_10BIT_OFFSET       4
+
+static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
+		int s_id,
+		u32 *idx)
+{
+	int rc = 0;
+	const struct sde_sspp_sub_blks *sblk = ctx->cap->sblk;
+
+	if (!ctx)
+		return -EINVAL;
+
+	switch (s_id) {
+	case SDE_SSPP_SRC:
+		*idx = sblk->src_blk.base;
+		break;
+	case SDE_SSPP_SCALER_QSEED2:
+	case SDE_SSPP_SCALER_QSEED3:
+	case SDE_SSPP_SCALER_RGB:
+		*idx = sblk->scaler_blk.base;
+		break;
+	case SDE_SSPP_CSC:
+	case SDE_SSPP_CSC_10BIT:
+		*idx = sblk->csc_blk.base;
+		break;
+	case SDE_SSPP_HSIC:
+		*idx = sblk->hsic_blk.base;
+		break;
+	case SDE_SSPP_PCC:
+		*idx = sblk->pcc_blk.base;
+		break;
+	case SDE_SSPP_MEMCOLOR:
+		*idx = sblk->memcolor_blk.base;
+		break;
+	default:
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+
+static void _sspp_setup_opmode(struct sde_hw_pipe *ctx,
+		u32 mask, u8 en)
+{
+	u32 idx;
+	u32 opmode;
+
+	if (!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
+		_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) ||
+		!test_bit(SDE_SSPP_CSC, &ctx->cap->features))
+		return;
+
+	opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
+
+	if (en)
+		opmode |= mask;
+	else
+		opmode &= ~mask;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
+}
+
+static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx,
+		u32 mask, u8 en)
+{
+	u32 idx;
+	u32 opmode;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC_10BIT, &idx))
+		return;
+
+	opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
+	if (en)
+		opmode |= mask;
+	else
+		opmode &= ~mask;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode);
+}
+
+/**
+ * Setup source pixel format, flip,
+ */
+static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
+		const struct sde_format *fmt, u32 flags)
+{
+	struct sde_hw_blk_reg_map *c;
+	u32 chroma_samp, unpack, src_format;
+	u32 secure = 0;
+	u32 opmode = 0;
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !fmt)
+		return;
+
+	c = &ctx->hw;
+	opmode = SDE_REG_READ(c, SSPP_SRC_OP_MODE + idx);
+	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
+			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
+
+	if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION)
+		secure = 0xF;
+
+	if (flags & SDE_SSPP_FLIP_LR)
+		opmode |= MDSS_MDP_OP_FLIP_LR;
+	if (flags & SDE_SSPP_FLIP_UD)
+		opmode |= MDSS_MDP_OP_FLIP_UD;
+
+	chroma_samp = fmt->chroma_sample;
+	if (flags & SDE_SSPP_SOURCE_ROTATED_90) {
+		if (chroma_samp == SDE_CHROMA_H2V1)
+			chroma_samp = SDE_CHROMA_H1V2;
+		else if (chroma_samp == SDE_CHROMA_H1V2)
+			chroma_samp = SDE_CHROMA_H2V1;
+	}
+
+	src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
+		(fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
+		(fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
+
+	if (flags & SDE_SSPP_ROT_90)
+		src_format |= BIT(11); /* ROT90 */
+
+	if (fmt->alpha_enable && fmt->fetch_planes == SDE_PLANE_INTERLEAVED)
+		src_format |= BIT(8); /* SRCC3_EN */
+
+	if (flags & SDE_SSPP_SOLID_FILL)
+		src_format |= BIT(22);
+
+	unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
+		(fmt->element[1] << 8) | (fmt->element[0] << 0);
+	src_format |= ((fmt->unpack_count - 1) << 12) |
+		(fmt->unpack_tight << 17) |
+		(fmt->unpack_align_msb << 18) |
+		((fmt->bpp - 1) << 9);
+
+	if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
+		if (SDE_FORMAT_IS_UBWC(fmt))
+			opmode |= MDSS_MDP_OP_BWC_EN;
+		src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
+		SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
+			SDE_FETCH_CONFIG_RESET_VALUE |
+			ctx->highest_bank_bit << 18);
+	}
+
+	opmode |= MDSS_MDP_OP_PE_OVERRIDE;
+
+	/* if this is YUV pixel format, enable CSC */
+	if (SDE_FORMAT_IS_YUV(fmt))
+		src_format |= BIT(15);
+
+	if (SDE_FORMAT_IS_DX(fmt))
+		src_format |= BIT(14);
+
+	/* update scaler opmode, if appropriate */
+	if (test_bit(SDE_SSPP_CSC, &ctx->cap->features))
+		_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
+			SDE_FORMAT_IS_YUV(fmt));
+	else if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features))
+		_sspp_setup_csc10_opmode(ctx,
+			VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
+			SDE_FORMAT_IS_YUV(fmt));
+
+	SDE_REG_WRITE(c, SSPP_SRC_FORMAT + idx, src_format);
+	SDE_REG_WRITE(c, SSPP_SRC_UNPACK_PATTERN + idx, unpack);
+	SDE_REG_WRITE(c, SSPP_SRC_OP_MODE + idx, opmode);
+	SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);
+
+	/* clear previous UBWC error */
+	SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
+}
+
+static void sde_hw_sspp_setup_pe_config(struct sde_hw_pipe *ctx,
+		struct sde_hw_pixel_ext *pe_ext)
+{
+	struct sde_hw_blk_reg_map *c;
+	u8 color;
+	u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
+	const u32 bytemask = 0xff;
+	const u32 shortmask = 0xffff;
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !pe_ext)
+		return;
+
+	c = &ctx->hw;
+
+	/* program SW pixel extension override for all pipes*/
+	for (color = 0; color < SDE_MAX_PLANES; color++) {
+		/* color 2 has the same set of registers as color 1 */
+		if (color == 2)
+			continue;
+
+		lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
+			((pe_ext->right_rpt[color] & bytemask) << 16)|
+			((pe_ext->left_ftch[color] & bytemask) << 8)|
+			(pe_ext->left_rpt[color] & bytemask);
+
+		tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
+			((pe_ext->btm_rpt[color] & bytemask) << 16)|
+			((pe_ext->top_ftch[color] & bytemask) << 8)|
+			(pe_ext->top_rpt[color] & bytemask);
+
+		tot_req_pixels[color] = (((pe_ext->roi_h[color] +
+			pe_ext->num_ext_pxls_top[color] +
+			pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
+			((pe_ext->roi_w[color] +
+			pe_ext->num_ext_pxls_left[color] +
+			pe_ext->num_ext_pxls_right[color]) & shortmask);
+	}
+
+	/* color 0 */
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx,
+			tot_req_pixels[0]);
+
+	/* color 1 and color 2 */
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx,
+			tot_req_pixels[1]);
+
+	/* color 3 */
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]);
+	SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx,
+			tot_req_pixels[3]);
+}
+
+static void _sde_hw_sspp_setup_scaler(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_cfg *sspp,
+		struct sde_hw_pixel_ext *pe,
+		void *scaler_cfg)
+{
+	struct sde_hw_blk_reg_map *c;
+	int config_h = 0x0;
+	int config_v = 0x0;
+	u32 idx;
+
+	(void)sspp;
+	(void)scaler_cfg;
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !pe)
+		return;
+
+	c = &ctx->hw;
+
+	/* enable scaler(s) if valid filter set */
+	if (pe->horz_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
+		config_h |= pe->horz_filter[SDE_SSPP_COMP_0] << 8;
+	if (pe->horz_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
+		config_h |= pe->horz_filter[SDE_SSPP_COMP_1_2] << 12;
+	if (pe->horz_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
+		config_h |= pe->horz_filter[SDE_SSPP_COMP_3] << 16;
+
+	if (config_h)
+		config_h |= BIT(0);
+
+	if (pe->vert_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX)
+		config_v |= pe->vert_filter[SDE_SSPP_COMP_0] << 10;
+	if (pe->vert_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX)
+		config_v |= pe->vert_filter[SDE_SSPP_COMP_1_2] << 14;
+	if (pe->vert_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX)
+		config_v |= pe->vert_filter[SDE_SSPP_COMP_3] << 18;
+
+	if (config_v)
+		config_v |= BIT(1);
+
+	SDE_REG_WRITE(c, SCALE_CONFIG + idx,  config_h | config_v);
+	SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_X + idx,
+		pe->init_phase_x[SDE_SSPP_COMP_0]);
+	SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_Y + idx,
+		pe->init_phase_y[SDE_SSPP_COMP_0]);
+	SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_X + idx,
+		pe->phase_step_x[SDE_SSPP_COMP_0]);
+	SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_Y + idx,
+		pe->phase_step_y[SDE_SSPP_COMP_0]);
+
+	SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_X + idx,
+		pe->init_phase_x[SDE_SSPP_COMP_1_2]);
+	SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_Y + idx,
+		pe->init_phase_y[SDE_SSPP_COMP_1_2]);
+	SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_X + idx,
+		pe->phase_step_x[SDE_SSPP_COMP_1_2]);
+	SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_Y + idx,
+		pe->phase_step_y[SDE_SSPP_COMP_1_2]);
+}
+
+static void _sde_hw_sspp_setup_scaler3_lut(struct sde_hw_pipe *ctx,
+		struct sde_hw_scaler3_cfg *scaler3_cfg)
+{
+	u32 idx;
+	int i, j, filter;
+	int config_lut = 0x0;
+	unsigned long lut_flags;
+	u32 lut_addr, lut_offset, lut_len;
+	u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
+	static const uint32_t offset[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
+		{{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
+		{{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
+		{{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
+		{{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
+		{{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
+	};
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) ||
+		!scaler3_cfg)
+		return;
+
+	lut_flags = (unsigned long) scaler3_cfg->lut_flag;
+	if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
+		(scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
+		lut[0] = scaler3_cfg->dir_lut;
+		config_lut = 1;
+	}
+	if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
+		(scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+		(scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+		lut[1] = scaler3_cfg->cir_lut +
+			scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
+		config_lut = 1;
+	}
+	if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
+		(scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+		(scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+		lut[2] = scaler3_cfg->cir_lut +
+			scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
+		config_lut = 1;
+	}
+	if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
+		(scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+		(scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+		lut[3] = scaler3_cfg->sep_lut +
+			scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
+		config_lut = 1;
+	}
+	if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
+		(scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+		(scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+		lut[4] = scaler3_cfg->sep_lut +
+			scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
+		config_lut = 1;
+	}
+
+	if (config_lut) {
+		for (filter = 0; filter < QSEED3_FILTERS; filter++) {
+			if (!lut[filter])
+				continue;
+			lut_offset = 0;
+			for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
+				lut_addr = QSEED3_COEF_LUT + idx
+					+ offset[filter][i][1];
+				lut_len = offset[filter][i][0] << 2;
+				for (j = 0; j < lut_len; j++) {
+					SDE_REG_WRITE(&ctx->hw,
+						lut_addr,
+						(lut[filter])[lut_offset++]);
+					lut_addr += 4;
+				}
+			}
+		}
+	}
+
+	if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
+		SDE_REG_WRITE(&ctx->hw, QSEED3_COEF_LUT_CTRL + idx, BIT(0));
+
+}
+
+static void _sde_hw_sspp_setup_scaler3_de(struct sde_hw_pipe *ctx,
+		struct sde_hw_scaler3_de_cfg *de_cfg)
+{
+	u32 idx;
+	u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
+	u32 adjust_a, adjust_b, adjust_c;
+	struct sde_hw_blk_reg_map *hw;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !de_cfg)
+		return;
+
+	if (!de_cfg->enable)
+		return;
+
+	hw = &ctx->hw;
+	sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
+		((de_cfg->sharpen_level2 & 0x1FF) << 16);
+
+	sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
+		((de_cfg->prec_shift & 0x7) << 13) |
+		((de_cfg->clip & 0x7) << 16);
+
+	shape_ctl = (de_cfg->thr_quiet & 0xFF) |
+		((de_cfg->thr_dieout & 0x3FF) << 16);
+
+	de_thr = (de_cfg->thr_low & 0x3FF) |
+		((de_cfg->thr_high & 0x3FF) << 16);
+
+	adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
+		((de_cfg->adjust_a[1] & 0x3FF) << 10) |
+		((de_cfg->adjust_a[2] & 0x3FF) << 20);
+
+	adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
+		((de_cfg->adjust_b[1] & 0x3FF) << 10) |
+		((de_cfg->adjust_b[2] & 0x3FF) << 20);
+
+	adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
+		((de_cfg->adjust_c[1] & 0x3FF) << 10) |
+		((de_cfg->adjust_c[2] & 0x3FF) << 20);
+
+	SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN + idx, sharp_lvl);
+	SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN_CTL + idx, sharp_ctl);
+	SDE_REG_WRITE(hw, QSEED3_DE_SHAPE_CTL + idx, shape_ctl);
+	SDE_REG_WRITE(hw, QSEED3_DE_THRESHOLD + idx, de_thr);
+	SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_0 + idx, adjust_a);
+	SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_1 + idx, adjust_b);
+	SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_2 + idx, adjust_c);
+
+}
+
+static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_cfg *sspp,
+		struct sde_hw_pixel_ext *pe,
+		void *scaler_cfg)
+{
+	u32 idx;
+	u32 op_mode = 0;
+	u32 phase_init, preload, src_y_rgb, src_uv, dst;
+	struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
+
+	(void)pe;
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !sspp
+		|| !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
+		return;
+
+	if (!scaler3_cfg->enable) {
+		SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, 0x0);
+		return;
+	}
+
+	op_mode |= BIT(0);
+	op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
+
+	if (SDE_FORMAT_IS_YUV(sspp->layout.format)) {
+		op_mode |= BIT(12);
+		op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
+	}
+
+	if (!SDE_FORMAT_IS_DX(sspp->layout.format))
+		op_mode |= BIT(14);
+
+	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
+	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+
+	preload =
+		((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
+		((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
+		((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
+		((scaler3_cfg->preload_y[1] & 0x7F) << 24);
+
+	src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
+		((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
+
+	src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
+		((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
+
+	dst = (scaler3_cfg->dst_width & 0x1FFFF) |
+		((scaler3_cfg->dst_height & 0x1FFFF) << 16);
+
+	if (scaler3_cfg->de.enable) {
+		_sde_hw_sspp_setup_scaler3_de(ctx, &scaler3_cfg->de);
+		op_mode |= BIT(8);
+	}
+
+	if (scaler3_cfg->lut_flag)
+		_sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg);
+
+	if (ctx->cap->sblk->scaler_blk.version == 0x1002) {
+		if (sspp->layout.format->alpha_enable) {
+			op_mode |= BIT(10);
+			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
+		}
+		phase_init =
+			((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
+			((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
+			((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
+			((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
+		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init);
+	} else {
+		if (sspp->layout.format->alpha_enable) {
+			op_mode |= BIT(10);
+			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
+		}
+		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx,
+			scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
+		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx,
+			scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
+		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_H + idx,
+			scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
+		SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_V + idx,
+			scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
+	}
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_H + idx,
+		scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_V + idx,
+		scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_H + idx,
+		scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_V + idx,
+		scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_PRELOAD + idx, preload);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_Y_RGB_A + idx, src_y_rgb);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_UV + idx, src_uv);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst);
+
+	SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode);
+}
+
+/**
+ * sde_hw_sspp_setup_rects()
+ */
+static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_cfg *cfg,
+		struct sde_hw_pixel_ext *pe_ext,
+		void *scale_cfg)
+{
+	struct sde_hw_blk_reg_map *c;
+	u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
+	u32 decimation = 0;
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !cfg)
+		return;
+
+	c = &ctx->hw;
+
+	/* program pixel extension override */
+	if (pe_ext)
+		sde_hw_sspp_setup_pe_config(ctx, pe_ext);
+
+	/* src and dest rect programming */
+	src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x);
+	src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w);
+	dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x);
+	dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w);
+
+	ystride0 = (cfg->layout.plane_pitch[0]) |
+			(cfg->layout.plane_pitch[1] << 16);
+	ystride1 = (cfg->layout.plane_pitch[2]) |
+			(cfg->layout.plane_pitch[3] << 16);
+
+	/* program scaler, phase registers, if pipes supporting scaling */
+	if (ctx->cap->features & SDE_SSPP_SCALER) {
+		/* program decimation */
+		decimation = ((1 << cfg->horz_decimation) - 1) << 8;
+		decimation |= ((1 << cfg->vert_decimation) - 1);
+		ctx->ops.setup_scaler(ctx, cfg, pe_ext, scale_cfg);
+	}
+
+	/* rectangle register programming */
+	SDE_REG_WRITE(c, SSPP_SRC_SIZE + idx, src_size);
+	SDE_REG_WRITE(c, SSPP_SRC_XY + idx, src_xy);
+	SDE_REG_WRITE(c, SSPP_OUT_SIZE + idx, dst_size);
+	SDE_REG_WRITE(c, SSPP_OUT_XY + idx, dst_xy);
+
+	SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
+	SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
+	SDE_REG_WRITE(c, SSPP_DECIMATION_CONFIG + idx, decimation);
+}
+
+static void sde_hw_sspp_setup_sourceaddress(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_cfg *cfg)
+{
+	int i;
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
+		SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
+			cfg->layout.plane_addr[i]);
+}
+
+static void sde_hw_sspp_setup_csc(struct sde_hw_pipe *ctx,
+		struct sde_csc_cfg *data)
+{
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC, &idx) || !data)
+		return;
+
+	if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features))
+		idx += CSC_10BIT_OFFSET;
+
+	sde_hw_csc_setup(&ctx->hw, idx, data);
+}
+
+static void sde_hw_sspp_setup_sharpening(struct sde_hw_pipe *ctx,
+		struct sde_hw_sharp_cfg *cfg)
+{
+	struct sde_hw_blk_reg_map *c;
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !cfg ||
+			!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features))
+		return;
+
+	c = &ctx->hw;
+
+	SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx, cfg->strength);
+	SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x4, cfg->edge_thr);
+	SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x8, cfg->smooth_thr);
+	SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0xC, cfg->noise_thr);
+}
+
+static void sde_hw_sspp_setup_solidfill(struct sde_hw_pipe *ctx, u32 color)
+{
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
+		return;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
+}
+
+static void sde_hw_sspp_setup_danger_safe_lut(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_qos_cfg *cfg)
+{
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
+		return;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
+	SDE_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
+}
+
+static void sde_hw_sspp_setup_creq_lut(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_qos_cfg *cfg)
+{
+	u32 idx;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
+		return;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
+}
+
+static void sde_hw_sspp_setup_qos_ctrl(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_qos_cfg *cfg)
+{
+	u32 idx;
+	u32 qos_ctrl = 0;
+
+	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
+		return;
+
+	if (cfg->vblank_en) {
+		qos_ctrl |= ((cfg->creq_vblank &
+				SSPP_QOS_CTRL_CREQ_VBLANK_MASK) <<
+				SSPP_QOS_CTRL_CREQ_VBLANK_OFF);
+		qos_ctrl |= ((cfg->danger_vblank &
+				SSPP_QOS_CTRL_DANGER_VBLANK_MASK) <<
+				SSPP_QOS_CTRL_DANGER_VBLANK_OFF);
+		qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN;
+	}
+
+	if (cfg->danger_safe_en)
+		qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
+
+	SDE_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
+}
+
+static void _setup_layer_ops(struct sde_hw_pipe *c,
+		unsigned long features)
+{
+	if (test_bit(SDE_SSPP_SRC, &features)) {
+		c->ops.setup_format = sde_hw_sspp_setup_format;
+		c->ops.setup_rects = sde_hw_sspp_setup_rects;
+		c->ops.setup_sourceaddress = sde_hw_sspp_setup_sourceaddress;
+		c->ops.setup_solidfill = sde_hw_sspp_setup_solidfill;
+	}
+	if (test_bit(SDE_SSPP_QOS, &features)) {
+		c->ops.setup_danger_safe_lut =
+			sde_hw_sspp_setup_danger_safe_lut;
+		c->ops.setup_creq_lut = sde_hw_sspp_setup_creq_lut;
+		c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl;
+	}
+
+	if (test_bit(SDE_SSPP_CSC, &features) ||
+		test_bit(SDE_SSPP_CSC_10BIT, &features))
+		c->ops.setup_csc = sde_hw_sspp_setup_csc;
+
+	if (test_bit(SDE_SSPP_SCALER_QSEED2, &features))
+		c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening;
+
+	if (test_bit(SDE_SSPP_SCALER_QSEED3, &features))
+		c->ops.setup_scaler = _sde_hw_sspp_setup_scaler3;
+	else
+		c->ops.setup_scaler = _sde_hw_sspp_setup_scaler;
+
+	if (test_bit(SDE_SSPP_HSIC, &features)) {
+		/* TODO: add version based assignment here as inline or macro */
+		if (c->cap->sblk->hsic_blk.version ==
+			(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
+			c->ops.setup_pa_hue = sde_setup_pipe_pa_hue_v1_7;
+			c->ops.setup_pa_sat = sde_setup_pipe_pa_sat_v1_7;
+			c->ops.setup_pa_val = sde_setup_pipe_pa_val_v1_7;
+			c->ops.setup_pa_cont = sde_setup_pipe_pa_cont_v1_7;
+		}
+	}
+
+	if (test_bit(SDE_SSPP_MEMCOLOR, &features)) {
+		if (c->cap->sblk->memcolor_blk.version ==
+			(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
+			c->ops.setup_pa_memcolor =
+				sde_setup_pipe_pa_memcol_v1_7;
+	}
+}
+
+static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
+		void __iomem *addr,
+		struct sde_mdss_cfg *catalog,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	if ((sspp < SSPP_MAX) && catalog && addr && b) {
+		for (i = 0; i < catalog->sspp_count; i++) {
+			if (sspp == catalog->sspp[i].id) {
+				b->base_off = addr;
+				b->blk_off = catalog->sspp[i].base;
+				b->hwversion = catalog->hwversion;
+				b->log_mask = SDE_DBG_MASK_SSPP;
+				return &catalog->sspp[i];
+			}
+		}
+	}
+
+	return ERR_PTR(-ENOMEM);
+}
+
+struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
+			void __iomem *addr,
+			struct sde_mdss_cfg *catalog)
+{
+	struct sde_hw_pipe *ctx;
+	struct sde_sspp_cfg *cfg;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _sspp_offset(idx, addr, catalog, &ctx->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(ctx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Assign ops */
+	ctx->idx = idx;
+	ctx->cap = cfg;
+	_setup_layer_ops(ctx, ctx->cap->features);
+	ctx->highest_bank_bit = catalog->mdp[0].highest_bank_bit;
+
+	return ctx;
+}
+
+void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx)
+{
+	kfree(ctx);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
new file mode 100644
index 0000000000000000000000000000000000000000..743f5e72d1a86c475e179f6635c4884dd223f927
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -0,0 +1,467 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_SSPP_H
+#define _SDE_HW_SSPP_H
+
+#include "sde_hw_catalog.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+#include "sde_formats.h"
+#include "sde_color_processing.h"
+
+struct sde_hw_pipe;
+
+/**
+ * Flags
+ */
+#define SDE_SSPP_SECURE_OVERLAY_SESSION 0x1
+#define SDE_SSPP_FLIP_LR	 0x2
+#define SDE_SSPP_FLIP_UD	 0x4
+#define SDE_SSPP_SOURCE_ROTATED_90 0x8
+#define SDE_SSPP_ROT_90  0x10
+#define SDE_SSPP_SOLID_FILL 0x20
+
+/**
+ * Define all scaler feature bits in catalog
+ */
+#define SDE_SSPP_SCALER ((1UL << SDE_SSPP_SCALER_RGB) | \
+	(1UL << SDE_SSPP_SCALER_QSEED2) | \
+	(1UL << SDE_SSPP_SCALER_QSEED3))
+
+/**
+ * Component indices
+ */
+enum {
+	SDE_SSPP_COMP_0,
+	SDE_SSPP_COMP_1_2,
+	SDE_SSPP_COMP_2,
+	SDE_SSPP_COMP_3,
+
+	SDE_SSPP_COMP_MAX
+};
+
+enum {
+	SDE_FRAME_LINEAR,
+	SDE_FRAME_TILE_A4X,
+	SDE_FRAME_TILE_A5X,
+};
+
+enum sde_hw_filter {
+	SDE_SCALE_FILTER_NEAREST = 0,
+	SDE_SCALE_FILTER_BIL,
+	SDE_SCALE_FILTER_PCMN,
+	SDE_SCALE_FILTER_CA,
+	SDE_SCALE_FILTER_MAX
+};
+
+struct sde_hw_sharp_cfg {
+	u32 strength;
+	u32 edge_thr;
+	u32 smooth_thr;
+	u32 noise_thr;
+};
+
+struct sde_hw_pixel_ext {
+	/* scaling factors are enabled for this input layer */
+	uint8_t enable_pxl_ext;
+
+	int init_phase_x[SDE_MAX_PLANES];
+	int phase_step_x[SDE_MAX_PLANES];
+	int init_phase_y[SDE_MAX_PLANES];
+	int phase_step_y[SDE_MAX_PLANES];
+
+	/*
+	 * Number of pixels extension in left, right, top and bottom direction
+	 * for all color components. This pixel value for each color component
+	 * should be sum of fetch + repeat pixels.
+	 */
+	int num_ext_pxls_left[SDE_MAX_PLANES];
+	int num_ext_pxls_right[SDE_MAX_PLANES];
+	int num_ext_pxls_top[SDE_MAX_PLANES];
+	int num_ext_pxls_btm[SDE_MAX_PLANES];
+
+	/*
+	 * Number of pixels needs to be overfetched in left, right, top and
+	 * bottom directions from source image for scaling.
+	 */
+	int left_ftch[SDE_MAX_PLANES];
+	int right_ftch[SDE_MAX_PLANES];
+	int top_ftch[SDE_MAX_PLANES];
+	int btm_ftch[SDE_MAX_PLANES];
+
+	/*
+	 * Number of pixels needs to be repeated in left, right, top and
+	 * bottom directions for scaling.
+	 */
+	int left_rpt[SDE_MAX_PLANES];
+	int right_rpt[SDE_MAX_PLANES];
+	int top_rpt[SDE_MAX_PLANES];
+	int btm_rpt[SDE_MAX_PLANES];
+
+	uint32_t roi_w[SDE_MAX_PLANES];
+	uint32_t roi_h[SDE_MAX_PLANES];
+
+	/*
+	 * Filter type to be used for scaling in horizontal and vertical
+	 * directions
+	 */
+	enum sde_hw_filter horz_filter[SDE_MAX_PLANES];
+	enum sde_hw_filter vert_filter[SDE_MAX_PLANES];
+
+};
+
+/**
+ * struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
+ * @enable:         detail enhancer enable/disable
+ * @sharpen_level1: sharpening strength for noise
+ * @sharpen_level2: sharpening strength for signal
+ * @ clip:          clip shift
+ * @ limit:         limit value
+ * @ thr_quiet:     quiet threshold
+ * @ thr_dieout:    dieout threshold
+ * @ thr_high:      low threshold
+ * @ thr_high:      high threshold
+ * @ prec_shift:    precision shift
+ * @ adjust_a:      A-coefficients for mapping curve
+ * @ adjust_b:      B-coefficients for mapping curve
+ * @ adjust_c:      C-coefficients for mapping curve
+ */
+struct sde_hw_scaler3_de_cfg {
+	u32 enable;
+	int16_t sharpen_level1;
+	int16_t sharpen_level2;
+	uint16_t clip;
+	uint16_t limit;
+	uint16_t thr_quiet;
+	uint16_t thr_dieout;
+	uint16_t thr_low;
+	uint16_t thr_high;
+	uint16_t prec_shift;
+	int16_t adjust_a[SDE_MAX_DE_CURVES];
+	int16_t adjust_b[SDE_MAX_DE_CURVES];
+	int16_t adjust_c[SDE_MAX_DE_CURVES];
+};
+
+/**
+ * struct sde_hw_scaler3_cfg : QSEEDv3 configuration
+ * @enable:        scaler enable
+ * @dir_en:        direction detection block enable
+ * @ init_phase_x: horizontal initial phase
+ * @ phase_step_x: horizontal phase step
+ * @ init_phase_y: vertical initial phase
+ * @ phase_step_y: vertical phase step
+ * @ preload_x:    horizontal preload value
+ * @ preload_y:    vertical preload value
+ * @ src_width:    source width
+ * @ src_height:   source height
+ * @ dst_width:    destination width
+ * @ dst_height:   destination height
+ * @ y_rgb_filter_cfg: y/rgb plane filter configuration
+ * @ uv_filter_cfg: uv plane filter configuration
+ * @ alpha_filter_cfg: alpha filter configuration
+ * @ blend_cfg:    blend coefficients configuration
+ * @ lut_flag:     scaler LUT update flags
+ *                 0x1 swap LUT bank
+ *                 0x2 update 2D filter LUT
+ *                 0x4 update y circular filter LUT
+ *                 0x8 update uv circular filter LUT
+ *                 0x10 update y separable filter LUT
+ *                 0x20 update uv separable filter LUT
+ * @ dir_lut_idx:  2D filter LUT index
+ * @ y_rgb_cir_lut_idx: y circular filter LUT index
+ * @ uv_cir_lut_idx: uv circular filter LUT index
+ * @ y_rgb_sep_lut_idx: y circular filter LUT index
+ * @ uv_sep_lut_idx: uv separable filter LUT index
+ * @ dir_lut:      pointer to 2D LUT
+ * @ cir_lut:      pointer to circular filter LUT
+ * @ sep_lut:      pointer to separable filter LUT
+ * @ de: detail enhancer configuration
+ */
+struct sde_hw_scaler3_cfg {
+	u32 enable;
+	u32 dir_en;
+	int32_t init_phase_x[SDE_MAX_PLANES];
+	int32_t phase_step_x[SDE_MAX_PLANES];
+	int32_t init_phase_y[SDE_MAX_PLANES];
+	int32_t phase_step_y[SDE_MAX_PLANES];
+
+	u32 preload_x[SDE_MAX_PLANES];
+	u32 preload_y[SDE_MAX_PLANES];
+	u32 src_width[SDE_MAX_PLANES];
+	u32 src_height[SDE_MAX_PLANES];
+
+	u32 dst_width;
+	u32 dst_height;
+
+	u32 y_rgb_filter_cfg;
+	u32 uv_filter_cfg;
+	u32 alpha_filter_cfg;
+	u32 blend_cfg;
+
+	u32 lut_flag;
+	u32 dir_lut_idx;
+
+	u32 y_rgb_cir_lut_idx;
+	u32 uv_cir_lut_idx;
+	u32 y_rgb_sep_lut_idx;
+	u32 uv_sep_lut_idx;
+	u32 *dir_lut;
+	size_t dir_len;
+	u32 *cir_lut;
+	size_t cir_len;
+	u32 *sep_lut;
+	size_t sep_len;
+
+	/*
+	 * Detail enhancer settings
+	 */
+	struct sde_hw_scaler3_de_cfg de;
+};
+
+/**
+ * struct sde_hw_pipe_cfg : Pipe description
+ * @layout:    format layout information for programming buffer to hardware
+ * @src_rect:  src ROI, caller takes into account the different operations
+ *             such as decimation, flip etc to program this field
+ * @dest_rect: destination ROI.
+ * @ horz_decimation : horizontal decimation factor( 0, 2, 4, 8, 16)
+ * @ vert_decimation : vertical decimation factor( 0, 2, 4, 8, 16)
+ *              2: Read 1 line/pixel drop 1 line/pixel
+ *              4: Read 1 line/pixel drop 3  lines/pixels
+ *              8: Read 1 line/pixel drop 7 lines/pixels
+ *              16: Read 1 line/pixel drop 15 line/pixels
+ */
+struct sde_hw_pipe_cfg {
+	struct sde_hw_fmt_layout layout;
+	struct sde_rect src_rect;
+	struct sde_rect dst_rect;
+	u8 horz_decimation;
+	u8 vert_decimation;
+};
+
+/**
+ * struct sde_hw_pipe_qos_cfg : Source pipe QoS configuration
+ * @danger_lut: LUT for generate danger level based on fill level
+ * @safe_lut: LUT for generate safe level based on fill level
+ * @creq_lut: LUT for generate creq level based on fill level
+ * @creq_vblank: creq value generated to vbif during vertical blanking
+ * @danger_vblank: danger value generated during vertical blanking
+ * @vblank_en: enable creq_vblank and danger_vblank during vblank
+ * @danger_safe_en: enable danger safe generation
+ */
+struct sde_hw_pipe_qos_cfg {
+	u32 danger_lut;
+	u32 safe_lut;
+	u32 creq_lut;
+	u32 creq_vblank;
+	u32 danger_vblank;
+	bool vblank_en;
+	bool danger_safe_en;
+};
+
+/**
+ * struct sde_hw_sspp_ops - interface to the SSPP Hw driver functions
+ * Caller must call the init function to get the pipe context for each pipe
+ * Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_sspp_ops {
+	/**
+	 * setup_format - setup pixel format cropping rectangle, flip
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe config structure
+	 * @flags: Extra flags for format config
+	 */
+	void (*setup_format)(struct sde_hw_pipe *ctx,
+			const struct sde_format *fmt, u32 flags);
+
+	/**
+	 * setup_rects - setup pipe ROI rectangles
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe config structure
+	 * @pe_ext: Pointer to pixel ext settings
+	 * @scale_cfg: Pointer to scaler settings
+	 */
+	void (*setup_rects)(struct sde_hw_pipe *ctx,
+			struct sde_hw_pipe_cfg *cfg,
+			struct sde_hw_pixel_ext *pe_ext,
+			void *scale_cfg);
+
+	/**
+	 * setup_sourceaddress - setup pipe source addresses
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe config structure
+	 */
+	void (*setup_sourceaddress)(struct sde_hw_pipe *ctx,
+			struct sde_hw_pipe_cfg *cfg);
+
+	/**
+	 * setup_csc - setup color space coversion
+	 * @ctx: Pointer to pipe context
+	 * @data: Pointer to config structure
+	 */
+	void (*setup_csc)(struct sde_hw_pipe *ctx, struct sde_csc_cfg *data);
+
+	/**
+	 * setup_solidfill - enable/disable colorfill
+	 * @ctx: Pointer to pipe context
+	 * @const_color: Fill color value
+	 * @flags: Pipe flags
+	 */
+	void (*setup_solidfill)(struct sde_hw_pipe *ctx, u32 color);
+
+	/**
+	 * setup_sharpening - setup sharpening
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to config structure
+	 */
+	void (*setup_sharpening)(struct sde_hw_pipe *ctx,
+			struct sde_hw_sharp_cfg *cfg);
+
+
+	/**
+	 * setup_pa_hue(): Setup source hue adjustment
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to hue data
+	 */
+	void (*setup_pa_hue)(struct sde_hw_pipe *ctx, void *cfg);
+
+	/**
+	 * setup_pa_sat(): Setup source saturation adjustment
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to saturation data
+	 */
+	void (*setup_pa_sat)(struct sde_hw_pipe *ctx, void *cfg);
+
+	/**
+	 * setup_pa_val(): Setup source value adjustment
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to value data
+	 */
+	void (*setup_pa_val)(struct sde_hw_pipe *ctx, void *cfg);
+
+	/**
+	 * setup_pa_cont(): Setup source contrast adjustment
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer contrast data
+	 */
+	void (*setup_pa_cont)(struct sde_hw_pipe *ctx, void *cfg);
+
+	/**
+	 * setup_pa_memcolor - setup source color processing
+	 * @ctx: Pointer to pipe context
+	 * @type: Memcolor type (Skin, sky or foliage)
+	 * @cfg: Pointer to memory color config data
+	 */
+	void (*setup_pa_memcolor)(struct sde_hw_pipe *ctx,
+			enum sde_memcolor_type type, void *cfg);
+
+	/**
+	 * setup_igc - setup inverse gamma correction
+	 * @ctx: Pointer to pipe context
+	 */
+	void (*setup_igc)(struct sde_hw_pipe *ctx);
+
+	/**
+	 * setup_danger_safe_lut - setup danger safe LUTs
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe QoS configuration
+	 *
+	 */
+	void (*setup_danger_safe_lut)(struct sde_hw_pipe *ctx,
+			struct sde_hw_pipe_qos_cfg *cfg);
+
+	/**
+	 * setup_creq_lut - setup CREQ LUT
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe QoS configuration
+	 *
+	 */
+	void (*setup_creq_lut)(struct sde_hw_pipe *ctx,
+			struct sde_hw_pipe_qos_cfg *cfg);
+
+	/**
+	 * setup_qos_ctrl - setup QoS control
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to pipe QoS configuration
+	 *
+	 */
+	void (*setup_qos_ctrl)(struct sde_hw_pipe *ctx,
+			struct sde_hw_pipe_qos_cfg *cfg);
+
+	/**
+	 * setup_histogram - setup histograms
+	 * @ctx: Pointer to pipe context
+	 * @cfg: Pointer to histogram configuration
+	 */
+	void (*setup_histogram)(struct sde_hw_pipe *ctx,
+			void *cfg);
+
+	/**
+	 * setup_scaler - setup scaler
+	 * @ctx: Pointer to pipe context
+	 * @pipe_cfg: Pointer to pipe configuration
+	 * @pe_cfg: Pointer to pixel extension configuration
+	 * @scaler_cfg: Pointer to scaler configuration
+	 */
+	void (*setup_scaler)(struct sde_hw_pipe *ctx,
+		struct sde_hw_pipe_cfg *pipe_cfg,
+		struct sde_hw_pixel_ext *pe_cfg,
+		void *scaler_cfg);
+};
+
+/**
+ * struct sde_hw_pipe - pipe description
+ * @base_off:     mdp register mapped offset
+ * @blk_off:      pipe offset relative to mdss offset
+ * @length        length of register block offset
+ * @hwversion     mdss hw version number
+ * @idx:          pipe index
+ * @type :        pipe type, VIG/DMA/RGB/CURSOR, certain operations are not
+ *                supported for each pipe type
+ * @pipe_hw_cap:  pointer to layer_cfg
+ * @highest_bank_bit:
+ * @ops:          pointer to operations possible for this pipe
+ */
+struct sde_hw_pipe {
+	/* base */
+	 struct sde_hw_blk_reg_map hw;
+
+	/* Pipe */
+	enum sde_sspp idx;
+	const struct sde_sspp_cfg *cap;
+	u32 highest_bank_bit;
+
+	/* Ops */
+	struct sde_hw_sspp_ops ops;
+};
+
+/**
+ * sde_hw_sspp_init - initializes the sspp hw driver object.
+ * Should be called once before accessing every pipe.
+ * @idx:  Pipe index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * @catalog : Pointer to mdss catalog data
+ */
+struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
+			void __iomem *addr,
+			struct sde_mdss_cfg *catalog);
+
+/**
+ * sde_hw_sspp_destroy(): Destroys SSPP driver context
+ * should be called during Hw pipe cleanup.
+ * @ctx:  Pointer to SSPP driver context returned by sde_hw_sspp_init
+ */
+void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx);
+
+#endif /*_SDE_HW_SSPP_H */
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
new file mode 100644
index 0000000000000000000000000000000000000000..1a5d469e6e7e0b6f54f07820f22c7333210aaf5a
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -0,0 +1,268 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_top.h"
+
+#define SSPP_SPARE                        0x28
+
+#define FLD_SPLIT_DISPLAY_CMD             BIT(1)
+#define FLD_SMART_PANEL_FREE_RUN          BIT(2)
+#define FLD_INTF_1_SW_TRG_MUX             BIT(4)
+#define FLD_INTF_2_SW_TRG_MUX             BIT(8)
+#define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
+
+#define DANGER_STATUS                     0x360
+#define SAFE_STATUS                       0x364
+
+#define TE_LINE_INTERVAL                  0x3F4
+
+#define TRAFFIC_SHAPER_EN                 BIT(31)
+#define TRAFFIC_SHAPER_RD_CLIENT(num)     (0x030 + (num * 4))
+#define TRAFFIC_SHAPER_WR_CLIENT(num)     (0x060 + (num * 4))
+#define TRAFFIC_SHAPER_FIXPOINT_FACTOR    4
+
+static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
+		struct split_pipe_cfg *cfg)
+{
+	struct sde_hw_blk_reg_map *c = &mdp->hw;
+	u32 upper_pipe = 0;
+	u32 lower_pipe = 0;
+
+	if (!mdp || !cfg)
+		return;
+
+	if (cfg->en) {
+		if (cfg->mode == INTF_MODE_CMD) {
+			lower_pipe = FLD_SPLIT_DISPLAY_CMD;
+			/* interface controlling sw trigger */
+			if (cfg->intf == INTF_2)
+				lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
+			else
+				lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
+
+			/* free run */
+			if (cfg->pp_split_slave != INTF_MAX)
+				lower_pipe = FLD_SMART_PANEL_FREE_RUN;
+
+			upper_pipe = lower_pipe;
+		} else {
+			if (cfg->intf == INTF_2) {
+				lower_pipe = FLD_INTF_1_SW_TRG_MUX;
+				upper_pipe = FLD_INTF_2_SW_TRG_MUX;
+			} else {
+				lower_pipe = FLD_INTF_2_SW_TRG_MUX;
+				upper_pipe = FLD_INTF_1_SW_TRG_MUX;
+			}
+		}
+	}
+
+	SDE_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
+	SDE_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
+	SDE_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
+	SDE_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
+}
+
+static void sde_hw_setup_pp_split(struct sde_hw_mdp *mdp,
+		struct split_pipe_cfg *cfg)
+{
+	u32 ppb_config = 0x0;
+	u32 ppb_control = 0x0;
+
+	if (!mdp || !cfg)
+		return;
+
+	if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
+		ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
+		ppb_config |= BIT(16); /* split enable */
+		ppb_control = BIT(5); /* horz split*/
+	}
+	if (cfg->pp_split_index) {
+		SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
+	} else {
+		SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
+		SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
+	}
+}
+
+static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp,
+		struct cdm_output_cfg *cfg)
+{
+	struct sde_hw_blk_reg_map *c = &mdp->hw;
+	u32 out_ctl = 0;
+
+	if (cfg->wb_en)
+		out_ctl |= BIT(24);
+	else if (cfg->intf_en)
+		out_ctl |= BIT(19);
+
+	SDE_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
+}
+
+static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
+		enum sde_clk_ctrl_type clk_ctrl, bool enable)
+{
+	struct sde_hw_blk_reg_map *c = &mdp->hw;
+	u32 reg_off, bit_off;
+	u32 reg_val, new_val;
+	bool clk_forced_on;
+
+	if (clk_ctrl <= SDE_CLK_CTRL_NONE || clk_ctrl >= SDE_CLK_CTRL_MAX)
+		return false;
+
+	reg_off = mdp->cap->clk_ctrls[clk_ctrl].reg_off;
+	bit_off = mdp->cap->clk_ctrls[clk_ctrl].bit_off;
+
+	reg_val = SDE_REG_READ(c, reg_off);
+
+	if (enable)
+		new_val = reg_val | BIT(bit_off);
+	else
+		new_val = reg_val & ~BIT(bit_off);
+
+	SDE_REG_WRITE(c, reg_off, new_val);
+
+	clk_forced_on = !(reg_val & BIT(bit_off));
+
+	return clk_forced_on;
+}
+
+
+static void sde_hw_get_danger_status(struct sde_hw_mdp *mdp,
+		struct sde_danger_safe_status *status)
+{
+	struct sde_hw_blk_reg_map *c = &mdp->hw;
+	u32 value;
+
+	value = SDE_REG_READ(c, DANGER_STATUS);
+	status->mdp = (value >> 0) & 0x3;
+	status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
+	status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
+	status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
+	status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
+	status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
+	status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
+	status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
+	status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
+	status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
+	status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
+	status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
+	status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
+	status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
+	status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
+	status->wb[WB_0] = 0;
+	status->wb[WB_1] = 0;
+	status->wb[WB_2] = (value >> 2) & 0x3;
+	status->wb[WB_3] = 0;
+}
+
+static void sde_hw_get_safe_status(struct sde_hw_mdp *mdp,
+		struct sde_danger_safe_status *status)
+{
+	struct sde_hw_blk_reg_map *c = &mdp->hw;
+	u32 value;
+
+	value = SDE_REG_READ(c, SAFE_STATUS);
+	status->mdp = (value >> 0) & 0x1;
+	status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
+	status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
+	status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
+	status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
+	status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
+	status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
+	status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
+	status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
+	status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
+	status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
+	status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
+	status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
+	status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
+	status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
+	status->wb[WB_0] = 0;
+	status->wb[WB_1] = 0;
+	status->wb[WB_2] = (value >> 2) & 0x1;
+	status->wb[WB_3] = 0;
+}
+
+static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops,
+		unsigned long cap)
+{
+	ops->setup_split_pipe = sde_hw_setup_split_pipe;
+	ops->setup_pp_split = sde_hw_setup_pp_split;
+	ops->setup_cdm_output = sde_hw_setup_cdm_output;
+	ops->setup_clk_force_ctrl = sde_hw_setup_clk_force_ctrl;
+	ops->get_danger_status = sde_hw_get_danger_status;
+	ops->get_safe_status = sde_hw_get_safe_status;
+}
+
+static const struct sde_mdp_cfg *_top_offset(enum sde_mdp mdp,
+		const struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->mdp_count; i++) {
+		if (mdp == m->mdp[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->mdp[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_TOP;
+			return &m->mdp[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
+		void __iomem *addr,
+		const struct sde_mdss_cfg *m)
+{
+	struct sde_hw_mdp *mdp;
+	const struct sde_mdp_cfg *cfg;
+
+	mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
+	if (!mdp)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _top_offset(idx, m, addr, &mdp->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(mdp);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/*
+	 * Assign ops
+	 */
+	mdp->idx = idx;
+	mdp->cap = cfg;
+	_setup_mdp_ops(&mdp->ops, mdp->cap->features);
+
+	/*
+	 * Perform any default initialization for the intf
+	 */
+
+	return mdp;
+}
+
+void sde_hw_mdp_destroy(struct sde_hw_mdp *mdp)
+{
+	kfree(mdp);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.h b/drivers/gpu/drm/msm/sde/sde_hw_top.h
new file mode 100644
index 0000000000000000000000000000000000000000..780d051e7408036940cdcfafd03f9f74e11d00cf
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.h
@@ -0,0 +1,170 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_TOP_H
+#define _SDE_HW_TOP_H
+
+#include "sde_hw_catalog.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+
+struct sde_hw_mdp;
+
+/**
+ * struct traffic_shaper_cfg: traffic shaper configuration
+ * @en        : enable/disable traffic shaper
+ * @rd_client : true if read client; false if write client
+ * @client_id : client identifier
+ * @bpc_denom : denominator of byte per clk
+ * @bpc_numer : numerator of byte per clk
+ */
+struct traffic_shaper_cfg {
+	bool en;
+	bool rd_client;
+	u32 client_id;
+	u32 bpc_denom;
+	u64 bpc_numer;
+};
+
+/**
+ * struct split_pipe_cfg - pipe configuration for dual display panels
+ * @en        : Enable/disable dual pipe confguration
+ * @mode      : Panel interface mode
+ * @intf      : Interface id for main control path
+ * @pp_split_slave: Slave interface for ping pong split, INTF_MAX to disable
+ * @pp_split_idx:   Ping pong index for ping pong split
+ * @split_flush_en: Allows both the paths to be flushed when master path is
+ *              flushed
+ */
+struct split_pipe_cfg {
+	bool en;
+	enum sde_intf_mode mode;
+	enum sde_intf intf;
+	enum sde_intf pp_split_slave;
+	u32 pp_split_index;
+	bool split_flush_en;
+};
+
+/**
+ * struct cdm_output_cfg: output configuration for cdm
+ * @wb_en     : enable/disable writeback output
+ * @intf_en   : enable/disable interface output
+ */
+struct cdm_output_cfg {
+	bool wb_en;
+	bool intf_en;
+};
+
+/**
+ * struct sde_danger_safe_status: danger and safe status signals
+ * @mdp: top level status
+ * @sspp: source pipe status
+ * @wb: writebck output status
+ */
+struct sde_danger_safe_status {
+	u8 mdp;
+	u8 sspp[SSPP_MAX];
+	u8 wb[WB_MAX];
+};
+
+/**
+ * struct sde_hw_mdp_ops - interface to the MDP TOP Hw driver functions
+ * Assumption is these functions will be called after clocks are enabled.
+ * @setup_split_pipe : Programs the pipe control registers
+ * @setup_pp_split : Programs the pp split control registers
+ * @setup_cdm_output : programs cdm control
+ * @setup_traffic_shaper : programs traffic shaper control
+ */
+struct sde_hw_mdp_ops {
+	/** setup_split_pipe() : Regsiters are not double buffered, thisk
+	 * function should be called before timing control enable
+	 * @mdp  : mdp top context driver
+	 * @cfg  : upper and lower part of pipe configuration
+	 */
+	void (*setup_split_pipe)(struct sde_hw_mdp *mdp,
+			struct split_pipe_cfg *p);
+
+	/** setup_pp_split() : Configure pp split related registers
+	 * @mdp  : mdp top context driver
+	 * @cfg  : upper and lower part of pipe configuration
+	 */
+	void (*setup_pp_split)(struct sde_hw_mdp *mdp,
+			struct split_pipe_cfg *cfg);
+
+	/**
+	 * setup_cdm_output() : Setup selection control of the cdm data path
+	 * @mdp  : mdp top context driver
+	 * @cfg  : cdm output configuration
+	 */
+	void (*setup_cdm_output)(struct sde_hw_mdp *mdp,
+			struct cdm_output_cfg *cfg);
+
+	/**
+	 * setup_traffic_shaper() : Setup traffic shaper control
+	 * @mdp  : mdp top context driver
+	 * @cfg  : traffic shaper configuration
+	 */
+	void (*setup_traffic_shaper)(struct sde_hw_mdp *mdp,
+			struct traffic_shaper_cfg *cfg);
+
+	/**
+	 * setup_clk_force_ctrl - set clock force control
+	 * @mdp: mdp top context driver
+	 * @clk_ctrl: clock to be controlled
+	 * @enable: force on enable
+	 * @return: if the clock is forced-on by this function
+	 */
+	bool (*setup_clk_force_ctrl)(struct sde_hw_mdp *mdp,
+			enum sde_clk_ctrl_type clk_ctrl, bool enable);
+
+	/**
+	 * get_danger_status - get danger status
+	 * @mdp: mdp top context driver
+	 * @status: Pointer to danger safe status
+	 */
+	void (*get_danger_status)(struct sde_hw_mdp *mdp,
+			struct sde_danger_safe_status *status);
+
+	/**
+	 * get_safe_status - get safe status
+	 * @mdp: mdp top context driver
+	 * @status: Pointer to danger safe status
+	 */
+	void (*get_safe_status)(struct sde_hw_mdp *mdp,
+			struct sde_danger_safe_status *status);
+};
+
+struct sde_hw_mdp {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* intf */
+	enum sde_mdp idx;
+	const struct sde_mdp_cfg *cap;
+
+	/* ops */
+	struct sde_hw_mdp_ops ops;
+};
+
+/**
+ * sde_hw_intf_init - initializes the intf driver for the passed interface idx
+ * @idx:  Interface index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * @m:    Pointer to mdss catalog data
+ */
+struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
+		void __iomem *addr,
+		const struct sde_mdss_cfg *m);
+
+void sde_hw_mdp_destroy(struct sde_hw_mdp *mdp);
+
+#endif /*_SDE_HW_TOP_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.c b/drivers/gpu/drm/msm/sde/sde_hw_util.c
new file mode 100644
index 0000000000000000000000000000000000000000..6f52f31a75695ec507d689f452ac16733f9458f1
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.c
@@ -0,0 +1,92 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include "msm_drv.h"
+#include "sde_kms.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+
+/* using a file static variables for debugfs access */
+static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE;
+
+void sde_reg_write(struct sde_hw_blk_reg_map *c,
+		u32 reg_off,
+		u32 val,
+		const char *name)
+{
+	/* don't need to mutex protect this */
+	if (c->log_mask & sde_hw_util_log_mask)
+		SDE_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
+				name, c->blk_off + reg_off, val);
+	writel_relaxed(val, c->base_off + c->blk_off + reg_off);
+}
+
+int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off)
+{
+	return readl_relaxed(c->base_off + c->blk_off + reg_off);
+}
+
+u32 *sde_hw_util_get_log_mask_ptr(void)
+{
+	return &sde_hw_util_log_mask;
+}
+
+void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c,
+		u32 csc_reg_off,
+		struct sde_csc_cfg *data)
+{
+	static const u32 matrix_shift = 7;
+	u32 val;
+
+	/* matrix coeff - convert S15.16 to S4.9 */
+	val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) |
+		(((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16);
+	SDE_REG_WRITE(c, csc_reg_off, val);
+	val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) |
+		(((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0x4, val);
+	val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) |
+		(((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0x8, val);
+	val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) |
+		(((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16);
+	SDE_REG_WRITE(c, csc_reg_off + 0xc, val);
+	val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF;
+	SDE_REG_WRITE(c, csc_reg_off + 0x10, val);
+
+	/* Pre clamp */
+	val = (data->csc_pre_lv[0] << 8) | data->csc_pre_lv[1];
+	SDE_REG_WRITE(c, csc_reg_off + 0x14, val);
+	val = (data->csc_pre_lv[2] << 8) | data->csc_pre_lv[3];
+	SDE_REG_WRITE(c, csc_reg_off + 0x18, val);
+	val = (data->csc_pre_lv[4] << 8) | data->csc_pre_lv[5];
+	SDE_REG_WRITE(c, csc_reg_off + 0x1c, val);
+
+	/* Post clamp */
+	val = (data->csc_post_lv[0] << 8) | data->csc_post_lv[1];
+	SDE_REG_WRITE(c, csc_reg_off + 0x20, val);
+	val = (data->csc_post_lv[2] << 8) | data->csc_post_lv[3];
+	SDE_REG_WRITE(c, csc_reg_off + 0x24, val);
+	val = (data->csc_post_lv[4] << 8) | data->csc_post_lv[5];
+	SDE_REG_WRITE(c, csc_reg_off + 0x28, val);
+
+	/* Pre-Bias */
+	SDE_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
+
+	/* Post-Bias */
+	SDE_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
+	SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.h b/drivers/gpu/drm/msm/sde/sde_hw_util.h
new file mode 100644
index 0000000000000000000000000000000000000000..a4d8be9de90709526cb307ebd18caf5d21b0ca2b
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.h
@@ -0,0 +1,55 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_UTIL_H
+#define _SDE_HW_UTIL_H
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "sde_hw_mdss.h"
+
+/*
+ * This is the common struct maintained by each sub block
+ * for mapping the register offsets in this block to the
+ * absoulute IO address
+ * @base_off:     mdp register mapped offset
+ * @blk_off:      pipe offset relative to mdss offset
+ * @length        length of register block offset
+ * @hwversion     mdss hw version number
+ */
+struct sde_hw_blk_reg_map {
+	void __iomem *base_off;
+	u32 blk_off;
+	u32 length;
+	u32 hwversion;
+	u32 log_mask;
+};
+
+u32 *sde_hw_util_get_log_mask_ptr(void);
+
+void sde_reg_write(struct sde_hw_blk_reg_map *c,
+		u32 reg_off,
+		u32 val,
+		const char *name);
+int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off);
+
+#define SDE_REG_WRITE(c, off, val) sde_reg_write(c, off, val, #off)
+#define SDE_REG_READ(c, off) sde_reg_read(c, off)
+
+void *sde_hw_util_get_dir(void);
+
+void sde_hw_csc_setup(struct sde_hw_blk_reg_map  *c,
+		u32 csc_reg_off,
+		struct sde_csc_cfg *data);
+
+#endif /* _SDE_HW_UTIL_H */
+
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_vbif.c b/drivers/gpu/drm/msm/sde/sde_hw_vbif.c
new file mode 100644
index 0000000000000000000000000000000000000000..76473fa879c5ccce6016dde0aec15fcb6232997b
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_vbif.c
@@ -0,0 +1,165 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_vbif.h"
+
+#define VBIF_VERSION			0x0000
+#define VBIF_CLK_FORCE_CTRL0		0x0008
+#define VBIF_CLK_FORCE_CTRL1		0x000C
+#define VBIF_QOS_REMAP_00		0x0020
+#define VBIF_QOS_REMAP_01		0x0024
+#define VBIF_QOS_REMAP_10		0x0028
+#define VBIF_QOS_REMAP_11		0x002C
+#define VBIF_WRITE_GATHTER_EN		0x00AC
+#define VBIF_IN_RD_LIM_CONF0		0x00B0
+#define VBIF_IN_RD_LIM_CONF1		0x00B4
+#define VBIF_IN_RD_LIM_CONF2		0x00B8
+#define VBIF_IN_WR_LIM_CONF0		0x00C0
+#define VBIF_IN_WR_LIM_CONF1		0x00C4
+#define VBIF_IN_WR_LIM_CONF2		0x00C8
+#define VBIF_OUT_RD_LIM_CONF0		0x00D0
+#define VBIF_OUT_WR_LIM_CONF0		0x00D4
+#define VBIF_XIN_HALT_CTRL0		0x0200
+#define VBIF_XIN_HALT_CTRL1		0x0204
+
+static void sde_hw_set_limit_conf(struct sde_hw_vbif *vbif,
+		u32 xin_id, bool rd, u32 limit)
+{
+	struct sde_hw_blk_reg_map *c = &vbif->hw;
+	u32 reg_val;
+	u32 reg_off;
+	u32 bit_off;
+
+	if (rd)
+		reg_off = VBIF_IN_RD_LIM_CONF0;
+	else
+		reg_off = VBIF_IN_WR_LIM_CONF0;
+
+	reg_off += (xin_id / 4) * 4;
+	bit_off = (xin_id % 4) * 8;
+	reg_val = SDE_REG_READ(c, reg_off);
+	reg_val &= ~(0xFF << bit_off);
+	reg_val |= (limit) << bit_off;
+	SDE_REG_WRITE(c, reg_off, reg_val);
+}
+
+static u32 sde_hw_get_limit_conf(struct sde_hw_vbif *vbif,
+		u32 xin_id, bool rd)
+{
+	struct sde_hw_blk_reg_map *c = &vbif->hw;
+	u32 reg_val;
+	u32 reg_off;
+	u32 bit_off;
+	u32 limit;
+
+	if (rd)
+		reg_off = VBIF_IN_RD_LIM_CONF0;
+	else
+		reg_off = VBIF_IN_WR_LIM_CONF0;
+
+	reg_off += (xin_id / 4) * 4;
+	bit_off = (xin_id % 4) * 8;
+	reg_val = SDE_REG_READ(c, reg_off);
+	limit = (reg_val >> bit_off) & 0xFF;
+
+	return limit;
+}
+
+static void sde_hw_set_halt_ctrl(struct sde_hw_vbif *vbif,
+		u32 xin_id, bool enable)
+{
+	struct sde_hw_blk_reg_map *c = &vbif->hw;
+	u32 reg_val;
+
+	reg_val = SDE_REG_READ(c, VBIF_XIN_HALT_CTRL0);
+
+	if (enable)
+		reg_val |= BIT(xin_id);
+	else
+		reg_val &= ~BIT(xin_id);
+
+	SDE_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);
+}
+
+static bool sde_hw_get_halt_ctrl(struct sde_hw_vbif *vbif,
+		u32 xin_id)
+{
+	struct sde_hw_blk_reg_map *c = &vbif->hw;
+	u32 reg_val;
+
+	reg_val = SDE_REG_READ(c, VBIF_XIN_HALT_CTRL1);
+
+	return (reg_val & BIT(xin_id)) ? true : false;
+}
+
+static void _setup_vbif_ops(struct sde_hw_vbif_ops *ops,
+		unsigned long cap)
+{
+	ops->set_limit_conf = sde_hw_set_limit_conf;
+	ops->get_limit_conf = sde_hw_get_limit_conf;
+	ops->set_halt_ctrl = sde_hw_set_halt_ctrl;
+	ops->get_halt_ctrl = sde_hw_get_halt_ctrl;
+}
+
+static const struct sde_vbif_cfg *_top_offset(enum sde_vbif vbif,
+		const struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->vbif_count; i++) {
+		if (vbif == m->vbif[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->vbif[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_VBIF;
+			return &m->vbif[i];
+		}
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+struct sde_hw_vbif *sde_hw_vbif_init(enum sde_vbif idx,
+		void __iomem *addr,
+		const struct sde_mdss_cfg *m)
+{
+	struct sde_hw_vbif *c;
+	const struct sde_vbif_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _top_offset(idx, m, addr, &c->hw);
+	if (IS_ERR_OR_NULL(cfg)) {
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/*
+	 * Assign ops
+	 */
+	c->idx = idx;
+	c->cap = cfg;
+	_setup_vbif_ops(&c->ops, c->cap->features);
+
+	return c;
+}
+
+void sde_hw_vbif_destroy(struct sde_hw_vbif *vbif)
+{
+	kfree(vbif);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_vbif.h b/drivers/gpu/drm/msm/sde/sde_hw_vbif.h
new file mode 100644
index 0000000000000000000000000000000000000000..de7fac0ed8f2e6b88e1c4b1ad9edf2adfdc69f69
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_vbif.h
@@ -0,0 +1,90 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_VBIF_H
+#define _SDE_HW_VBIF_H
+
+#include "sde_hw_catalog.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_util.h"
+
+struct sde_hw_vbif;
+
+/**
+ * struct sde_hw_vbif_ops : Interface to the VBIF hardware driver functions
+ *  Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_vbif_ops {
+	/**
+	 * set_limit_conf - set transaction limit config
+	 * @vbif: vbif context driver
+	 * @xin_id: client interface identifier
+	 * @rd: true for read limit; false for write limit
+	 * @limit: outstanding transaction limit
+	 */
+	void (*set_limit_conf)(struct sde_hw_vbif *vbif,
+			u32 xin_id, bool rd, u32 limit);
+
+	/**
+	 * get_limit_conf - get transaction limit config
+	 * @vbif: vbif context driver
+	 * @xin_id: client interface identifier
+	 * @rd: true for read limit; false for write limit
+	 * @return: outstanding transaction limit
+	 */
+	u32 (*get_limit_conf)(struct sde_hw_vbif *vbif,
+			u32 xin_id, bool rd);
+
+	/**
+	 * set_halt_ctrl - set halt control
+	 * @vbif: vbif context driver
+	 * @xin_id: client interface identifier
+	 * @enable: halt control enable
+	 */
+	void (*set_halt_ctrl)(struct sde_hw_vbif *vbif,
+			u32 xin_id, bool enable);
+
+	/**
+	 * get_halt_ctrl - get halt control
+	 * @vbif: vbif context driver
+	 * @xin_id: client interface identifier
+	 * @return: halt control enable
+	 */
+	bool (*get_halt_ctrl)(struct sde_hw_vbif *vbif,
+			u32 xin_id);
+};
+
+struct sde_hw_vbif {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* vbif */
+	enum sde_vbif idx;
+	const struct sde_vbif_cfg *cap;
+
+	/* ops */
+	struct sde_hw_vbif_ops ops;
+};
+
+/**
+ * sde_hw_vbif_init - initializes the vbif driver for the passed interface idx
+ * @idx:  Interface index for which driver object is required
+ * @addr: Mapped register io address of MDSS
+ * @m:    Pointer to mdss catalog data
+ */
+struct sde_hw_vbif *sde_hw_vbif_init(enum sde_vbif idx,
+		void __iomem *addr,
+		const struct sde_mdss_cfg *m);
+
+void sde_hw_vbif_destroy(struct sde_hw_vbif *vbif);
+
+#endif /*_SDE_HW_VBIF_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_wb.c b/drivers/gpu/drm/msm/sde/sde_hw_wb.c
new file mode 100644
index 0000000000000000000000000000000000000000..426e9991a6b568af5be721f95906c88cf2aba329
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_wb.c
@@ -0,0 +1,224 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_mdss.h"
+#include "sde_hwio.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_wb.h"
+#include "sde_formats.h"
+
+#define WB_DST_FORMAT			0x000
+#define WB_DST_OP_MODE			0x004
+#define WB_DST_PACK_PATTERN		0x008
+#define WB_DST0_ADDR			0x00C
+#define WB_DST1_ADDR			0x010
+#define WB_DST2_ADDR			0x014
+#define WB_DST3_ADDR			0x018
+#define WB_DST_YSTRIDE0			0x01C
+#define WB_DST_YSTRIDE1			0x020
+#define WB_DST_YSTRIDE1			0x020
+#define WB_DST_DITHER_BITDEPTH		0x024
+#define WB_DST_MATRIX_ROW0		0x030
+#define WB_DST_MATRIX_ROW1		0x034
+#define WB_DST_MATRIX_ROW2		0x038
+#define WB_DST_MATRIX_ROW3		0x03C
+#define WB_DST_WRITE_CONFIG		0x048
+#define WB_ROTATION_DNSCALER		0x050
+#define WB_ROTATOR_PIPE_DOWNSCALER	0x054
+#define WB_N16_INIT_PHASE_X_C03		0x060
+#define WB_N16_INIT_PHASE_X_C12		0x064
+#define WB_N16_INIT_PHASE_Y_C03		0x068
+#define WB_N16_INIT_PHASE_Y_C12		0x06C
+#define WB_OUT_SIZE			0x074
+#define WB_ALPHA_X_VALUE		0x078
+#define WB_CSC_BASE			0x260
+#define WB_DST_ADDR_SW_STATUS		0x2B0
+#define WB_CDP_CTRL			0x2B4
+#define WB_OUT_IMAGE_SIZE		0x2C0
+#define WB_OUT_XY			0x2C4
+
+static struct sde_wb_cfg *_wb_offset(enum sde_wb wb,
+		struct sde_mdss_cfg *m,
+		void __iomem *addr,
+		struct sde_hw_blk_reg_map *b)
+{
+	int i;
+
+	for (i = 0; i < m->wb_count; i++) {
+		if (wb == m->wb[i].id) {
+			b->base_off = addr;
+			b->blk_off = m->wb[i].base;
+			b->hwversion = m->hwversion;
+			b->log_mask = SDE_DBG_MASK_WB;
+			return &m->wb[i];
+		}
+	}
+	return ERR_PTR(-EINVAL);
+}
+
+static void sde_hw_wb_setup_outaddress(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *data)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+
+	SDE_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);
+	SDE_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);
+	SDE_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);
+	SDE_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);
+}
+
+static void sde_hw_wb_setup_format(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *data)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	const struct sde_format *fmt = data->dest.format;
+	u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
+	u32 write_config = 0;
+	u32 opmode = 0;
+	u32 dst_addr_sw = 0;
+	u32 cdp_settings = 0x0;
+
+	chroma_samp = fmt->chroma_sample;
+
+	dst_format = (chroma_samp << 23) |
+			(fmt->fetch_planes << 19) |
+			(fmt->bits[C3_ALPHA] << 6) |
+			(fmt->bits[C2_R_Cr] << 4) |
+			(fmt->bits[C1_B_Cb] << 2) |
+			(fmt->bits[C0_G_Y] << 0);
+
+	if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
+		dst_format |= BIT(8); /* DSTC3_EN */
+		if (!fmt->alpha_enable ||
+				!(ctx->caps->features & BIT(SDE_WB_PIPE_ALPHA)))
+			dst_format |= BIT(14); /* DST_ALPHA_X */
+	}
+
+	if (SDE_FORMAT_IS_YUV(fmt) &&
+			(ctx->caps->features & BIT(SDE_WB_YUV_CONFIG)))
+		dst_format |= BIT(15);
+
+	if (SDE_FORMAT_IS_DX(fmt))
+		dst_format |= BIT(21);
+
+	pattern = (fmt->element[3] << 24) |
+			(fmt->element[2] << 16) |
+			(fmt->element[1] << 8)  |
+			(fmt->element[0] << 0);
+
+	dst_format |= (fmt->unpack_align_msb << 18) |
+			(fmt->unpack_tight << 17) |
+			((fmt->unpack_count - 1) << 12) |
+			((fmt->bpp - 1) << 9);
+
+	ystride0 = data->dest.plane_pitch[0] |
+			(data->dest.plane_pitch[1] << 16);
+	ystride1 = data->dest.plane_pitch[2] |
+			(data->dest.plane_pitch[3] << 16);
+
+	if (data->roi.h && data->roi.w)
+		outsize = (data->roi.h << 16) | data->roi.w;
+	else
+		outsize = (data->dest.height << 16) | data->dest.width;
+
+	if (SDE_FORMAT_IS_UBWC(fmt)) {
+		opmode |= BIT(0);
+		dst_format |= BIT(31);
+		if (ctx->highest_bank_bit)
+			write_config |= (ctx->highest_bank_bit << 8);
+		if (fmt->base.pixel_format == DRM_FORMAT_RGB565)
+			write_config |= 0x8;
+	}
+
+	if (data->is_secure)
+		dst_addr_sw |= BIT(0);
+
+	SDE_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);
+	SDE_REG_WRITE(c, WB_DST_FORMAT, dst_format);
+	SDE_REG_WRITE(c, WB_DST_OP_MODE, opmode);
+	SDE_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern);
+	SDE_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0);
+	SDE_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1);
+	SDE_REG_WRITE(c, WB_OUT_SIZE, outsize);
+	SDE_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);
+	SDE_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw);
+
+	/* Enable CDP */
+	cdp_settings = BIT(0);
+
+	if (!SDE_FORMAT_IS_LINEAR(fmt))
+		cdp_settings |= BIT(1);
+
+	/* Enable 64 transactions if line mode*/
+	if (data->intf_mode == INTF_MODE_WB_LINE)
+		cdp_settings |= BIT(3);
+
+	SDE_REG_WRITE(c, WB_CDP_CTRL, cdp_settings);
+}
+
+static void sde_hw_wb_roi(struct sde_hw_wb *ctx, struct sde_hw_wb_cfg *wb)
+{
+	struct sde_hw_blk_reg_map *c = &ctx->hw;
+	u32 image_size, out_size, out_xy;
+
+	image_size = (wb->dest.height << 16) | wb->dest.width;
+	out_xy = (wb->roi.y << 16) | wb->roi.x;
+	out_size = (wb->roi.h << 16) | wb->roi.w;
+
+	SDE_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size);
+	SDE_REG_WRITE(c, WB_OUT_XY, out_xy);
+	SDE_REG_WRITE(c, WB_OUT_SIZE, out_size);
+}
+
+static void _setup_wb_ops(struct sde_hw_wb_ops *ops,
+	unsigned long features)
+{
+	ops->setup_outaddress = sde_hw_wb_setup_outaddress;
+	ops->setup_outformat = sde_hw_wb_setup_format;
+
+	if (test_bit(SDE_WB_XY_ROI_OFFSET, &features))
+		ops->setup_roi = sde_hw_wb_roi;
+}
+
+struct sde_hw_wb *sde_hw_wb_init(enum sde_wb idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m,
+		struct sde_hw_mdp *hw_mdp)
+{
+	struct sde_hw_wb *c;
+	struct sde_wb_cfg *cfg;
+
+	c = kzalloc(sizeof(*c), GFP_KERNEL);
+	if (!c)
+		return ERR_PTR(-ENOMEM);
+
+	cfg = _wb_offset(idx, m, addr, &c->hw);
+	if (IS_ERR(cfg)) {
+		WARN(1, "Unable to find wb idx=%d\n", idx);
+		kfree(c);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Assign ops */
+	c->idx = idx;
+	c->caps = cfg;
+	_setup_wb_ops(&c->ops, c->caps->features);
+	c->highest_bank_bit = m->mdp[0].highest_bank_bit;
+	c->hw_mdp = hw_mdp;
+
+	return c;
+}
+
+void sde_hw_wb_destroy(struct sde_hw_wb *hw_wb)
+{
+	kfree(hw_wb);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_wb.h b/drivers/gpu/drm/msm/sde/sde_hw_wb.h
new file mode 100644
index 0000000000000000000000000000000000000000..52a5ee5b06a507e4f4ba6c4c64705365931556b7
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_wb.h
@@ -0,0 +1,105 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HW_WB_H
+#define _SDE_HW_WB_H
+
+#include "sde_hw_catalog.h"
+#include "sde_hw_mdss.h"
+#include "sde_hw_top.h"
+#include "sde_hw_util.h"
+
+struct sde_hw_wb;
+
+struct sde_hw_wb_cfg {
+	struct sde_hw_fmt_layout dest;
+	enum sde_intf_mode intf_mode;
+	struct traffic_shaper_cfg ts_cfg;
+	struct sde_rect roi;
+	bool is_secure;
+};
+
+/**
+ *
+ * struct sde_hw_wb_ops : Interface to the wb Hw driver functions
+ *  Assumption is these functions will be called after clocks are enabled
+ */
+struct sde_hw_wb_ops {
+	void (*setup_csc_data)(struct sde_hw_wb *ctx,
+			struct sde_csc_cfg *data);
+
+	void (*setup_outaddress)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_outformat)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_rotator)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_dither)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_cdwn)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_trafficshaper)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+
+	void (*setup_roi)(struct sde_hw_wb *ctx,
+		struct sde_hw_wb_cfg *wb);
+};
+
+/**
+ * struct sde_hw_wb : WB driver object
+ * @struct sde_hw_blk_reg_map *hw;
+ * @idx
+ * @wb_hw_caps
+ * @ops
+ * @highest_bank_bit: GPU highest memory bank bit used
+ * @hw_mdp: MDP top level hardware block
+ */
+struct sde_hw_wb {
+	/* base */
+	struct sde_hw_blk_reg_map hw;
+
+	/* wb path */
+	int idx;
+	const struct sde_wb_cfg *caps;
+
+	/* ops */
+	struct sde_hw_wb_ops ops;
+
+	u32 highest_bank_bit;
+
+	struct sde_hw_mdp *hw_mdp;
+};
+
+/**
+ * sde_hw_wb_init(): Initializes and return writeback hw driver object.
+ * @idx:  wb_path index for which driver object is required
+ * @addr: mapped register io address of MDP
+ * @m :   pointer to mdss catalog data
+ * @hw_mdp: pointer to mdp top hw driver object
+ */
+struct sde_hw_wb *sde_hw_wb_init(enum sde_wb idx,
+		void __iomem *addr,
+		struct sde_mdss_cfg *m,
+		struct sde_hw_mdp *hw_mdp);
+
+/**
+ * sde_hw_wb_destroy(): Destroy writeback hw driver object.
+ * @hw_wb:  Pointer to writeback hw driver object
+ */
+void sde_hw_wb_destroy(struct sde_hw_wb *hw_wb);
+
+#endif /*_SDE_HW_WB_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hwio.h b/drivers/gpu/drm/msm/sde/sde_hwio.h
new file mode 100644
index 0000000000000000000000000000000000000000..c95bace3a0046534eea205fcc71d1361edf4d4f9
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hwio.h
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_HWIO_H
+#define _SDE_HWIO_H
+
+#include "sde_hw_util.h"
+
+/**
+ * MDP TOP block Register and bit fields and defines
+ */
+#define DISP_INTF_SEL                   0x004
+#define INTR_EN                         0x010
+#define INTR_STATUS                     0x014
+#define INTR_CLEAR                      0x018
+#define INTR2_EN                        0x008
+#define INTR2_STATUS                    0x00c
+#define INTR2_CLEAR                     0x02c
+#define HIST_INTR_EN                    0x01c
+#define HIST_INTR_STATUS                0x020
+#define HIST_INTR_CLEAR                 0x024
+#define INTF_INTR_EN                    0x1C0
+#define INTF_INTR_STATUS                0x1C4
+#define INTF_INTR_CLEAR                 0x1C8
+#define SPLIT_DISPLAY_EN                0x2F4
+#define SPLIT_DISPLAY_UPPER_PIPE_CTRL   0x2F8
+#define DSPP_IGC_COLOR0_RAM_LUTN        0x300
+#define DSPP_IGC_COLOR1_RAM_LUTN        0x304
+#define DSPP_IGC_COLOR2_RAM_LUTN        0x308
+#define PPB0_CNTL                       0x330
+#define PPB0_CONFIG                     0x334
+#define PPB1_CNTL                       0x338
+#define PPB1_CONFIG                     0x33C
+#define HW_EVENTS_CTL                   0x37C
+#define CLK_CTRL3                       0x3A8
+#define CLK_STATUS3                     0x3AC
+#define CLK_CTRL4                       0x3B0
+#define CLK_STATUS4                     0x3B4
+#define CLK_CTRL5                       0x3B8
+#define CLK_STATUS5                     0x3BC
+#define CLK_CTRL7                       0x3D0
+#define CLK_STATUS7                     0x3D4
+#define SPLIT_DISPLAY_LOWER_PIPE_CTRL   0x3F0
+#define SPLIT_DISPLAY_TE_LINE_INTERVAL  0x3F4
+#define INTF_SW_RESET_MASK              0x3FC
+#define MDP_OUT_CTL_0                   0x410
+#define MDP_VSYNC_SEL                   0x414
+#define DCE_SEL                         0x450
+
+#endif /*_SDE_HWIO_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_irq.c b/drivers/gpu/drm/msm/sde/sde_irq.c
new file mode 100644
index 0000000000000000000000000000000000000000..909d6df382601150ef6b8cad33169eca9aa72d9c
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_irq.c
@@ -0,0 +1,166 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/kthread.h>
+
+#include "sde_irq.h"
+#include "sde_core_irq.h"
+
+irqreturn_t sde_irq(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	u32 interrupts;
+
+	sde_kms->hw_intr->ops.get_interrupt_sources(sde_kms->hw_intr,
+			&interrupts);
+
+	/*
+	 * Taking care of MDP interrupt
+	 */
+	if (interrupts & IRQ_SOURCE_MDP) {
+		interrupts &= ~IRQ_SOURCE_MDP;
+		sde_core_irq(sde_kms);
+	}
+
+	/*
+	 * Routing all other interrupts to external drivers
+	 */
+	while (interrupts) {
+		irq_hw_number_t hwirq = fls(interrupts) - 1;
+
+		generic_handle_irq(irq_find_mapping(
+				sde_kms->irq_controller.domain, hwirq));
+		interrupts &= ~(1 << hwirq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void sde_hw_irq_mask(struct irq_data *irqd)
+{
+	struct sde_kms *sde_kms;
+
+	if (!irqd || !irq_data_get_irq_chip_data(irqd)) {
+		SDE_ERROR("invalid parameters irqd %d\n", irqd != 0);
+		return;
+	}
+	sde_kms = irq_data_get_irq_chip_data(irqd);
+
+	smp_mb__before_atomic();
+	clear_bit(irqd->hwirq, &sde_kms->irq_controller.enabled_mask);
+	smp_mb__after_atomic();
+}
+
+static void sde_hw_irq_unmask(struct irq_data *irqd)
+{
+	struct sde_kms *sde_kms;
+
+	if (!irqd || !irq_data_get_irq_chip_data(irqd)) {
+		SDE_ERROR("invalid parameters irqd %d\n", irqd != 0);
+		return;
+	}
+	sde_kms = irq_data_get_irq_chip_data(irqd);
+
+	smp_mb__before_atomic();
+	set_bit(irqd->hwirq, &sde_kms->irq_controller.enabled_mask);
+	smp_mb__after_atomic();
+}
+
+static struct irq_chip sde_hw_irq_chip = {
+	.name = "sde",
+	.irq_mask = sde_hw_irq_mask,
+	.irq_unmask = sde_hw_irq_unmask,
+};
+
+static int sde_hw_irqdomain_map(struct irq_domain *domain,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	struct sde_kms *sde_kms;
+	int rc;
+
+	if (!domain || !domain->host_data) {
+		SDE_ERROR("invalid parameters domain %d\n", domain != 0);
+		return -EINVAL;
+	}
+	sde_kms = domain->host_data;
+
+	irq_set_chip_and_handler(irq, &sde_hw_irq_chip, handle_level_irq);
+	rc = irq_set_chip_data(irq, sde_kms);
+
+	return rc;
+}
+
+static struct irq_domain_ops sde_hw_irqdomain_ops = {
+	.map = sde_hw_irqdomain_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+void sde_irq_preinstall(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct device *dev;
+	struct irq_domain *domain;
+
+	if (!sde_kms->dev || !sde_kms->dev->dev) {
+		pr_err("invalid device handles\n");
+		return;
+	}
+	dev = sde_kms->dev->dev;
+
+	domain = irq_domain_add_linear(dev->of_node, 32,
+			&sde_hw_irqdomain_ops, sde_kms);
+	if (!domain) {
+		pr_err("failed to add irq_domain\n");
+		return;
+	}
+
+	sde_kms->irq_controller.enabled_mask = 0;
+	sde_kms->irq_controller.domain = domain;
+
+	sde_core_irq_preinstall(sde_kms);
+}
+
+int sde_irq_postinstall(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	int rc;
+
+	if (!kms) {
+		SDE_ERROR("invalid parameters\n");
+		return -EINVAL;
+	}
+
+	rc = sde_core_irq_postinstall(sde_kms);
+
+	return rc;
+}
+
+void sde_irq_uninstall(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+
+	if (!kms) {
+		SDE_ERROR("invalid parameters\n");
+		return;
+	}
+
+	sde_core_irq_uninstall(sde_kms);
+
+	if (sde_kms->irq_controller.domain) {
+		irq_domain_remove(sde_kms->irq_controller.domain);
+		sde_kms->irq_controller.domain = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_irq.h b/drivers/gpu/drm/msm/sde/sde_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..e10900719f3ff8f9e943c1782659370f59595d3f
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_irq.h
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_IRQ_H__
+#define __SDE_IRQ_H__
+
+#include <linux/kernel.h>
+#include <linux/irqdomain.h>
+
+#include "msm_kms.h"
+
+/**
+ * sde_irq_controller - define MDSS level interrupt controller context
+ * @enabled_mask:	enable status of MDSS level interrupt
+ * @domain:		interrupt domain of this controller
+ */
+struct sde_irq_controller {
+	unsigned long enabled_mask;
+	struct irq_domain *domain;
+};
+
+/**
+ * sde_irq_preinstall - perform pre-installation of MDSS IRQ handler
+ * @kms:		pointer to kms context
+ * @return:		none
+ */
+void sde_irq_preinstall(struct msm_kms *kms);
+
+/**
+ * sde_irq_postinstall - perform post-installation of MDSS IRQ handler
+ * @kms:		pointer to kms context
+ * @return:		0 if success; error code otherwise
+ */
+int sde_irq_postinstall(struct msm_kms *kms);
+
+/**
+ * sde_irq_uninstall - uninstall MDSS IRQ handler
+ * @drm_dev:		pointer to kms context
+ * @return:		none
+ */
+void sde_irq_uninstall(struct msm_kms *kms);
+
+/**
+ * sde_irq - MDSS level IRQ handler
+ * @kms:		pointer to kms context
+ * @return:		interrupt handling status
+ */
+irqreturn_t sde_irq(struct msm_kms *kms);
+
+#endif /* __SDE_IRQ_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
new file mode 100644
index 0000000000000000000000000000000000000000..afe90d16e31d1f946afafa721e1eb2ce75f9a936
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -0,0 +1,1208 @@
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <drm/drm_crtc.h>
+#include <linux/debugfs.h>
+
+#include "msm_drv.h"
+#include "msm_mmu.h"
+
+#include "dsi_display.h"
+#include "dsi_drm.h"
+#include "sde_wb.h"
+
+#include "sde_kms.h"
+#include "sde_core_irq.h"
+#include "sde_formats.h"
+#include "sde_hw_vbif.h"
+#include "sde_vbif.h"
+#include "sde_encoder.h"
+#include "sde_plane.h"
+#include "sde_crtc.h"
+
+#define CREATE_TRACE_POINTS
+#include "sde_trace.h"
+
+static const char * const iommu_ports[] = {
+		"mdp_0",
+};
+
+/**
+ * Controls size of event log buffer. Specified as a power of 2.
+ */
+#define SDE_EVTLOG_SIZE	1024
+
+/*
+ * To enable overall DRM driver logging
+ * # echo 0x2 > /sys/module/drm/parameters/debug
+ *
+ * To enable DRM driver h/w logging
+ * # echo <mask> > /sys/kernel/debug/dri/0/hw_log_mask
+ *
+ * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
+ */
+#define SDE_DEBUGFS_DIR "msm_sde"
+#define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
+
+/**
+ * sdecustom - enable certain driver customizations for sde clients
+ *	Enabling this modifies the standard DRM behavior slightly and assumes
+ *	that the clients have specific knowledge about the modifications that
+ *	are involved, so don't enable this unless you know what you're doing.
+ *
+ *	Parts of the driver that are affected by this setting may be located by
+ *	searching for invocations of the 'sde_is_custom_client()' function.
+ *
+ *	This is disabled by default.
+ */
+static bool sdecustom = true;
+module_param(sdecustom, bool, 0400);
+MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
+
+static int sde_kms_hw_init(struct msm_kms *kms);
+static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
+
+bool sde_is_custom_client(void)
+{
+	return sdecustom;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int _sde_danger_signal_status(struct seq_file *s,
+		bool danger_status)
+{
+	struct sde_kms *kms = (struct sde_kms *)s->private;
+	struct msm_drm_private *priv;
+	struct sde_danger_safe_status status;
+	int i;
+
+	if (!kms || !kms->dev || !kms->dev->dev_private || !kms->hw_mdp) {
+		SDE_ERROR("invalid arg(s)\n");
+		return 0;
+	}
+
+	priv = kms->dev->dev_private;
+	memset(&status, 0, sizeof(struct sde_danger_safe_status));
+
+	sde_power_resource_enable(&priv->phandle, kms->core_client, true);
+	if (danger_status) {
+		seq_puts(s, "\nDanger signal status:\n");
+		if (kms->hw_mdp->ops.get_danger_status)
+			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
+					&status);
+	} else {
+		seq_puts(s, "\nSafe signal status:\n");
+		if (kms->hw_mdp->ops.get_danger_status)
+			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
+					&status);
+	}
+	sde_power_resource_enable(&priv->phandle, kms->core_client, false);
+
+	seq_printf(s, "MDP     :  0x%x\n", status.mdp);
+
+	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
+		seq_printf(s, "SSPP%d   :  0x%x  \t", i - SSPP_VIG0,
+				status.sspp[i]);
+	seq_puts(s, "\n");
+
+	for (i = WB_0; i < WB_MAX; i++)
+		seq_printf(s, "WB%d     :  0x%x  \t", i - WB_0,
+				status.wb[i]);
+	seq_puts(s, "\n");
+
+	return 0;
+}
+
+#define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix)				\
+static int __prefix ## _open(struct inode *inode, struct file *file)	\
+{									\
+	return single_open(file, __prefix ## _show, inode->i_private);	\
+}									\
+static const struct file_operations __prefix ## _fops = {		\
+	.owner = THIS_MODULE,						\
+	.open = __prefix ## _open,					\
+	.release = single_release,					\
+	.read = seq_read,						\
+	.llseek = seq_lseek,						\
+}
+
+static int sde_debugfs_danger_stats_show(struct seq_file *s, void *v)
+{
+	return _sde_danger_signal_status(s, true);
+}
+DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_debugfs_danger_stats);
+
+static int sde_debugfs_safe_stats_show(struct seq_file *s, void *v)
+{
+	return _sde_danger_signal_status(s, false);
+}
+DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_debugfs_safe_stats);
+
+static void sde_debugfs_danger_destroy(struct sde_kms *sde_kms)
+{
+	debugfs_remove_recursive(sde_kms->debugfs_danger);
+	sde_kms->debugfs_danger = NULL;
+}
+
+static int sde_debugfs_danger_init(struct sde_kms *sde_kms,
+		struct dentry *parent)
+{
+	sde_kms->debugfs_danger = debugfs_create_dir("danger",
+			parent);
+	if (!sde_kms->debugfs_danger) {
+		SDE_ERROR("failed to create danger debugfs\n");
+		return -EINVAL;
+	}
+
+	debugfs_create_file("danger_status", 0644, sde_kms->debugfs_danger,
+			sde_kms, &sde_debugfs_danger_stats_fops);
+	debugfs_create_file("safe_status", 0644, sde_kms->debugfs_danger,
+			sde_kms, &sde_debugfs_safe_stats_fops);
+
+	return 0;
+}
+
+static int _sde_debugfs_show_regset32(struct seq_file *s, void *data)
+{
+	struct sde_debugfs_regset32 *regset;
+	struct sde_kms *sde_kms;
+	struct drm_device *dev;
+	struct msm_drm_private *priv;
+	void __iomem *base;
+	uint32_t i, addr;
+
+	if (!s || !s->private)
+		return 0;
+
+	regset = s->private;
+
+	sde_kms = regset->sde_kms;
+	if (!sde_kms || !sde_kms->mmio)
+		return 0;
+
+	dev = sde_kms->dev;
+	if (!dev)
+		return 0;
+
+	priv = dev->dev_private;
+	if (!priv)
+		return 0;
+
+	base = sde_kms->mmio + regset->offset;
+
+	/* insert padding spaces, if needed */
+	if (regset->offset & 0xF) {
+		seq_printf(s, "[%x]", regset->offset & ~0xF);
+		for (i = 0; i < (regset->offset & 0xF); i += 4)
+			seq_puts(s, "         ");
+	}
+
+	if (sde_power_resource_enable(&priv->phandle,
+				sde_kms->core_client, true)) {
+		seq_puts(s, "failed to enable sde clocks\n");
+		return 0;
+	}
+
+	/* main register output */
+	for (i = 0; i < regset->blk_len; i += 4) {
+		addr = regset->offset + i;
+		if ((addr & 0xF) == 0x0)
+			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
+		seq_printf(s, " %08x", readl_relaxed(base + i));
+	}
+	seq_puts(s, "\n");
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+
+	return 0;
+}
+
+static int sde_debugfs_open_regset32(struct inode *inode,
+		struct file *file)
+{
+	return single_open(file, _sde_debugfs_show_regset32, inode->i_private);
+}
+
+static const struct file_operations sde_fops_regset32 = {
+	.open =		sde_debugfs_open_regset32,
+	.read =		seq_read,
+	.llseek =	seq_lseek,
+	.release =	single_release,
+};
+
+void sde_debugfs_setup_regset32(struct sde_debugfs_regset32 *regset,
+		uint32_t offset, uint32_t length, struct sde_kms *sde_kms)
+{
+	if (regset) {
+		regset->offset = offset;
+		regset->blk_len = length;
+		regset->sde_kms = sde_kms;
+	}
+}
+
+void *sde_debugfs_create_regset32(const char *name, umode_t mode,
+		void *parent, struct sde_debugfs_regset32 *regset)
+{
+	if (!name || !regset || !regset->sde_kms || !regset->blk_len)
+		return NULL;
+
+	/* make sure offset is a multiple of 4 */
+	regset->offset = round_down(regset->offset, 4);
+
+	return debugfs_create_file(name, mode, parent,
+			regset, &sde_fops_regset32);
+}
+
+void *sde_debugfs_get_root(struct sde_kms *sde_kms)
+{
+	return sde_kms ? sde_kms->debugfs_root : 0;
+}
+
+static int _sde_debugfs_init(struct sde_kms *sde_kms)
+{
+	void *p;
+
+	p = sde_hw_util_get_log_mask_ptr();
+
+	if (!sde_kms || !p)
+		return -EINVAL;
+
+	if (sde_kms->dev && sde_kms->dev->primary)
+		sde_kms->debugfs_root = sde_kms->dev->primary->debugfs_root;
+	else
+		sde_kms->debugfs_root = debugfs_create_dir(SDE_DEBUGFS_DIR, 0);
+
+	/* allow debugfs_root to be NULL */
+	debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME,
+			0644, sde_kms->debugfs_root, p);
+
+	/* create common folder for debug information */
+	sde_kms->debugfs_debug = debugfs_create_dir("debug",
+			sde_kms->debugfs_root);
+	if (!sde_kms->debugfs_debug)
+		SDE_ERROR("failed to create debugfs debug directory\n");
+
+	sde_debugfs_danger_init(sde_kms, sde_kms->debugfs_debug);
+	sde_debugfs_vbif_init(sde_kms, sde_kms->debugfs_debug);
+
+	return 0;
+}
+
+static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
+{
+	/* don't need to NULL check debugfs_root */
+	if (sde_kms) {
+		sde_debugfs_vbif_destroy(sde_kms);
+		sde_debugfs_danger_destroy(sde_kms);
+		debugfs_remove_recursive(sde_kms->debugfs_debug);
+		sde_kms->debugfs_debug = 0;
+		debugfs_remove_recursive(sde_kms->debugfs_root);
+		sde_kms->debugfs_root = 0;
+	}
+}
+#else
+static void sde_debugfs_danger_destroy(struct sde_kms *sde_kms,
+		struct dentry *parent)
+{
+}
+
+static int sde_debugfs_danger_init(struct sde_kms *sde_kms,
+		struct dentry *parent)
+{
+	return 0;
+}
+#endif
+
+static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev = sde_kms->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+
+	return sde_crtc_vblank(crtc, true);
+}
+
+static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev = sde_kms->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+
+	sde_crtc_vblank(crtc, false);
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+}
+
+static void sde_kms_prepare_commit(struct msm_kms *kms,
+		struct drm_atomic_state *state)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev = sde_kms->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+}
+
+static void sde_kms_commit(struct msm_kms *kms,
+		struct drm_atomic_state *old_state)
+{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *old_crtc_state;
+	int i;
+
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+		if (crtc->state->active) {
+			SDE_EVT32(DRMID(crtc));
+			sde_crtc_commit_kickoff(crtc);
+		}
+	}
+}
+
+static void sde_kms_complete_commit(struct msm_kms *kms,
+		struct drm_atomic_state *old_state)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev = sde_kms->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *old_crtc_state;
+	int i;
+
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i)
+		sde_crtc_complete_commit(crtc, old_crtc_state);
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+
+	SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
+}
+
+static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
+		struct drm_crtc *crtc)
+{
+	struct drm_encoder *encoder;
+	struct drm_device *dev = crtc->dev;
+	int ret;
+
+	if (!kms || !crtc || !crtc->state) {
+		SDE_ERROR("invalid params\n");
+		return;
+	}
+
+	if (!crtc->state->enable) {
+		SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
+		return;
+	}
+
+	if (!crtc->state->active) {
+		SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
+		return;
+	}
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc != crtc)
+			continue;
+		/*
+		 * Wait post-flush if necessary to delay before plane_cleanup
+		 * For example, wait for vsync in case of video mode panels
+		 * This should be a no-op for command mode panels
+		 */
+		SDE_EVT32(DRMID(crtc));
+		ret = sde_encoder_wait_for_commit_done(encoder);
+		if (ret && ret != -EWOULDBLOCK) {
+			SDE_ERROR("wait for commit done returned %d\n", ret);
+			break;
+		}
+	}
+}
+
+static void sde_kms_prepare_fence(struct msm_kms *kms,
+		struct drm_atomic_state *old_state)
+{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *old_crtc_state;
+	int i, rc;
+
+	if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
+		SDE_ERROR("invalid argument(s)\n");
+		return;
+	}
+
+retry:
+	/* attempt to acquire ww mutex for connection */
+	rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
+			       old_state->acquire_ctx);
+
+	if (rc == -EDEADLK) {
+		drm_modeset_backoff(old_state->acquire_ctx);
+		goto retry;
+	}
+
+	/* old_state actually contains updated crtc pointers */
+	for_each_crtc_in_state(old_state, crtc, old_crtc_state, i)
+		sde_crtc_prepare_commit(crtc, old_crtc_state);
+}
+
+/**
+ * _sde_kms_get_displays - query for underlying display handles and cache them
+ * @sde_kms:    Pointer to sde kms structure
+ * Returns:     Zero on success
+ */
+static int _sde_kms_get_displays(struct sde_kms *sde_kms)
+{
+	int rc = -ENOMEM;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde kms\n");
+		return -EINVAL;
+	}
+
+	/* dsi */
+	sde_kms->dsi_displays = NULL;
+	sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
+	if (sde_kms->dsi_display_count) {
+		sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
+				sizeof(void *),
+				GFP_KERNEL);
+		if (!sde_kms->dsi_displays) {
+			SDE_ERROR("failed to allocate dsi displays\n");
+			goto exit_deinit_dsi;
+		}
+		sde_kms->dsi_display_count =
+			dsi_display_get_active_displays(sde_kms->dsi_displays,
+					sde_kms->dsi_display_count);
+	}
+
+	/* wb */
+	sde_kms->wb_displays = NULL;
+	sde_kms->wb_display_count = sde_wb_get_num_of_displays();
+	if (sde_kms->wb_display_count) {
+		sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
+				sizeof(void *),
+				GFP_KERNEL);
+		if (!sde_kms->wb_displays) {
+			SDE_ERROR("failed to allocate wb displays\n");
+			goto exit_deinit_wb;
+		}
+		sde_kms->wb_display_count =
+			wb_display_get_displays(sde_kms->wb_displays,
+					sde_kms->wb_display_count);
+	}
+	return 0;
+
+exit_deinit_wb:
+	kfree(sde_kms->wb_displays);
+	sde_kms->wb_display_count = 0;
+	sde_kms->wb_displays = NULL;
+
+exit_deinit_dsi:
+	kfree(sde_kms->dsi_displays);
+	sde_kms->dsi_display_count = 0;
+	sde_kms->dsi_displays = NULL;
+	return rc;
+}
+
+/**
+ * _sde_kms_release_displays - release cache of underlying display handles
+ * @sde_kms:    Pointer to sde kms structure
+ */
+static void _sde_kms_release_displays(struct sde_kms *sde_kms)
+{
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde kms\n");
+		return;
+	}
+
+	kfree(sde_kms->wb_displays);
+	sde_kms->wb_displays = NULL;
+	sde_kms->wb_display_count = 0;
+
+	kfree(sde_kms->dsi_displays);
+	sde_kms->dsi_displays = NULL;
+	sde_kms->dsi_display_count = 0;
+}
+
+/**
+ * _sde_kms_setup_displays - create encoders, bridges and connectors
+ *                           for underlying displays
+ * @dev:        Pointer to drm device structure
+ * @priv:       Pointer to private drm device data
+ * @sde_kms:    Pointer to sde kms structure
+ * Returns:     Zero on success
+ */
+static int _sde_kms_setup_displays(struct drm_device *dev,
+		struct msm_drm_private *priv,
+		struct sde_kms *sde_kms)
+{
+	static const struct sde_connector_ops dsi_ops = {
+		.post_init =  dsi_conn_post_init,
+		.detect =     dsi_conn_detect,
+		.get_modes =  dsi_connector_get_modes,
+		.mode_valid = dsi_conn_mode_valid,
+		.get_info =   dsi_display_get_info,
+		.set_backlight = dsi_display_set_backlight
+	};
+	static const struct sde_connector_ops wb_ops = {
+		.post_init =    sde_wb_connector_post_init,
+		.detect =       sde_wb_connector_detect,
+		.get_modes =    sde_wb_connector_get_modes,
+		.set_property = sde_wb_connector_set_property,
+		.get_info =     sde_wb_get_info,
+	};
+	struct msm_display_info info;
+	struct drm_encoder *encoder;
+	void *display, *connector;
+	int i, max_encoders;
+	int rc = 0;
+
+	if (!dev || !priv || !sde_kms) {
+		SDE_ERROR("invalid argument(s)\n");
+		return -EINVAL;
+	}
+
+	max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count;
+	if (max_encoders > ARRAY_SIZE(priv->encoders)) {
+		max_encoders = ARRAY_SIZE(priv->encoders);
+		SDE_ERROR("capping number of displays to %d", max_encoders);
+	}
+
+	/* dsi */
+	for (i = 0; i < sde_kms->dsi_display_count &&
+		priv->num_encoders < max_encoders; ++i) {
+		display = sde_kms->dsi_displays[i];
+		encoder = NULL;
+
+		memset(&info, 0x0, sizeof(info));
+		rc = dsi_display_get_info(&info, display);
+		if (rc) {
+			SDE_ERROR("dsi get_info %d failed\n", i);
+			continue;
+		}
+
+		encoder = sde_encoder_init(dev, &info);
+		if (IS_ERR_OR_NULL(encoder)) {
+			SDE_ERROR("encoder init failed for dsi %d\n", i);
+			continue;
+		}
+
+		rc = dsi_display_drm_bridge_init(display, encoder);
+		if (rc) {
+			SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
+			sde_encoder_destroy(encoder);
+			continue;
+		}
+
+		connector = sde_connector_init(dev,
+					encoder,
+					0,
+					display,
+					&dsi_ops,
+					DRM_CONNECTOR_POLL_HPD,
+					DRM_MODE_CONNECTOR_DSI);
+		if (connector) {
+			priv->encoders[priv->num_encoders++] = encoder;
+		} else {
+			SDE_ERROR("dsi %d connector init failed\n", i);
+			dsi_display_drm_bridge_deinit(display);
+			sde_encoder_destroy(encoder);
+		}
+	}
+
+	/* wb */
+	for (i = 0; i < sde_kms->wb_display_count &&
+		priv->num_encoders < max_encoders; ++i) {
+		display = sde_kms->wb_displays[i];
+		encoder = NULL;
+
+		memset(&info, 0x0, sizeof(info));
+		rc = sde_wb_get_info(&info, display);
+		if (rc) {
+			SDE_ERROR("wb get_info %d failed\n", i);
+			continue;
+		}
+
+		encoder = sde_encoder_init(dev, &info);
+		if (IS_ERR_OR_NULL(encoder)) {
+			SDE_ERROR("encoder init failed for wb %d\n", i);
+			continue;
+		}
+
+		rc = sde_wb_drm_init(display, encoder);
+		if (rc) {
+			SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
+			sde_encoder_destroy(encoder);
+			continue;
+		}
+
+		connector = sde_connector_init(dev,
+				encoder,
+				0,
+				display,
+				&wb_ops,
+				DRM_CONNECTOR_POLL_HPD,
+				DRM_MODE_CONNECTOR_VIRTUAL);
+		if (connector) {
+			priv->encoders[priv->num_encoders++] = encoder;
+		} else {
+			SDE_ERROR("wb %d connector init failed\n", i);
+			sde_wb_drm_deinit(display);
+			sde_encoder_destroy(encoder);
+		}
+	}
+
+	return 0;
+}
+
+static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
+{
+	struct msm_drm_private *priv;
+	int i;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde_kms\n");
+		return;
+	} else if (!sde_kms->dev) {
+		SDE_ERROR("invalid dev\n");
+		return;
+	} else if (!sde_kms->dev->dev_private) {
+		SDE_ERROR("invalid dev_private\n");
+		return;
+	}
+	priv = sde_kms->dev->dev_private;
+
+	for (i = 0; i < priv->num_crtcs; i++)
+		priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
+	priv->num_crtcs = 0;
+
+	for (i = 0; i < priv->num_planes; i++)
+		priv->planes[i]->funcs->destroy(priv->planes[i]);
+	priv->num_planes = 0;
+
+	for (i = 0; i < priv->num_connectors; i++)
+		priv->connectors[i]->funcs->destroy(priv->connectors[i]);
+	priv->num_connectors = 0;
+
+	for (i = 0; i < priv->num_encoders; i++)
+		priv->encoders[i]->funcs->destroy(priv->encoders[i]);
+	priv->num_encoders = 0;
+
+	_sde_kms_release_displays(sde_kms);
+}
+
+static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
+{
+	struct drm_device *dev;
+	struct drm_plane *primary_planes[MAX_PLANES], *plane;
+	struct drm_crtc *crtc;
+
+	struct msm_drm_private *priv;
+	struct sde_mdss_cfg *catalog;
+
+	int primary_planes_idx, i, ret;
+	int max_crtc_count, max_plane_count;
+
+	if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
+		SDE_ERROR("invalid sde_kms\n");
+		return -EINVAL;
+	}
+
+	dev = sde_kms->dev;
+	priv = dev->dev_private;
+	catalog = sde_kms->catalog;
+
+	/*
+	 * Query for underlying display drivers, and create connectors,
+	 * bridges and encoders for them.
+	 */
+	if (!_sde_kms_get_displays(sde_kms))
+		(void)_sde_kms_setup_displays(dev, priv, sde_kms);
+
+	max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
+	max_plane_count = min_t(u32, catalog->sspp_count, MAX_PLANES);
+
+	/* Create the planes */
+	primary_planes_idx = 0;
+	for (i = 0; i < max_plane_count; i++) {
+		bool primary = true;
+
+		if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
+			|| primary_planes_idx >= max_crtc_count)
+			primary = false;
+
+		plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
+				(1UL << max_crtc_count) - 1);
+		if (IS_ERR(plane)) {
+			SDE_ERROR("sde_plane_init failed\n");
+			ret = PTR_ERR(plane);
+			goto fail;
+		}
+		priv->planes[priv->num_planes++] = plane;
+
+		if (primary)
+			primary_planes[primary_planes_idx++] = plane;
+	}
+
+	max_crtc_count = min(max_crtc_count, primary_planes_idx);
+
+	/* Create one CRTC per encoder */
+	for (i = 0; i < max_crtc_count; i++) {
+		crtc = sde_crtc_init(dev, primary_planes[i]);
+		if (IS_ERR(crtc)) {
+			ret = PTR_ERR(crtc);
+			goto fail;
+		}
+		priv->crtcs[priv->num_crtcs++] = crtc;
+	}
+
+	if (sde_is_custom_client()) {
+		/* All CRTCs are compatible with all planes */
+		for (i = 0; i < priv->num_planes; i++)
+			priv->planes[i]->possible_crtcs =
+				(1 << priv->num_crtcs) - 1;
+	}
+
+	/* All CRTCs are compatible with all encoders */
+	for (i = 0; i < priv->num_encoders; i++)
+		priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
+
+	return 0;
+fail:
+	_sde_kms_drm_obj_destroy(sde_kms);
+	return ret;
+}
+
+static int sde_kms_postinit(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev;
+
+	if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
+		SDE_ERROR("invalid sde_kms\n");
+		return -EINVAL;
+	}
+
+	dev = sde_kms->dev;
+
+	/*
+	 * Allow vblank interrupt to be disabled by drm vblank timer.
+	 */
+	dev->vblank_disable_allowed = true;
+
+	return 0;
+}
+
+static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
+		struct drm_encoder *encoder)
+{
+	return rate;
+}
+
+static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
+		struct platform_device *pdev)
+{
+	struct drm_device *dev;
+	struct msm_drm_private *priv;
+	int i;
+
+	if (!sde_kms || !pdev)
+		return;
+
+	dev = sde_kms->dev;
+	if (!dev)
+		return;
+
+	priv = dev->dev_private;
+	if (!priv)
+		return;
+
+	if (sde_kms->hw_intr)
+		sde_hw_intr_destroy(sde_kms->hw_intr);
+	sde_kms->hw_intr = NULL;
+
+	_sde_kms_release_displays(sde_kms);
+
+	/* safe to call these more than once during shutdown */
+	_sde_debugfs_destroy(sde_kms);
+	_sde_kms_mmu_destroy(sde_kms);
+	sde_core_perf_destroy(&sde_kms->perf);
+
+	if (sde_kms->catalog) {
+		for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
+			u32 vbif_idx = sde_kms->catalog->vbif[i].id;
+
+			if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
+				sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
+		}
+	}
+
+	if (sde_kms->rm_init)
+		sde_rm_destroy(&sde_kms->rm);
+	sde_kms->rm_init = false;
+
+	if (sde_kms->catalog)
+		sde_hw_catalog_deinit(sde_kms->catalog);
+	sde_kms->catalog = NULL;
+
+	if (sde_kms->core_client)
+		sde_power_client_destroy(&priv->phandle, sde_kms->core_client);
+	sde_kms->core_client = NULL;
+
+	if (sde_kms->vbif[VBIF_NRT])
+		msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
+	sde_kms->vbif[VBIF_NRT] = NULL;
+
+	if (sde_kms->vbif[VBIF_RT])
+		msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
+	sde_kms->vbif[VBIF_RT] = NULL;
+
+	if (sde_kms->mmio)
+		msm_iounmap(pdev, sde_kms->mmio);
+	sde_kms->mmio = NULL;
+}
+
+static void sde_kms_destroy(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms;
+	struct drm_device *dev;
+
+	if (!kms) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+
+	sde_kms = to_sde_kms(kms);
+	dev = sde_kms->dev;
+	if (!dev) {
+		SDE_ERROR("invalid device\n");
+		return;
+	}
+
+	_sde_kms_hw_destroy(sde_kms, dev->platformdev);
+	kfree(sde_kms);
+}
+
+static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
+{
+	struct sde_kms *sde_kms = to_sde_kms(kms);
+	struct drm_device *dev = sde_kms->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+	unsigned i;
+
+	for (i = 0; i < priv->num_crtcs; i++)
+		sde_crtc_cancel_pending_flip(priv->crtcs[i], file);
+}
+
+static const struct msm_kms_funcs kms_funcs = {
+	.hw_init         = sde_kms_hw_init,
+	.postinit        = sde_kms_postinit,
+	.irq_preinstall  = sde_irq_preinstall,
+	.irq_postinstall = sde_irq_postinstall,
+	.irq_uninstall   = sde_irq_uninstall,
+	.irq             = sde_irq,
+	.preclose        = sde_kms_preclose,
+	.prepare_fence   = sde_kms_prepare_fence,
+	.prepare_commit  = sde_kms_prepare_commit,
+	.commit          = sde_kms_commit,
+	.complete_commit = sde_kms_complete_commit,
+	.wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
+	.enable_vblank   = sde_kms_enable_vblank,
+	.disable_vblank  = sde_kms_disable_vblank,
+	.check_modified_format = sde_format_check_modified_format,
+	.get_format      = sde_get_msm_format,
+	.round_pixclk    = sde_kms_round_pixclk,
+	.destroy         = sde_kms_destroy,
+};
+
+/* the caller api needs to turn on clock before calling it */
+static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
+{
+	sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
+}
+
+static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
+{
+	struct msm_mmu *mmu;
+	int i;
+
+	for (i = ARRAY_SIZE(sde_kms->mmu_id) - 1; i >= 0; i--) {
+		if (!sde_kms->mmu[i])
+			continue;
+
+		mmu = sde_kms->mmu[i];
+		msm_unregister_mmu(sde_kms->dev, mmu);
+		mmu->funcs->detach(mmu, (const char **)iommu_ports,
+				ARRAY_SIZE(iommu_ports));
+		mmu->funcs->destroy(mmu);
+		sde_kms->mmu[i] = 0;
+		sde_kms->mmu_id[i] = 0;
+	}
+
+	return 0;
+}
+
+static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
+{
+	struct msm_mmu *mmu;
+	int i, ret;
+
+	for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
+		mmu = msm_smmu_new(sde_kms->dev->dev, i);
+		if (IS_ERR(mmu)) {
+			/* MMU's can be optional depending on platform */
+			ret = PTR_ERR(mmu);
+			DRM_INFO("failed to init iommu id %d: rc: %d\n", i,
+					ret);
+			continue;
+		}
+
+		ret = mmu->funcs->attach(mmu, (const char **)iommu_ports,
+				ARRAY_SIZE(iommu_ports));
+		if (ret) {
+			SDE_ERROR("failed to attach iommu %d: %d\n", i, ret);
+			mmu->funcs->destroy(mmu);
+			goto fail;
+		}
+
+		sde_kms->mmu_id[i] = msm_register_mmu(sde_kms->dev, mmu);
+		if (sde_kms->mmu_id[i] < 0) {
+			ret = sde_kms->mmu_id[i];
+			SDE_ERROR("failed to register sde iommu %d: %d\n",
+					i, ret);
+			mmu->funcs->detach(mmu, (const char **)iommu_ports,
+					ARRAY_SIZE(iommu_ports));
+			goto fail;
+		}
+
+		sde_kms->mmu[i] = mmu;
+	}
+
+	return 0;
+fail:
+	_sde_kms_mmu_destroy(sde_kms);
+
+	return ret;
+}
+
+static int sde_kms_hw_init(struct msm_kms *kms)
+{
+	struct sde_kms *sde_kms;
+	struct drm_device *dev;
+	struct msm_drm_private *priv;
+	int i, rc = -EINVAL;
+
+	if (!kms) {
+		SDE_ERROR("invalid kms\n");
+		goto end;
+	}
+
+	sde_kms = to_sde_kms(kms);
+	dev = sde_kms->dev;
+	if (!dev || !dev->platformdev) {
+		SDE_ERROR("invalid device\n");
+		goto end;
+	}
+
+	priv = dev->dev_private;
+	if (!priv) {
+		SDE_ERROR("invalid private data\n");
+		goto end;
+	}
+
+	sde_kms->mmio = msm_ioremap(dev->platformdev, "mdp_phys", "SDE");
+	if (IS_ERR(sde_kms->mmio)) {
+		rc = PTR_ERR(sde_kms->mmio);
+		SDE_ERROR("mdp register memory map failed: %d\n", rc);
+		sde_kms->mmio = NULL;
+		goto error;
+	}
+	DRM_INFO("mapped mdp address space @%p\n", sde_kms->mmio);
+
+	sde_kms->vbif[VBIF_RT] = msm_ioremap(dev->platformdev,
+			"vbif_phys", "VBIF");
+	if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
+		rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
+		SDE_ERROR("vbif register memory map failed: %d\n", rc);
+		sde_kms->vbif[VBIF_RT] = NULL;
+		goto error;
+	}
+
+	sde_kms->vbif[VBIF_NRT] = msm_ioremap(dev->platformdev,
+			"vbif_nrt_phys", "VBIF_NRT");
+	if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
+		sde_kms->vbif[VBIF_NRT] = NULL;
+		SDE_DEBUG("VBIF NRT is not defined");
+	}
+
+	sde_kms->core_client = sde_power_client_create(&priv->phandle, "core");
+	if (IS_ERR_OR_NULL(sde_kms->core_client)) {
+		rc = PTR_ERR(sde_kms->core_client);
+		SDE_ERROR("sde power client create failed: %d\n", rc);
+		sde_kms->core_client = NULL;
+		goto error;
+	}
+
+	rc = sde_power_resource_enable(&priv->phandle, sde_kms->core_client,
+		true);
+	if (rc) {
+		SDE_ERROR("resource enable failed: %d\n", rc);
+		goto error;
+	}
+
+	_sde_kms_core_hw_rev_init(sde_kms);
+
+	pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
+
+	sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
+	if (IS_ERR_OR_NULL(sde_kms->catalog)) {
+		rc = PTR_ERR(sde_kms->catalog);
+		SDE_ERROR("catalog init failed: %d\n", rc);
+		sde_kms->catalog = NULL;
+		goto power_error;
+	}
+
+	rc = sde_rm_init(&sde_kms->rm, sde_kms->catalog, sde_kms->mmio,
+			sde_kms->dev);
+	if (rc) {
+		SDE_ERROR("rm init failed: %d\n", rc);
+		goto power_error;
+	}
+
+	sde_kms->rm_init = true;
+
+	sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
+	if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
+		rc = PTR_ERR(sde_kms->hw_mdp);
+		SDE_ERROR("failed to get hw_mdp: %d\n", rc);
+		sde_kms->hw_mdp = NULL;
+		goto power_error;
+	}
+
+	for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
+		u32 vbif_idx = sde_kms->catalog->vbif[i].id;
+
+		sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
+				sde_kms->vbif[vbif_idx], sde_kms->catalog);
+		if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
+			rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
+			SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
+			sde_kms->hw_vbif[vbif_idx] = NULL;
+			goto power_error;
+		}
+	}
+
+	/*
+	 * Now we need to read the HW catalog and initialize resources such as
+	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
+	 */
+	rc = _sde_kms_mmu_init(sde_kms);
+	if (rc) {
+		SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
+		goto power_error;
+	}
+
+	/*
+	 * NOTE: Calling sde_debugfs_init here so that the drm_minor device for
+	 *       'primary' is already created.
+	 */
+	rc = _sde_debugfs_init(sde_kms);
+	if (rc) {
+		SDE_ERROR("sde_debugfs init failed: %d\n", rc);
+		goto power_error;
+	}
+
+	rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
+			&priv->phandle, priv->pclient, "core_clk_src",
+			sde_kms->debugfs_debug);
+	if (rc) {
+		SDE_ERROR("failed to init perf %d\n", rc);
+		goto perf_err;
+	}
+
+	/*
+	 * _sde_kms_drm_obj_init should create the DRM related objects
+	 * i.e. CRTCs, planes, encoders, connectors and so forth
+	 */
+	rc = _sde_kms_drm_obj_init(sde_kms);
+	if (rc) {
+		SDE_ERROR("modeset init failed: %d\n", rc);
+		goto drm_obj_init_err;
+	}
+
+	dev->mode_config.min_width = 0;
+	dev->mode_config.min_height = 0;
+
+	/*
+	 * max crtc width is equal to the max mixer width * 2 and max height is
+	 * is 4K
+	 */
+	dev->mode_config.max_width = sde_kms->catalog->max_mixer_width * 2;
+	dev->mode_config.max_height = 4096;
+
+	/*
+	 * Support format modifiers for compression etc.
+	 */
+	dev->mode_config.allow_fb_modifiers = true;
+
+	sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
+	if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
+		rc = PTR_ERR(sde_kms->hw_intr);
+		SDE_ERROR("hw_intr init failed: %d\n", rc);
+		sde_kms->hw_intr = NULL;
+		goto hw_intr_init_err;
+	}
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+	return 0;
+
+hw_intr_init_err:
+	_sde_kms_drm_obj_destroy(sde_kms);
+drm_obj_init_err:
+	sde_core_perf_destroy(&sde_kms->perf);
+perf_err:
+power_error:
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+error:
+	_sde_kms_hw_destroy(sde_kms, dev->platformdev);
+end:
+	return rc;
+}
+
+struct msm_kms *sde_kms_init(struct drm_device *dev)
+{
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	if (!dev || !dev->dev_private) {
+		SDE_ERROR("drm device node invalid\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	priv = dev->dev_private;
+
+	sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
+	if (!sde_kms) {
+		SDE_ERROR("failed to allocate sde kms\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	msm_kms_init(&sde_kms->base, &kms_funcs);
+	sde_kms->dev = dev;
+
+	return &sde_kms->base;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.h b/drivers/gpu/drm/msm/sde/sde_kms.h
new file mode 100644
index 0000000000000000000000000000000000000000..bf127ffe9eb6a3b5889bc4ef8bc66840275cbdcb
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_kms.h
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SDE_KMS_H__
+#define __SDE_KMS_H__
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_mmu.h"
+#include "sde_dbg.h"
+#include "sde_hw_catalog.h"
+#include "sde_hw_ctl.h"
+#include "sde_hw_lm.h"
+#include "sde_hw_interrupts.h"
+#include "sde_hw_wb.h"
+#include "sde_hw_top.h"
+#include "sde_rm.h"
+#include "sde_power_handle.h"
+#include "sde_irq.h"
+#include "sde_core_perf.h"
+
+#define DRMID(x) ((x) ? (x)->base.id : -1)
+
+/**
+ * SDE_DEBUG - macro for kms/plane/crtc/encoder/connector logs
+ * @fmt: Pointer to format string
+ */
+#define SDE_DEBUG(fmt, ...)                                                \
+	do {                                                               \
+		if (unlikely(drm_debug & DRM_UT_KMS))                      \
+			drm_ut_debug_printk(__func__, fmt, ##__VA_ARGS__); \
+		else                                                       \
+			pr_debug(fmt, ##__VA_ARGS__);                      \
+	} while (0)
+
+/**
+ * SDE_DEBUG_DRIVER - macro for hardware driver logging
+ * @fmt: Pointer to format string
+ */
+#define SDE_DEBUG_DRIVER(fmt, ...)                                         \
+	do {                                                               \
+		if (unlikely(drm_debug & DRM_UT_DRIVER))                   \
+			drm_ut_debug_printk(__func__, fmt, ##__VA_ARGS__); \
+		else                                                       \
+			pr_debug(fmt, ##__VA_ARGS__);                      \
+	} while (0)
+
+#define SDE_ERROR(fmt, ...) pr_err("[sde error]" fmt, ##__VA_ARGS__)
+
+#define POPULATE_RECT(rect, a, b, c, d, Q16_flag) \
+	do {						\
+		(rect)->x = (Q16_flag) ? (a) >> 16 : (a);    \
+		(rect)->y = (Q16_flag) ? (b) >> 16 : (b);    \
+		(rect)->w = (Q16_flag) ? (c) >> 16 : (c);    \
+		(rect)->h = (Q16_flag) ? (d) >> 16 : (d);    \
+	} while (0)
+
+#define CHECK_LAYER_BOUNDS(offset, size, max_size) \
+	(((size) > (max_size)) || ((offset) > ((max_size) - (size))))
+
+/**
+ * ktime_compare_safe - compare two ktime structures
+ *	This macro is similar to the standard ktime_compare() function, but
+ *	attempts to also handle ktime overflows.
+ * @A: First ktime value
+ * @B: Second ktime value
+ * Returns: -1 if A < B, 0 if A == B, 1 if A > B
+ */
+#define ktime_compare_safe(A, B) \
+	ktime_compare(ktime_sub((A), (B)), ktime_set(0, 0))
+
+#define SDE_NAME_SIZE  12
+
+/*
+ * struct sde_irq_callback - IRQ callback handlers
+ * @list: list to callback
+ * @func: intr handler
+ * @arg: argument for the handler
+ */
+struct sde_irq_callback {
+	struct list_head list;
+	void (*func)(void *arg, int irq_idx);
+	void *arg;
+};
+
+/**
+ * struct sde_irq: IRQ structure contains callback registration info
+ * @total_irq:    total number of irq_idx obtained from HW interrupts mapping
+ * @irq_cb_tbl:   array of IRQ callbacks setting
+ * @enable_counts array of IRQ enable counts
+ * @cb_lock:      callback lock
+ * @debugfs_file: debugfs file for irq statistics
+ */
+struct sde_irq {
+	u32 total_irqs;
+	struct list_head *irq_cb_tbl;
+	atomic_t *enable_counts;
+	atomic_t *irq_counts;
+	spinlock_t cb_lock;
+	struct dentry *debugfs_file;
+};
+
+struct sde_kms {
+	struct msm_kms base;
+	struct drm_device *dev;
+	int core_rev;
+	struct sde_mdss_cfg *catalog;
+
+	struct msm_mmu *mmu[MSM_SMMU_DOMAIN_MAX];
+	int mmu_id[MSM_SMMU_DOMAIN_MAX];
+	struct sde_power_client *core_client;
+
+	/* directory entry for debugfs */
+	void *debugfs_root;
+	struct dentry *debugfs_debug;
+	struct dentry *debugfs_danger;
+	struct dentry *debugfs_vbif;
+
+	/* io/register spaces: */
+	void __iomem *mmio, *vbif[VBIF_MAX];
+
+	struct regulator *vdd;
+	struct regulator *mmagic;
+	struct regulator *venus;
+
+	struct sde_irq_controller irq_controller;
+
+	struct sde_hw_intr *hw_intr;
+	struct sde_irq irq_obj;
+
+	struct sde_core_perf perf;
+
+	struct sde_rm rm;
+	bool rm_init;
+
+	struct sde_hw_vbif *hw_vbif[VBIF_MAX];
+	struct sde_hw_mdp *hw_mdp;
+	int dsi_display_count;
+	void **dsi_displays;
+	int wb_display_count;
+	void **wb_displays;
+
+	bool has_danger_ctrl;
+};
+
+struct vsync_info {
+	u32 frame_count;
+	u32 line_count;
+};
+
+#define to_sde_kms(x) container_of(x, struct sde_kms, base)
+
+/**
+ * sde_is_custom_client - whether or not to enable non-standard customizations
+ *
+ * Return: Whether or not the 'sdeclient' module parameter was set on boot up
+ */
+bool sde_is_custom_client(void);
+
+/**
+ * Debugfs functions - extra helper functions for debugfs support
+ *
+ * Main debugfs documentation is located at,
+ *
+ * Documentation/filesystems/debugfs.txt
+ *
+ * @sde_debugfs_setup_regset32: Initialize data for sde_debugfs_create_regset32
+ * @sde_debugfs_create_regset32: Create 32-bit register dump file
+ * @sde_debugfs_get_root: Get root dentry for SDE_KMS's debugfs node
+ */
+
+/**
+ * Companion structure for sde_debugfs_create_regset32. Do not initialize the
+ * members of this structure explicitly; use sde_debugfs_setup_regset32 instead.
+ */
+struct sde_debugfs_regset32 {
+	uint32_t offset;
+	uint32_t blk_len;
+	struct sde_kms *sde_kms;
+};
+
+/**
+ * sde_debugfs_setup_regset32 - Initialize register block definition for debugfs
+ * This function is meant to initialize sde_debugfs_regset32 structures for use
+ * with sde_debugfs_create_regset32.
+ * @regset: opaque register definition structure
+ * @offset: sub-block offset
+ * @length: sub-block length, in bytes
+ * @sde_kms: pointer to sde kms structure
+ */
+void sde_debugfs_setup_regset32(struct sde_debugfs_regset32 *regset,
+		uint32_t offset, uint32_t length, struct sde_kms *sde_kms);
+
+/**
+ * sde_debugfs_create_regset32 - Create register read back file for debugfs
+ *
+ * This function is almost identical to the standard debugfs_create_regset32()
+ * function, with the main difference being that a list of register
+ * names/offsets do not need to be provided. The 'read' function simply outputs
+ * sequential register values over a specified range.
+ *
+ * Similar to the related debugfs_create_regset32 API, the structure pointed to
+ * by regset needs to persist for the lifetime of the created file. The calling
+ * code is responsible for initialization/management of this structure.
+ *
+ * The structure pointed to by regset is meant to be opaque. Please use
+ * sde_debugfs_setup_regset32 to initialize it.
+ *
+ * @name:   File name within debugfs
+ * @mode:   File mode within debugfs
+ * @parent: Parent directory entry within debugfs, can be NULL
+ * @regset: Pointer to persistent register block definition
+ *
+ * Return: dentry pointer for newly created file, use either debugfs_remove()
+ *         or debugfs_remove_recursive() (on a parent directory) to remove the
+ *         file
+ */
+void *sde_debugfs_create_regset32(const char *name, umode_t mode,
+		void *parent, struct sde_debugfs_regset32 *regset);
+
+/**
+ * sde_debugfs_get_root - Return root directory entry for SDE's debugfs
+ *
+ * The return value should be passed as the 'parent' argument to subsequent
+ * debugfs create calls.
+ *
+ * @sde_kms: Pointer to SDE's KMS structure
+ *
+ * Return: dentry pointer for SDE's debugfs location
+ */
+void *sde_debugfs_get_root(struct sde_kms *sde_kms);
+
+/**
+ * SDE info management functions
+ * These functions/definitions allow for building up a 'sde_info' structure
+ * containing one or more "key=value\n" entries.
+ */
+#define SDE_KMS_INFO_MAX_SIZE	4096
+
+/**
+ * struct sde_kms_info - connector information structure container
+ * @data: Array of information character data
+ * @len: Current length of information data
+ * @staged_len: Temporary data buffer length, commit to
+ *              len using sde_kms_info_stop
+ * @start: Whether or not a partial data entry was just started
+ */
+struct sde_kms_info {
+	char data[SDE_KMS_INFO_MAX_SIZE];
+	uint32_t len;
+	uint32_t staged_len;
+	bool start;
+};
+
+/**
+ * SDE_KMS_INFO_DATA - Macro for accessing sde_kms_info data bytes
+ * @S: Pointer to sde_kms_info structure
+ * Returns: Pointer to byte data
+ */
+#define SDE_KMS_INFO_DATA(S)    ((S) ? ((struct sde_kms_info *)(S))->data : 0)
+
+/**
+ * SDE_KMS_INFO_DATALEN - Macro for accessing sde_kms_info data length
+ * @S: Pointer to sde_kms_info structure
+ * Returns: Size of available byte data
+ */
+#define SDE_KMS_INFO_DATALEN(S) ((S) ? ((struct sde_kms_info *)(S))->len : 0)
+
+/**
+ * sde_kms_info_reset - reset sde_kms_info structure
+ * @info: Pointer to sde_kms_info structure
+ */
+void sde_kms_info_reset(struct sde_kms_info *info);
+
+/**
+ * sde_kms_info_add_keyint - add integer value to 'sde_kms_info'
+ * @info: Pointer to sde_kms_info structure
+ * @key: Pointer to key string
+ * @value: Signed 32-bit integer value
+ */
+void sde_kms_info_add_keyint(struct sde_kms_info *info,
+		const char *key,
+		int32_t value);
+
+/**
+ * sde_kms_info_add_keystr - add string value to 'sde_kms_info'
+ * @info: Pointer to sde_kms_info structure
+ * @key: Pointer to key string
+ * @value: Pointer to string value
+ */
+void sde_kms_info_add_keystr(struct sde_kms_info *info,
+		const char *key,
+		const char *value);
+
+/**
+ * sde_kms_info_start - begin adding key to 'sde_kms_info'
+ * Usage:
+ *      sde_kms_info_start(key)
+ *      sde_kms_info_append(val_1)
+ *      ...
+ *      sde_kms_info_append(val_n)
+ *      sde_kms_info_stop
+ * @info: Pointer to sde_kms_info structure
+ * @key: Pointer to key string
+ */
+void sde_kms_info_start(struct sde_kms_info *info,
+		const char *key);
+
+/**
+ * sde_kms_info_append - append value string to 'sde_kms_info'
+ * Usage:
+ *      sde_kms_info_start(key)
+ *      sde_kms_info_append(val_1)
+ *      ...
+ *      sde_kms_info_append(val_n)
+ *      sde_kms_info_stop
+ * @info: Pointer to sde_kms_info structure
+ * @str: Pointer to partial value string
+ */
+void sde_kms_info_append(struct sde_kms_info *info,
+		const char *str);
+
+/**
+ * sde_kms_info_append_format - append format code string to 'sde_kms_info'
+ * Usage:
+ *      sde_kms_info_start(key)
+ *      sde_kms_info_append_format(fourcc, modifier)
+ *      ...
+ *      sde_kms_info_stop
+ * @info: Pointer to sde_kms_info structure
+ * @pixel_format: FOURCC format code
+ * @modifier: 64-bit drm format modifier
+ */
+void sde_kms_info_append_format(struct sde_kms_info *info,
+		uint32_t pixel_format,
+		uint64_t modifier);
+
+/**
+ * sde_kms_info_stop - finish adding key to 'sde_kms_info'
+ * Usage:
+ *      sde_kms_info_start(key)
+ *      sde_kms_info_append(val_1)
+ *      ...
+ *      sde_kms_info_append(val_n)
+ *      sde_kms_info_stop
+ * @info: Pointer to sde_kms_info structure
+ */
+void sde_kms_info_stop(struct sde_kms_info *info);
+
+/**
+ * Vblank enable/disable functions
+ */
+int sde_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
+void sde_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
+
+#endif /* __sde_kms_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_kms_utils.c b/drivers/gpu/drm/msm/sde/sde_kms_utils.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e29c09deb403b134cd1221ad6c33bcd77550e67
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_kms_utils.c
@@ -0,0 +1,153 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"sde-kms_utils:[%s] " fmt, __func__
+
+#include "sde_kms.h"
+
+void sde_kms_info_reset(struct sde_kms_info *info)
+{
+	if (info) {
+		info->len = 0;
+		info->staged_len = 0;
+	}
+}
+
+void sde_kms_info_add_keyint(struct sde_kms_info *info,
+		const char *key,
+		int32_t value)
+{
+	uint32_t len;
+
+	if (info && key) {
+		len = snprintf(info->data + info->len,
+				SDE_KMS_INFO_MAX_SIZE - info->len,
+				"%s=%d\n",
+				key,
+				value);
+
+		/* check if snprintf truncated the string */
+		if ((info->len + len) < SDE_KMS_INFO_MAX_SIZE)
+			info->len += len;
+	}
+}
+
+void sde_kms_info_add_keystr(struct sde_kms_info *info,
+		const char *key,
+		const char *value)
+{
+	uint32_t len;
+
+	if (info && key && value) {
+		len = snprintf(info->data + info->len,
+				SDE_KMS_INFO_MAX_SIZE - info->len,
+				"%s=%s\n",
+				key,
+				value);
+
+		/* check if snprintf truncated the string */
+		if ((info->len + len) < SDE_KMS_INFO_MAX_SIZE)
+			info->len += len;
+	}
+}
+
+void sde_kms_info_start(struct sde_kms_info *info,
+		const char *key)
+{
+	uint32_t len;
+
+	if (info && key) {
+		len = snprintf(info->data + info->len,
+				SDE_KMS_INFO_MAX_SIZE - info->len,
+				"%s=",
+				key);
+
+		info->start = true;
+
+		/* check if snprintf truncated the string */
+		if ((info->len + len) < SDE_KMS_INFO_MAX_SIZE)
+			info->staged_len = info->len + len;
+	}
+}
+
+void sde_kms_info_append(struct sde_kms_info *info,
+		const char *str)
+{
+	uint32_t len;
+
+	if (info) {
+		len = snprintf(info->data + info->staged_len,
+				SDE_KMS_INFO_MAX_SIZE - info->staged_len,
+				"%s",
+				str);
+
+		/* check if snprintf truncated the string */
+		if ((info->staged_len + len) < SDE_KMS_INFO_MAX_SIZE) {
+			info->staged_len += len;
+			info->start = false;
+		}
+	}
+}
+
+void sde_kms_info_append_format(struct sde_kms_info *info,
+		uint32_t pixel_format,
+		uint64_t modifier)
+{
+	uint32_t len;
+
+	if (!info)
+		return;
+
+	if (modifier) {
+		len = snprintf(info->data + info->staged_len,
+				SDE_KMS_INFO_MAX_SIZE - info->staged_len,
+				info->start ?
+				"%c%c%c%c/%llX/%llX" : " %c%c%c%c/%llX/%llX",
+				(pixel_format >> 0) & 0xFF,
+				(pixel_format >> 8) & 0xFF,
+				(pixel_format >> 16) & 0xFF,
+				(pixel_format >> 24) & 0xFF,
+				(modifier >> 56) & 0xFF,
+				modifier & ((1ULL << 56) - 1));
+	} else {
+		len = snprintf(info->data + info->staged_len,
+				SDE_KMS_INFO_MAX_SIZE - info->staged_len,
+				info->start ?
+				"%c%c%c%c" : " %c%c%c%c",
+				(pixel_format >> 0) & 0xFF,
+				(pixel_format >> 8) & 0xFF,
+				(pixel_format >> 16) & 0xFF,
+				(pixel_format >> 24) & 0xFF);
+	}
+
+	/* check if snprintf truncated the string */
+	if ((info->staged_len + len) < SDE_KMS_INFO_MAX_SIZE) {
+		info->staged_len += len;
+		info->start = false;
+	}
+}
+
+void sde_kms_info_stop(struct sde_kms_info *info)
+{
+	uint32_t len;
+
+	if (info) {
+		/* insert final delimiter */
+		len = snprintf(info->data + info->staged_len,
+				SDE_KMS_INFO_MAX_SIZE - info->staged_len,
+				"\n");
+
+		/* check if snprintf truncated the string */
+		if ((info->staged_len + len) < SDE_KMS_INFO_MAX_SIZE)
+			info->len = info->staged_len + len;
+	}
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ca74926cfac6d2a02f9eab00152d5c5c59652a5
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -0,0 +1,2400 @@
+/*
+ * Copyright (C) 2014-2017 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/debugfs.h>
+#include <uapi/drm/sde_drm.h>
+#include <uapi/drm/msm_drm_pp.h>
+
+#include "msm_prop.h"
+
+#include "sde_kms.h"
+#include "sde_fence.h"
+#include "sde_formats.h"
+#include "sde_hw_sspp.h"
+#include "sde_trace.h"
+#include "sde_crtc.h"
+#include "sde_vbif.h"
+#include "sde_plane.h"
+#include "sde_color_processing.h"
+
+#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
+		(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
+
+#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
+		(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
+
+#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
+#define PHASE_STEP_SHIFT	21
+#define PHASE_STEP_UNIT_SCALE   ((int) (1 << PHASE_STEP_SHIFT))
+#define PHASE_RESIDUAL		15
+
+#define SHARP_STRENGTH_DEFAULT	32
+#define SHARP_EDGE_THR_DEFAULT	112
+#define SHARP_SMOOTH_THR_DEFAULT	8
+#define SHARP_NOISE_THR_DEFAULT	2
+
+#define SDE_NAME_SIZE  12
+
+#define SDE_PLANE_COLOR_FILL_FLAG	BIT(31)
+
+/* dirty bits for update function */
+#define SDE_PLANE_DIRTY_RECTS	0x1
+#define SDE_PLANE_DIRTY_FORMAT	0x2
+#define SDE_PLANE_DIRTY_SHARPEN	0x4
+#define SDE_PLANE_DIRTY_ALL	0xFFFFFFFF
+
+/**
+ * enum sde_plane_qos - Different qos configurations for each pipe
+ *
+ * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
+ * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
+ *	this configuration is mutually exclusive from VBLANK_CTRL.
+ * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
+ */
+enum sde_plane_qos {
+	SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
+	SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
+	SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
+};
+
+/*
+ * struct sde_plane - local sde plane structure
+ * @csc_cfg: Decoded user configuration for csc
+ * @csc_usr_ptr: Points to csc_cfg if valid user config available
+ * @csc_ptr: Points to sde_csc_cfg structure to use for current
+ */
+struct sde_plane {
+	struct drm_plane base;
+
+	int mmu_id;
+
+	struct mutex lock;
+
+	enum sde_sspp pipe;
+	uint32_t features;      /* capabilities from catalog */
+	uint32_t nformats;
+	uint32_t formats[64];
+
+	struct sde_hw_pipe *pipe_hw;
+	struct sde_hw_pipe_cfg pipe_cfg;
+	struct sde_hw_sharp_cfg sharp_cfg;
+	struct sde_hw_scaler3_cfg *scaler3_cfg;
+	struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
+	uint32_t color_fill;
+	bool is_error;
+	bool is_rt_pipe;
+
+	struct sde_hw_pixel_ext pixel_ext;
+	bool pixel_ext_usr;
+
+	struct sde_csc_cfg csc_cfg;
+	struct sde_csc_cfg *csc_usr_ptr;
+	struct sde_csc_cfg *csc_ptr;
+
+	const struct sde_sspp_sub_blks *pipe_sblk;
+
+	char pipe_name[SDE_NAME_SIZE];
+
+	struct msm_property_info property_info;
+	struct msm_property_data property_data[PLANE_PROP_COUNT];
+	struct drm_property_blob *blob_info;
+
+	/* debugfs related stuff */
+	struct dentry *debugfs_root;
+	struct sde_debugfs_regset32 debugfs_src;
+	struct sde_debugfs_regset32 debugfs_scaler;
+	struct sde_debugfs_regset32 debugfs_csc;
+};
+
+#define to_sde_plane(x) container_of(x, struct sde_plane, base)
+
+static bool sde_plane_enabled(struct drm_plane_state *state)
+{
+	return state && state->fb && state->crtc;
+}
+
+/**
+ * _sde_plane_calc_fill_level - calculate fill level of the given source format
+ * @plane:		Pointer to drm plane
+ * @fmt:		Pointer to source buffer format
+ * @src_wdith:		width of source buffer
+ * Return: fill level corresponding to the source buffer/format or 0 if error
+ */
+static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
+		const struct sde_format *fmt, u32 src_width)
+{
+	struct sde_plane *psde;
+	u32 fixed_buff_size;
+	u32 total_fl;
+
+	if (!plane || !fmt) {
+		SDE_ERROR("invalid arguments\n");
+		return 0;
+	}
+
+	psde = to_sde_plane(plane);
+	fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
+
+	if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
+		if (fmt->chroma_sample == SDE_CHROMA_420) {
+			/* NV12 */
+			total_fl = (fixed_buff_size / 2) /
+				((src_width + 32) * fmt->bpp);
+		} else {
+			/* non NV12 */
+			total_fl = (fixed_buff_size) /
+				((src_width + 32) * fmt->bpp);
+		}
+	} else {
+		total_fl = (fixed_buff_size * 2) /
+			((src_width + 32) * fmt->bpp);
+	}
+
+	SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
+			plane->base.id, psde->pipe - SSPP_VIG0,
+			fmt->base.pixel_format, src_width, total_fl);
+
+	return total_fl;
+}
+
+/**
+ * _sde_plane_get_qos_lut_linear - get linear LUT mapping
+ * @total_fl:		fill level
+ * Return: LUT setting corresponding to the fill level
+ */
+static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
+{
+	u32 qos_lut;
+
+	if (total_fl <= 4)
+		qos_lut = 0x1B;
+	else if (total_fl <= 5)
+		qos_lut = 0x5B;
+	else if (total_fl <= 6)
+		qos_lut = 0x15B;
+	else if (total_fl <= 7)
+		qos_lut = 0x55B;
+	else if (total_fl <= 8)
+		qos_lut = 0x155B;
+	else if (total_fl <= 9)
+		qos_lut = 0x555B;
+	else if (total_fl <= 10)
+		qos_lut = 0x1555B;
+	else if (total_fl <= 11)
+		qos_lut = 0x5555B;
+	else if (total_fl <= 12)
+		qos_lut = 0x15555B;
+	else
+		qos_lut = 0x55555B;
+
+	return qos_lut;
+}
+
+/**
+ * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
+ * @total_fl:		fill level
+ * Return: LUT setting corresponding to the fill level
+ */
+static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
+{
+	u32 qos_lut;
+
+	if (total_fl <= 10)
+		qos_lut = 0x1AAff;
+	else if (total_fl <= 11)
+		qos_lut = 0x5AAFF;
+	else if (total_fl <= 12)
+		qos_lut = 0x15AAFF;
+	else
+		qos_lut = 0x55AAFF;
+
+	return qos_lut;
+}
+
+/**
+ * _sde_plane_set_qos_lut - set QoS LUT of the given plane
+ * @plane:		Pointer to drm plane
+ * @fb:			Pointer to framebuffer associated with the given plane
+ */
+static void _sde_plane_set_qos_lut(struct drm_plane *plane,
+		struct drm_framebuffer *fb)
+{
+	struct sde_plane *psde;
+	const struct sde_format *fmt = NULL;
+	u32 qos_lut;
+	u32 total_fl = 0;
+
+	if (!plane || !fb) {
+		SDE_ERROR("invalid arguments plane %d fb %d\n",
+				plane != 0, fb != 0);
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+
+	if (!psde->pipe_hw || !psde->pipe_sblk) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	} else if (!psde->pipe_hw->ops.setup_creq_lut) {
+		return;
+	}
+
+	if (!psde->is_rt_pipe) {
+		qos_lut = psde->pipe_sblk->creq_lut_nrt;
+	} else {
+		fmt = sde_get_sde_format_ext(
+				fb->pixel_format,
+				fb->modifier,
+				drm_format_num_planes(fb->pixel_format));
+		total_fl = _sde_plane_calc_fill_level(plane, fmt,
+				psde->pipe_cfg.src_rect.w);
+
+		if (SDE_FORMAT_IS_LINEAR(fmt))
+			qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
+		else
+			qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
+	}
+
+	psde->pipe_qos_cfg.creq_lut = qos_lut;
+
+	trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
+			(fmt) ? fmt->base.pixel_format : 0,
+			psde->is_rt_pipe, total_fl, qos_lut,
+			(fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
+
+	SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
+			plane->base.id,
+			psde->pipe - SSPP_VIG0,
+			(fmt) ? fmt->base.pixel_format : 0,
+			psde->is_rt_pipe, total_fl, qos_lut);
+
+	psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
+}
+
+/**
+ * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
+ * @plane:		Pointer to drm plane
+ * @fb:			Pointer to framebuffer associated with the given plane
+ */
+static void _sde_plane_set_danger_lut(struct drm_plane *plane,
+		struct drm_framebuffer *fb)
+{
+	struct sde_plane *psde;
+	const struct sde_format *fmt = NULL;
+	u32 danger_lut, safe_lut;
+
+	if (!plane || !fb) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+
+	if (!psde->pipe_hw || !psde->pipe_sblk) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	} else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
+		return;
+	}
+
+	if (!psde->is_rt_pipe) {
+		danger_lut = psde->pipe_sblk->danger_lut_nrt;
+		safe_lut = psde->pipe_sblk->safe_lut_nrt;
+	} else {
+		fmt = sde_get_sde_format_ext(
+				fb->pixel_format,
+				fb->modifier,
+				drm_format_num_planes(fb->pixel_format));
+
+		if (SDE_FORMAT_IS_LINEAR(fmt)) {
+			danger_lut = psde->pipe_sblk->danger_lut_linear;
+			safe_lut = psde->pipe_sblk->safe_lut_linear;
+		} else {
+			danger_lut = psde->pipe_sblk->danger_lut_tile;
+			safe_lut = psde->pipe_sblk->safe_lut_tile;
+		}
+	}
+
+	psde->pipe_qos_cfg.danger_lut = danger_lut;
+	psde->pipe_qos_cfg.safe_lut = safe_lut;
+
+	trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
+			(fmt) ? fmt->base.pixel_format : 0,
+			(fmt) ? fmt->fetch_mode : 0,
+			psde->pipe_qos_cfg.danger_lut,
+			psde->pipe_qos_cfg.safe_lut);
+
+	SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
+		plane->base.id,
+		psde->pipe - SSPP_VIG0,
+		fmt ? fmt->base.pixel_format : 0,
+		fmt ? fmt->fetch_mode : -1,
+		psde->pipe_qos_cfg.danger_lut,
+		psde->pipe_qos_cfg.safe_lut);
+
+	psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
+			&psde->pipe_qos_cfg);
+}
+
+/**
+ * _sde_plane_set_qos_ctrl - set QoS control of the given plane
+ * @plane:		Pointer to drm plane
+ * @enable:		true to enable QoS control
+ * @flags:		QoS control mode (enum sde_plane_qos)
+ */
+static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
+	bool enable, u32 flags)
+{
+	struct sde_plane *psde;
+
+	if (!plane) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+
+	if (!psde->pipe_hw || !psde->pipe_sblk) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	} else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
+		return;
+	}
+
+	if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
+		psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
+		psde->pipe_qos_cfg.danger_vblank =
+				psde->pipe_sblk->danger_vblank;
+		psde->pipe_qos_cfg.vblank_en = enable;
+	}
+
+	 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
+		/* this feature overrules previous VBLANK_CTRL */
+		psde->pipe_qos_cfg.vblank_en = false;
+		psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
+	}
+
+	if (flags & SDE_PLANE_QOS_PANIC_CTRL)
+		psde->pipe_qos_cfg.danger_safe_en = enable;
+
+	if (!psde->is_rt_pipe) {
+		psde->pipe_qos_cfg.vblank_en = false;
+		psde->pipe_qos_cfg.danger_safe_en = false;
+	}
+
+	SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
+		plane->base.id,
+		psde->pipe - SSPP_VIG0,
+		psde->pipe_qos_cfg.danger_safe_en,
+		psde->pipe_qos_cfg.vblank_en,
+		psde->pipe_qos_cfg.creq_vblank,
+		psde->pipe_qos_cfg.danger_vblank,
+		psde->is_rt_pipe);
+
+	psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
+			&psde->pipe_qos_cfg);
+}
+
+int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
+{
+	struct sde_plane *psde;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	if (!plane || !plane->dev) {
+		SDE_ERROR("invalid arguments\n");
+		return -EINVAL;
+	}
+
+	priv = plane->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid KMS reference\n");
+		return -EINVAL;
+	}
+
+	sde_kms = to_sde_kms(priv->kms);
+	psde = to_sde_plane(plane);
+
+	if (!psde->is_rt_pipe)
+		goto end;
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
+
+	_sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
+
+	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
+
+end:
+	return 0;
+}
+
+/**
+ * _sde_plane_set_ot_limit - set OT limit for the given plane
+ * @plane:		Pointer to drm plane
+ * @crtc:		Pointer to drm crtc
+ */
+static void _sde_plane_set_ot_limit(struct drm_plane *plane,
+		struct drm_crtc *crtc)
+{
+	struct sde_plane *psde;
+	struct sde_vbif_set_ot_params ot_params;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	if (!plane || !plane->dev || !crtc) {
+		SDE_ERROR("invalid arguments plane %d crtc %d\n",
+				plane != 0, crtc != 0);
+		return;
+	}
+
+	priv = plane->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid KMS reference\n");
+		return;
+	}
+
+	sde_kms = to_sde_kms(priv->kms);
+	psde = to_sde_plane(plane);
+	if (!psde->pipe_hw) {
+		SDE_ERROR("invalid pipe reference\n");
+		return;
+	}
+
+	memset(&ot_params, 0, sizeof(ot_params));
+	ot_params.xin_id = psde->pipe_hw->cap->xin_id;
+	ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
+	ot_params.width = psde->pipe_cfg.src_rect.w;
+	ot_params.height = psde->pipe_cfg.src_rect.h;
+	ot_params.is_wfd = !psde->is_rt_pipe;
+	ot_params.frame_rate = crtc->mode.vrefresh;
+	ot_params.vbif_idx = VBIF_RT;
+	ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
+	ot_params.rd = true;
+
+	sde_vbif_set_ot_limit(sde_kms, &ot_params);
+}
+
+/* helper to update a state's input fence pointer from the property */
+static void _sde_plane_set_input_fence(struct sde_plane *psde,
+		struct sde_plane_state *pstate, uint64_t fd)
+{
+	if (!psde || !pstate) {
+		SDE_ERROR("invalid arg(s), plane %d state %d\n",
+				psde != 0, pstate != 0);
+		return;
+	}
+
+	/* clear previous reference */
+	if (pstate->input_fence)
+		sde_sync_put(pstate->input_fence);
+
+	/* get fence pointer for later */
+	pstate->input_fence = sde_sync_get(fd);
+
+	SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
+}
+
+int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
+{
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+	uint32_t prefix;
+	void *input_fence;
+	int ret = -EINVAL;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+	} else if (!plane->state) {
+		SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
+	} else {
+		psde = to_sde_plane(plane);
+		pstate = to_sde_plane_state(plane->state);
+		input_fence = pstate->input_fence;
+
+		if (input_fence) {
+			prefix = sde_sync_get_name_prefix(input_fence);
+			ret = sde_sync_wait(input_fence, wait_ms);
+
+			SDE_EVT32(DRMID(plane), -ret, prefix);
+
+			switch (ret) {
+			case 0:
+				SDE_DEBUG_PLANE(psde, "signaled\n");
+				break;
+			case -ETIME:
+				SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
+						wait_ms, prefix);
+				psde->is_error = true;
+				break;
+			default:
+				SDE_ERROR_PLANE(psde, "error %d on %08X\n",
+						ret, prefix);
+				psde->is_error = true;
+				break;
+			}
+		} else {
+			ret = 0;
+		}
+	}
+	return ret;
+}
+
+static inline void _sde_plane_set_scanout(struct drm_plane *plane,
+		struct sde_plane_state *pstate,
+		struct sde_hw_pipe_cfg *pipe_cfg,
+		struct drm_framebuffer *fb)
+{
+	struct sde_plane *psde;
+	int ret;
+
+	if (!plane || !pstate || !pipe_cfg || !fb) {
+		SDE_ERROR(
+			"invalid arg(s), plane %d state %d cfg %d fb %d\n",
+			plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+	if (!psde->pipe_hw) {
+		SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
+		return;
+	}
+
+	ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
+	if (ret == -EAGAIN)
+		SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
+	else if (ret)
+		SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
+	else if (psde->pipe_hw->ops.setup_sourceaddress)
+		psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
+}
+
+static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
+		struct sde_plane_state *pstate)
+{
+	struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg;
+	int ret = 0;
+
+	cfg->dir_lut = msm_property_get_blob(
+			&psde->property_info,
+			pstate->property_blobs, &cfg->dir_len,
+			PLANE_PROP_SCALER_LUT_ED);
+	cfg->cir_lut = msm_property_get_blob(
+			&psde->property_info,
+			pstate->property_blobs, &cfg->cir_len,
+			PLANE_PROP_SCALER_LUT_CIR);
+	cfg->sep_lut = msm_property_get_blob(
+			&psde->property_info,
+			pstate->property_blobs, &cfg->sep_len,
+			PLANE_PROP_SCALER_LUT_SEP);
+	if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
+		ret = -ENODATA;
+	return ret;
+}
+
+static void _sde_plane_setup_scaler3(struct sde_plane *psde,
+		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
+		struct sde_hw_scaler3_cfg *scale_cfg,
+		const struct sde_format *fmt,
+		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
+{
+}
+
+/**
+ * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
+ * @psde: Pointer to SDE plane object
+ * @src: Source size
+ * @dst: Destination size
+ * @phase_steps: Pointer to output array for phase steps
+ * @filter: Pointer to output array for filter type
+ * @fmt: Pointer to format definition
+ * @chroma_subsampling: Subsampling amount for chroma channel
+ *
+ * Returns: 0 on success
+ */
+static int _sde_plane_setup_scaler2(struct sde_plane *psde,
+		uint32_t src, uint32_t dst, uint32_t *phase_steps,
+		enum sde_hw_filter *filter, const struct sde_format *fmt,
+		uint32_t chroma_subsampling)
+{
+	if (!psde || !phase_steps || !filter || !fmt) {
+		SDE_ERROR(
+			"invalid arg(s), plane %d phase %d filter %d fmt %d\n",
+			psde != 0, phase_steps != 0, filter != 0, fmt != 0);
+		return -EINVAL;
+	}
+
+	/* calculate phase steps, leave init phase as zero */
+	phase_steps[SDE_SSPP_COMP_0] =
+		mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
+	phase_steps[SDE_SSPP_COMP_1_2] =
+		phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
+	phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
+	phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
+
+	/* calculate scaler config, if necessary */
+	if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
+		filter[SDE_SSPP_COMP_3] =
+			(src <= dst) ? SDE_SCALE_FILTER_BIL :
+			SDE_SCALE_FILTER_PCMN;
+
+		if (SDE_FORMAT_IS_YUV(fmt)) {
+			filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
+			filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
+		} else {
+			filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
+			filter[SDE_SSPP_COMP_1_2] =
+				SDE_SCALE_FILTER_NEAREST;
+		}
+	} else {
+		/* disable scaler */
+		filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
+		filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
+		filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
+	}
+	return 0;
+}
+
+/**
+ * _sde_plane_setup_pixel_ext - determine default pixel extension values
+ * @psde: Pointer to SDE plane object
+ * @src: Source size
+ * @dst: Destination size
+ * @decimated_src: Source size after decimation, if any
+ * @phase_steps: Pointer to output array for phase steps
+ * @out_src: Output array for pixel extension values
+ * @out_edge1: Output array for pixel extension first edge
+ * @out_edge2: Output array for pixel extension second edge
+ * @filter: Pointer to array for filter type
+ * @fmt: Pointer to format definition
+ * @chroma_subsampling: Subsampling amount for chroma channel
+ * @post_compare: Whether to chroma subsampled source size for comparisions
+ */
+static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
+		uint32_t src, uint32_t dst, uint32_t decimated_src,
+		uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
+		int *out_edge2, enum sde_hw_filter *filter,
+		const struct sde_format *fmt, uint32_t chroma_subsampling,
+		bool post_compare)
+{
+	int64_t edge1, edge2, caf;
+	uint32_t src_work;
+	int i, tmp;
+
+	if (psde && phase_steps && out_src && out_edge1 &&
+			out_edge2 && filter && fmt) {
+		/* handle CAF for YUV formats */
+		if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
+			caf = PHASE_STEP_UNIT_SCALE;
+		else
+			caf = 0;
+
+		for (i = 0; i < SDE_MAX_PLANES; i++) {
+			src_work = decimated_src;
+			if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
+				src_work /= chroma_subsampling;
+			if (post_compare)
+				src = src_work;
+			if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
+				/* unity */
+				edge1 = 0;
+				edge2 = 0;
+			} else if (dst >= src) {
+				/* upscale */
+				edge1 = (1 << PHASE_RESIDUAL);
+				edge1 -= caf;
+				edge2 = (1 << PHASE_RESIDUAL);
+				edge2 += (dst - 1) * *(phase_steps + i);
+				edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
+				edge2 += caf;
+				edge2 = -(edge2);
+			} else {
+				/* downscale */
+				edge1 = 0;
+				edge2 = (dst - 1) * *(phase_steps + i);
+				edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
+				edge2 += *(phase_steps + i);
+				edge2 = -(edge2);
+			}
+
+			/* only enable CAF for luma plane */
+			caf = 0;
+
+			/* populate output arrays */
+			*(out_src + i) = src_work;
+
+			/* edge updates taken from __pxl_extn_helper */
+			if (edge1 >= 0) {
+				tmp = (uint32_t)edge1;
+				tmp >>= PHASE_STEP_SHIFT;
+				*(out_edge1 + i) = -tmp;
+			} else {
+				tmp = (uint32_t)(-edge1);
+				*(out_edge1 + i) =
+					(tmp + PHASE_STEP_UNIT_SCALE - 1) >>
+					PHASE_STEP_SHIFT;
+			}
+			if (edge2 >= 0) {
+				tmp = (uint32_t)edge2;
+				tmp >>= PHASE_STEP_SHIFT;
+				*(out_edge2 + i) = -tmp;
+			} else {
+				tmp = (uint32_t)(-edge2);
+				*(out_edge2 + i) =
+					(tmp + PHASE_STEP_UNIT_SCALE - 1) >>
+					PHASE_STEP_SHIFT;
+			}
+		}
+	}
+}
+
+static inline void _sde_plane_setup_csc(struct sde_plane *psde)
+{
+	static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
+		{
+			/* S15.16 format */
+			0x00012A00, 0x00000000, 0x00019880,
+			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+			0x00012A00, 0x00020480, 0x00000000,
+		},
+		/* signed bias */
+		{ 0xfff0, 0xff80, 0xff80,},
+		{ 0x0, 0x0, 0x0,},
+		/* unsigned clamp */
+		{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
+		{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
+	};
+	static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
+		{
+			/* S15.16 format */
+			0x00012A00, 0x00000000, 0x00019880,
+			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+			0x00012A00, 0x00020480, 0x00000000,
+			},
+		/* signed bias */
+		{ 0xffc0, 0xfe00, 0xfe00,},
+		{ 0x0, 0x0, 0x0,},
+		/* unsigned clamp */
+		{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
+		{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
+	};
+
+	if (!psde) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	/* revert to kernel default if override not available */
+	if (psde->csc_usr_ptr)
+		psde->csc_ptr = psde->csc_usr_ptr;
+	else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
+		psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
+	else
+		psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
+
+	SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
+			psde->csc_ptr->csc_mv[0],
+			psde->csc_ptr->csc_mv[1],
+			psde->csc_ptr->csc_mv[2]);
+}
+
+static void sde_color_process_plane_setup(struct drm_plane *plane)
+{
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+	uint32_t hue, saturation, value, contrast;
+	struct drm_msm_memcol *memcol = NULL;
+	size_t memcol_sz = 0;
+
+	psde = to_sde_plane(plane);
+	pstate = to_sde_plane_state(plane->state);
+
+	hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
+	if (psde->pipe_hw->ops.setup_pa_hue)
+		psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
+	saturation = (uint32_t) sde_plane_get_property(pstate,
+		PLANE_PROP_SATURATION_ADJUST);
+	if (psde->pipe_hw->ops.setup_pa_sat)
+		psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
+	value = (uint32_t) sde_plane_get_property(pstate,
+		PLANE_PROP_VALUE_ADJUST);
+	if (psde->pipe_hw->ops.setup_pa_val)
+		psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
+	contrast = (uint32_t) sde_plane_get_property(pstate,
+		PLANE_PROP_CONTRAST_ADJUST);
+	if (psde->pipe_hw->ops.setup_pa_cont)
+		psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
+
+	if (psde->pipe_hw->ops.setup_pa_memcolor) {
+		/* Skin memory color setup */
+		memcol = msm_property_get_blob(&psde->property_info,
+					pstate->property_blobs,
+					&memcol_sz,
+					PLANE_PROP_SKIN_COLOR);
+		psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
+					MEMCOLOR_SKIN, memcol);
+
+		/* Sky memory color setup */
+		memcol = msm_property_get_blob(&psde->property_info,
+					pstate->property_blobs,
+					&memcol_sz,
+					PLANE_PROP_SKY_COLOR);
+		psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
+					MEMCOLOR_SKY, memcol);
+
+		/* Foliage memory color setup */
+		memcol = msm_property_get_blob(&psde->property_info,
+					pstate->property_blobs,
+					&memcol_sz,
+					PLANE_PROP_FOLIAGE_COLOR);
+		psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
+					MEMCOLOR_FOLIAGE, memcol);
+	}
+}
+
+static void _sde_plane_setup_scaler(struct sde_plane *psde,
+		const struct sde_format *fmt,
+		struct sde_plane_state *pstate)
+{
+	struct sde_hw_pixel_ext *pe;
+	uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
+
+	if (!psde || !fmt) {
+		SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
+				psde != 0, fmt != 0, pstate != 0);
+		return;
+	}
+
+	pe = &(psde->pixel_ext);
+
+	psde->pipe_cfg.horz_decimation =
+		sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
+	psde->pipe_cfg.vert_decimation =
+		sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
+
+	/* don't chroma subsample if decimating */
+	chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
+		drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
+	chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
+		drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
+
+	/* update scaler */
+	if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
+		int error;
+
+		error = _sde_plane_setup_scaler3_lut(psde, pstate);
+		if (error || !psde->pixel_ext_usr) {
+			/* calculate default config for QSEED3 */
+			_sde_plane_setup_scaler3(psde,
+					psde->pipe_cfg.src_rect.w,
+					psde->pipe_cfg.src_rect.h,
+					psde->pipe_cfg.dst_rect.w,
+					psde->pipe_cfg.dst_rect.h,
+					psde->scaler3_cfg, fmt,
+					chroma_subsmpl_h, chroma_subsmpl_v);
+		}
+	} else if (!psde->pixel_ext_usr) {
+		uint32_t deci_dim, i;
+
+		/* calculate default configuration for QSEED2 */
+		memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
+
+		SDE_DEBUG_PLANE(psde, "default config\n");
+		deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
+				psde->pipe_cfg.horz_decimation);
+		_sde_plane_setup_scaler2(psde,
+				deci_dim,
+				psde->pipe_cfg.dst_rect.w,
+				pe->phase_step_x,
+				pe->horz_filter, fmt, chroma_subsmpl_h);
+
+		if (SDE_FORMAT_IS_YUV(fmt))
+			deci_dim &= ~0x1;
+		_sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
+				psde->pipe_cfg.dst_rect.w, deci_dim,
+				pe->phase_step_x,
+				pe->roi_w,
+				pe->num_ext_pxls_left,
+				pe->num_ext_pxls_right, pe->horz_filter, fmt,
+				chroma_subsmpl_h, 0);
+
+		deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
+				psde->pipe_cfg.vert_decimation);
+		_sde_plane_setup_scaler2(psde,
+				deci_dim,
+				psde->pipe_cfg.dst_rect.h,
+				pe->phase_step_y,
+				pe->vert_filter, fmt, chroma_subsmpl_v);
+		_sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
+				psde->pipe_cfg.dst_rect.h, deci_dim,
+				pe->phase_step_y,
+				pe->roi_h,
+				pe->num_ext_pxls_top,
+				pe->num_ext_pxls_btm, pe->vert_filter, fmt,
+				chroma_subsmpl_v, 1);
+
+		for (i = 0; i < SDE_MAX_PLANES; i++) {
+			if (pe->num_ext_pxls_left[i] >= 0)
+				pe->left_rpt[i] = pe->num_ext_pxls_left[i];
+			else
+				pe->left_ftch[i] = pe->num_ext_pxls_left[i];
+
+			if (pe->num_ext_pxls_right[i] >= 0)
+				pe->right_rpt[i] = pe->num_ext_pxls_right[i];
+			else
+				pe->right_ftch[i] = pe->num_ext_pxls_right[i];
+
+			if (pe->num_ext_pxls_top[i] >= 0)
+				pe->top_rpt[i] = pe->num_ext_pxls_top[i];
+			else
+				pe->top_ftch[i] = pe->num_ext_pxls_top[i];
+
+			if (pe->num_ext_pxls_btm[i] >= 0)
+				pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
+			else
+				pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
+		}
+	}
+}
+
+/**
+ * _sde_plane_color_fill - enables color fill on plane
+ * @psde:   Pointer to SDE plane object
+ * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
+ * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
+ * Returns: 0 on success
+ */
+static int _sde_plane_color_fill(struct sde_plane *psde,
+		uint32_t color, uint32_t alpha)
+{
+	const struct sde_format *fmt;
+
+	if (!psde) {
+		SDE_ERROR("invalid plane\n");
+		return -EINVAL;
+	}
+
+	if (!psde->pipe_hw) {
+		SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	/*
+	 * select fill format to match user property expectation,
+	 * h/w only supports RGB variants
+	 */
+	fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
+
+	/* update sspp */
+	if (fmt && psde->pipe_hw->ops.setup_solidfill) {
+		psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
+				(color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
+
+		/* override scaler/decimation if solid fill */
+		psde->pipe_cfg.src_rect.x = 0;
+		psde->pipe_cfg.src_rect.y = 0;
+		psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
+		psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
+
+		_sde_plane_setup_scaler(psde, fmt, 0);
+
+		if (psde->pipe_hw->ops.setup_format)
+			psde->pipe_hw->ops.setup_format(psde->pipe_hw,
+					fmt, SDE_SSPP_SOLID_FILL);
+
+		if (psde->pipe_hw->ops.setup_rects)
+			psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
+					&psde->pipe_cfg, &psde->pixel_ext,
+					psde->scaler3_cfg);
+	}
+
+	return 0;
+}
+
+static int _sde_plane_mode_set(struct drm_plane *plane,
+				struct drm_plane_state *state)
+{
+	uint32_t nplanes, src_flags;
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+	const struct sde_format *fmt;
+	struct drm_crtc *crtc;
+	struct drm_framebuffer *fb;
+	struct sde_rect src, dst;
+	bool q16_data = true;
+	int idx;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+		return -EINVAL;
+	} else if (!plane->state) {
+		SDE_ERROR("invalid plane state\n");
+		return -EINVAL;
+	}
+
+	psde = to_sde_plane(plane);
+	pstate = to_sde_plane_state(plane->state);
+
+	crtc = state->crtc;
+	fb = state->fb;
+	if (!crtc || !fb) {
+		SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
+				crtc != 0, fb != 0);
+		return -EINVAL;
+	}
+	fmt = to_sde_format(msm_framebuffer_format(fb));
+	nplanes = fmt->num_planes;
+
+	/* determine what needs to be refreshed */
+	while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
+		switch (idx) {
+		case PLANE_PROP_SCALER_V1:
+		case PLANE_PROP_SCALER_V2:
+		case PLANE_PROP_H_DECIMATE:
+		case PLANE_PROP_V_DECIMATE:
+		case PLANE_PROP_SRC_CONFIG:
+		case PLANE_PROP_ZPOS:
+			pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
+			break;
+		case PLANE_PROP_CSC_V1:
+			pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
+			break;
+		case PLANE_PROP_COLOR_FILL:
+			/* potentially need to refresh everything */
+			pstate->dirty = SDE_PLANE_DIRTY_ALL;
+			break;
+		case PLANE_PROP_ROTATION:
+			pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
+			break;
+		case PLANE_PROP_INFO:
+		case PLANE_PROP_ALPHA:
+		case PLANE_PROP_INPUT_FENCE:
+		case PLANE_PROP_BLEND_OP:
+			/* no special action required */
+			break;
+		default:
+			/* unknown property, refresh everything */
+			pstate->dirty |= SDE_PLANE_DIRTY_ALL;
+			SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
+			break;
+		}
+	}
+
+	if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
+		memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
+
+	_sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
+
+	/* early out if nothing dirty */
+	if (!pstate->dirty)
+		return 0;
+	pstate->pending = true;
+
+	psde->is_rt_pipe = sde_crtc_is_rt(crtc);
+	_sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
+
+	/* update roi config */
+	if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
+		POPULATE_RECT(&src, state->src_x, state->src_y,
+			state->src_w, state->src_h, q16_data);
+		POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
+			state->crtc_w, state->crtc_h, !q16_data);
+
+		SDE_DEBUG_PLANE(psde,
+			"FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
+				fb->base.id, src.x, src.y, src.w, src.h,
+				crtc->base.id, dst.x, dst.y, dst.w, dst.h,
+				drm_get_format_name(fmt->base.pixel_format),
+				SDE_FORMAT_IS_UBWC(fmt));
+
+		if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
+			BIT(SDE_DRM_DEINTERLACE)) {
+			SDE_DEBUG_PLANE(psde, "deinterlace\n");
+			for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
+				psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
+			src.h /= 2;
+			src.y  = DIV_ROUND_UP(src.y, 2);
+			src.y &= ~0x1;
+		}
+
+		psde->pipe_cfg.src_rect = src;
+		psde->pipe_cfg.dst_rect = dst;
+
+		/* check for color fill */
+		psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
+				PLANE_PROP_COLOR_FILL);
+		if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
+			/* skip remaining processing on color fill */
+			pstate->dirty = 0x0;
+		} else if (psde->pipe_hw->ops.setup_rects) {
+			_sde_plane_setup_scaler(psde, fmt, pstate);
+
+			psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
+					&psde->pipe_cfg, &psde->pixel_ext,
+					psde->scaler3_cfg);
+		}
+	}
+
+	if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
+			psde->pipe_hw->ops.setup_format) {
+		src_flags = 0x0;
+		SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
+			sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
+		if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
+			BIT(DRM_REFLECT_X))
+			src_flags |= SDE_SSPP_FLIP_LR;
+		if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
+			BIT(DRM_REFLECT_Y))
+			src_flags |= SDE_SSPP_FLIP_UD;
+
+		/* update format */
+		psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
+
+		/* update csc */
+		if (SDE_FORMAT_IS_YUV(fmt))
+			_sde_plane_setup_csc(psde);
+		else
+			psde->csc_ptr = 0;
+	}
+
+	sde_color_process_plane_setup(plane);
+
+	/* update sharpening */
+	if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
+		psde->pipe_hw->ops.setup_sharpening) {
+		psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
+		psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
+		psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
+		psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
+
+		psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
+				&psde->sharp_cfg);
+	}
+
+	_sde_plane_set_qos_lut(plane, fb);
+	_sde_plane_set_danger_lut(plane, fb);
+
+	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
+		_sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
+		_sde_plane_set_ot_limit(plane, crtc);
+	}
+
+	/* clear dirty */
+	pstate->dirty = 0x0;
+
+	return 0;
+}
+
+static int sde_plane_prepare_fb(struct drm_plane *plane,
+		const struct drm_plane_state *new_state)
+{
+	struct drm_framebuffer *fb = new_state->fb;
+	struct sde_plane *psde = to_sde_plane(plane);
+
+	if (!new_state->fb)
+		return 0;
+
+	SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
+	return msm_framebuffer_prepare(fb, psde->mmu_id);
+}
+
+static void sde_plane_cleanup_fb(struct drm_plane *plane,
+		const struct drm_plane_state *old_state)
+{
+	struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
+	struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
+
+	if (!fb)
+		return;
+
+	SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
+	msm_framebuffer_cleanup(fb, psde->mmu_id);
+}
+
+static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
+		struct drm_plane_state *state,
+		struct drm_plane_state *old_state)
+{
+	struct sde_plane_state *pstate = to_sde_plane_state(state);
+
+	/* no need to check it again */
+	if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
+		return;
+
+	if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
+			|| psde->is_error) {
+		SDE_DEBUG_PLANE(psde,
+			"enabling/disabling full modeset required\n");
+		pstate->dirty |= SDE_PLANE_DIRTY_ALL;
+	} else if (to_sde_plane_state(old_state)->pending) {
+		SDE_DEBUG_PLANE(psde, "still pending\n");
+		pstate->dirty |= SDE_PLANE_DIRTY_ALL;
+	} else if (state->src_w != old_state->src_w ||
+		   state->src_h != old_state->src_h ||
+		   state->src_x != old_state->src_x ||
+		   state->src_y != old_state->src_y) {
+		SDE_DEBUG_PLANE(psde, "src rect updated\n");
+		pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
+	} else if (state->crtc_w != old_state->crtc_w ||
+		   state->crtc_h != old_state->crtc_h ||
+		   state->crtc_x != old_state->crtc_x ||
+		   state->crtc_y != old_state->crtc_y) {
+		SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
+		pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
+	}
+
+	if (!state->fb || !old_state->fb) {
+		SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
+	} else if (state->fb->pixel_format != old_state->fb->pixel_format) {
+		SDE_DEBUG_PLANE(psde, "format change\n");
+		pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
+	} else {
+		uint64_t *new_mods = state->fb->modifier;
+		uint64_t *old_mods = old_state->fb->modifier;
+		uint32_t *new_pitches = state->fb->pitches;
+		uint32_t *old_pitches = old_state->fb->pitches;
+		uint32_t *new_offset = state->fb->offsets;
+		uint32_t *old_offset = old_state->fb->offsets;
+		int i;
+
+		for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
+			if (new_mods[i] != old_mods[i]) {
+				SDE_DEBUG_PLANE(psde,
+					"format modifiers change\"\
+					plane:%d new_mode:%llu old_mode:%llu\n",
+					i, new_mods[i], old_mods[i]);
+				pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
+					SDE_PLANE_DIRTY_RECTS;
+				break;
+			}
+		}
+		for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
+			if (new_pitches[i] != old_pitches[i]) {
+				SDE_DEBUG_PLANE(psde,
+					"pitches change plane:%d\"\
+					old_pitches:%u new_pitches:%u\n",
+					i, old_pitches[i], new_pitches[i]);
+				pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
+				break;
+			}
+		}
+		for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
+			if (new_offset[i] != old_offset[i]) {
+				SDE_DEBUG_PLANE(psde,
+					"offset change plane:%d\"\
+					old_offset:%u new_offset:%u\n",
+					i, old_offset[i], new_offset[i]);
+				pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
+					SDE_PLANE_DIRTY_RECTS;
+				break;
+			}
+		}
+	}
+}
+
+static int sde_plane_atomic_check(struct drm_plane *plane,
+		struct drm_plane_state *state)
+{
+	int ret = 0;
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+	const struct sde_format *fmt;
+	struct sde_rect src, dst;
+	uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
+	uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
+	bool q16_data = true;
+
+	if (!plane || !state) {
+		SDE_ERROR("invalid arg(s), plane %d state %d\n",
+				plane != 0, state != 0);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	psde = to_sde_plane(plane);
+	pstate = to_sde_plane_state(state);
+
+	if (!psde->pipe_sblk) {
+		SDE_ERROR_PLANE(psde, "invalid catalog\n");
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
+	deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
+
+	/* src values are in Q16 fixed point, convert to integer */
+	POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
+		state->src_h, q16_data);
+	POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
+		state->crtc_h, !q16_data);
+
+	src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
+	src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
+
+	max_upscale = psde->pipe_sblk->maxupscale;
+	max_downscale = psde->pipe_sblk->maxdwnscale;
+	max_linewidth = psde->pipe_sblk->maxlinewidth;
+
+	SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
+		sde_plane_enabled(plane->state), sde_plane_enabled(state));
+
+	if (!sde_plane_enabled(state))
+		goto modeset_update;
+
+	fmt = to_sde_format(msm_framebuffer_format(state->fb));
+
+	min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
+
+	if (SDE_FORMAT_IS_YUV(fmt) &&
+		(!(psde->features & SDE_SSPP_SCALER) ||
+		 !(psde->features & (BIT(SDE_SSPP_CSC)
+		 | BIT(SDE_SSPP_CSC_10BIT))))) {
+		SDE_ERROR_PLANE(psde,
+				"plane doesn't have scaler/csc for yuv\n");
+		ret = -EINVAL;
+
+	/* check src bounds */
+	} else if (state->fb->width > MAX_IMG_WIDTH ||
+		state->fb->height > MAX_IMG_HEIGHT ||
+		src.w < min_src_size || src.h < min_src_size ||
+		CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
+		CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
+		SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
+			src.x, src.y, src.w, src.h);
+		ret = -E2BIG;
+
+	/* valid yuv image */
+	} else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
+			 (src.w & 0x1) || (src.h & 0x1))) {
+		SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
+				src.x, src.y, src.w, src.h);
+		ret = -EINVAL;
+
+	/* min dst support */
+	} else if (dst.w < 0x1 || dst.h < 0x1) {
+		SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
+				dst.x, dst.y, dst.w, dst.h);
+		ret = -EINVAL;
+
+	/* decimation validation */
+	} else if (deci_w || deci_h) {
+		if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
+			(deci_h > psde->pipe_sblk->maxvdeciexp)) {
+			SDE_ERROR_PLANE(psde,
+					"too much decimation requested\n");
+			ret = -EINVAL;
+		} else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
+			SDE_ERROR_PLANE(psde,
+					"decimation requires linear fetch\n");
+			ret = -EINVAL;
+		}
+
+	} else if (!(psde->features & SDE_SSPP_SCALER) &&
+		((src.w != dst.w) || (src.h != dst.h))) {
+		SDE_ERROR_PLANE(psde,
+			"pipe doesn't support scaling %ux%u->%ux%u\n",
+			src.w, src.h, dst.w, dst.h);
+		ret = -EINVAL;
+
+	/* check decimated source width */
+	} else if (src_deci_w > max_linewidth) {
+		SDE_ERROR_PLANE(psde,
+				"invalid src w:%u, deci w:%u, line w:%u\n",
+				src.w, src_deci_w, max_linewidth);
+		ret = -E2BIG;
+
+	/* check max scaler capability */
+	} else if (((src_deci_w * max_upscale) < dst.w) ||
+		((src_deci_h * max_upscale) < dst.h) ||
+		((dst.w * max_downscale) < src_deci_w) ||
+		((dst.h * max_downscale) < src_deci_h)) {
+		SDE_ERROR_PLANE(psde,
+			"too much scaling requested %ux%u->%ux%u\n",
+			src_deci_w, src_deci_h, dst.w, dst.h);
+		ret = -E2BIG;
+	}
+
+modeset_update:
+	if (!ret)
+		_sde_plane_atomic_check_mode_changed(psde, state, plane->state);
+exit:
+	return ret;
+}
+
+/**
+ * sde_plane_flush - final plane operations before commit flush
+ * @plane: Pointer to drm plane structure
+ */
+void sde_plane_flush(struct drm_plane *plane)
+{
+	struct sde_plane *psde;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+
+	/*
+	 * These updates have to be done immediately before the plane flush
+	 * timing, and may not be moved to the atomic_update/mode_set functions.
+	 */
+	if (psde->is_error)
+		/* force white frame with 0% alpha pipe output on error */
+		_sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
+	else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
+		/* force 100% alpha */
+		_sde_plane_color_fill(psde, psde->color_fill, 0xFF);
+	else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
+		psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
+
+	/* flag h/w flush complete */
+	if (plane->state)
+		to_sde_plane_state(plane->state)->pending = false;
+}
+
+static void sde_plane_atomic_update(struct drm_plane *plane,
+				struct drm_plane_state *old_state)
+{
+	struct sde_plane *psde;
+	struct drm_plane_state *state;
+	struct sde_plane_state *pstate;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	} else if (!plane->state) {
+		SDE_ERROR("invalid plane state\n");
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+	psde->is_error = false;
+	state = plane->state;
+	pstate = to_sde_plane_state(state);
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	if (!sde_plane_enabled(state)) {
+		pstate->pending = true;
+	} else {
+		int ret;
+
+		ret = _sde_plane_mode_set(plane, state);
+		/* atomic_check should have ensured that this doesn't fail */
+		WARN_ON(ret < 0);
+	}
+}
+
+
+/* helper to install properties which are common to planes and crtcs */
+static void _sde_plane_install_properties(struct drm_plane *plane,
+	struct sde_mdss_cfg *catalog)
+{
+	static const struct drm_prop_enum_list e_blend_op[] = {
+		{SDE_DRM_BLEND_OP_NOT_DEFINED,    "not_defined"},
+		{SDE_DRM_BLEND_OP_OPAQUE,         "opaque"},
+		{SDE_DRM_BLEND_OP_PREMULTIPLIED,  "premultiplied"},
+		{SDE_DRM_BLEND_OP_COVERAGE,       "coverage"}
+	};
+	static const struct drm_prop_enum_list e_src_config[] = {
+		{SDE_DRM_DEINTERLACE, "deinterlace"}
+	};
+	const struct sde_format_extended *format_list;
+	struct sde_kms_info *info;
+	struct sde_plane *psde = to_sde_plane(plane);
+	int zpos_max = 255;
+	int zpos_def = 0;
+	char feature_name[256];
+
+	if (!plane || !psde) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	} else if (!psde->pipe_hw || !psde->pipe_sblk) {
+		SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
+				psde->pipe_hw != 0, psde->pipe_sblk != 0);
+		return;
+	} else if (!catalog) {
+		SDE_ERROR("invalid catalog\n");
+		return;
+	}
+
+	if (sde_is_custom_client()) {
+		if (catalog->mixer_count && catalog->mixer &&
+				catalog->mixer[0].sblk->maxblendstages) {
+			zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
+			if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
+				zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
+		}
+	} else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
+		/* reserve zpos == 0 for primary planes */
+		zpos_def = drm_plane_index(plane) + 1;
+	}
+
+	msm_property_install_range(&psde->property_info, "zpos",
+		0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
+
+	msm_property_install_range(&psde->property_info, "alpha",
+		0x0, 0, 255, 255, PLANE_PROP_ALPHA);
+
+	/* linux default file descriptor range on each process */
+	msm_property_install_range(&psde->property_info, "input_fence",
+		0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
+
+	if (psde->pipe_sblk->maxhdeciexp) {
+		msm_property_install_range(&psde->property_info, "h_decimate",
+			0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
+			PLANE_PROP_H_DECIMATE);
+	}
+
+	if (psde->pipe_sblk->maxvdeciexp) {
+		msm_property_install_range(&psde->property_info, "v_decimate",
+				0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
+				PLANE_PROP_V_DECIMATE);
+	}
+
+	if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
+		msm_property_install_volatile_range(&psde->property_info,
+			"scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
+		msm_property_install_blob(&psde->property_info, "lut_ed", 0,
+			PLANE_PROP_SCALER_LUT_ED);
+		msm_property_install_blob(&psde->property_info, "lut_cir", 0,
+			PLANE_PROP_SCALER_LUT_CIR);
+		msm_property_install_blob(&psde->property_info, "lut_sep", 0,
+			PLANE_PROP_SCALER_LUT_SEP);
+	} else if (psde->features & SDE_SSPP_SCALER) {
+		msm_property_install_volatile_range(&psde->property_info,
+			"scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
+	}
+
+	if (psde->features & BIT(SDE_SSPP_CSC)) {
+		msm_property_install_volatile_range(&psde->property_info,
+			"csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
+	}
+
+	if (psde->features & BIT(SDE_SSPP_HSIC)) {
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_HUE_V",
+			psde->pipe_sblk->hsic_blk.version >> 16);
+		msm_property_install_range(&psde->property_info,
+			feature_name, 0, 0, 0xFFFFFFFF, 0,
+			PLANE_PROP_HUE_ADJUST);
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_SATURATION_V",
+			psde->pipe_sblk->hsic_blk.version >> 16);
+		msm_property_install_range(&psde->property_info,
+			feature_name, 0, 0, 0xFFFFFFFF, 0,
+			PLANE_PROP_SATURATION_ADJUST);
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_VALUE_V",
+			psde->pipe_sblk->hsic_blk.version >> 16);
+		msm_property_install_range(&psde->property_info,
+			feature_name, 0, 0, 0xFFFFFFFF, 0,
+			PLANE_PROP_VALUE_ADJUST);
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_CONTRAST_V",
+			psde->pipe_sblk->hsic_blk.version >> 16);
+		msm_property_install_range(&psde->property_info,
+			feature_name, 0, 0, 0xFFFFFFFF, 0,
+			PLANE_PROP_CONTRAST_ADJUST);
+	}
+
+	/* standard properties */
+	msm_property_install_rotation(&psde->property_info,
+		BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
+
+	msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
+		e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
+
+	msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
+		e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
+
+	if (psde->pipe_hw->ops.setup_solidfill)
+		msm_property_install_range(&psde->property_info, "color_fill",
+				0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
+
+	info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
+	if (!info) {
+		SDE_ERROR("failed to allocate info memory\n");
+		return;
+	}
+
+	msm_property_install_blob(&psde->property_info, "capabilities",
+		DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
+	sde_kms_info_reset(info);
+
+	format_list = psde->pipe_sblk->format_list;
+	if (format_list) {
+		sde_kms_info_start(info, "pixel_formats");
+		while (format_list->fourcc_format) {
+			sde_kms_info_append_format(info,
+					format_list->fourcc_format,
+					format_list->modifier);
+			++format_list;
+		}
+		sde_kms_info_stop(info);
+	}
+
+	sde_kms_info_add_keyint(info, "max_linewidth",
+			psde->pipe_sblk->maxlinewidth);
+	sde_kms_info_add_keyint(info, "max_upscale",
+			psde->pipe_sblk->maxupscale);
+	sde_kms_info_add_keyint(info, "max_downscale",
+			psde->pipe_sblk->maxdwnscale);
+	sde_kms_info_add_keyint(info, "max_horizontal_deci",
+			psde->pipe_sblk->maxhdeciexp);
+	sde_kms_info_add_keyint(info, "max_vertical_deci",
+			psde->pipe_sblk->maxvdeciexp);
+	msm_property_set_blob(&psde->property_info, &psde->blob_info,
+			info->data, info->len, PLANE_PROP_INFO);
+
+	kfree(info);
+
+	if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_SKIN_COLOR_V",
+			psde->pipe_sblk->memcolor_blk.version >> 16);
+		msm_property_install_blob(&psde->property_info, feature_name, 0,
+			PLANE_PROP_SKIN_COLOR);
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_SKY_COLOR_V",
+			psde->pipe_sblk->memcolor_blk.version >> 16);
+		msm_property_install_blob(&psde->property_info, feature_name, 0,
+			PLANE_PROP_SKY_COLOR);
+		snprintf(feature_name, sizeof(feature_name), "%s%d",
+			"SDE_SSPP_FOLIAGE_COLOR_V",
+			psde->pipe_sblk->memcolor_blk.version >> 16);
+		msm_property_install_blob(&psde->property_info, feature_name, 0,
+			PLANE_PROP_FOLIAGE_COLOR);
+	}
+}
+
+static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
+{
+	struct sde_drm_csc_v1 csc_v1;
+	int i;
+
+	if (!psde) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	psde->csc_usr_ptr = NULL;
+	if (!usr_ptr) {
+		SDE_DEBUG_PLANE(psde, "csc data removed\n");
+		return;
+	}
+
+	if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
+		SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
+		return;
+	}
+
+	/* populate from user space */
+	for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
+		psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
+	for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
+		psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
+		psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
+	}
+	for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
+		psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
+		psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
+	}
+	psde->csc_usr_ptr = &psde->csc_cfg;
+}
+
+static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
+{
+	struct sde_drm_scaler_v1 scale_v1;
+	struct sde_hw_pixel_ext *pe;
+	int i;
+
+	if (!psde) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	psde->pixel_ext_usr = false;
+	if (!usr) {
+		SDE_DEBUG_PLANE(psde, "scale data removed\n");
+		return;
+	}
+
+	if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
+		SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
+		return;
+	}
+
+	/* populate from user space */
+	pe = &(psde->pixel_ext);
+	memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
+	for (i = 0; i < SDE_MAX_PLANES; i++) {
+		pe->init_phase_x[i] = scale_v1.init_phase_x[i];
+		pe->phase_step_x[i] = scale_v1.phase_step_x[i];
+		pe->init_phase_y[i] = scale_v1.init_phase_y[i];
+		pe->phase_step_y[i] = scale_v1.phase_step_y[i];
+
+		pe->horz_filter[i] = scale_v1.horz_filter[i];
+		pe->vert_filter[i] = scale_v1.vert_filter[i];
+	}
+	for (i = 0; i < SDE_MAX_PLANES; i++) {
+		pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
+		pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
+		pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
+		pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
+		pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
+
+		pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
+		pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
+		pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
+		pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
+		pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
+	}
+
+	psde->pixel_ext_usr = true;
+
+	SDE_DEBUG_PLANE(psde, "user property data copied\n");
+}
+
+static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
+		struct sde_plane_state *pstate, void *usr)
+{
+	struct sde_drm_scaler_v2 scale_v2;
+	struct sde_hw_pixel_ext *pe;
+	int i;
+	struct sde_hw_scaler3_cfg *cfg;
+
+	if (!psde) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	cfg = psde->scaler3_cfg;
+	psde->pixel_ext_usr = false;
+	if (!usr) {
+		SDE_DEBUG_PLANE(psde, "scale data removed\n");
+		return;
+	}
+
+	if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
+		SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
+		return;
+	}
+
+	/* populate from user space */
+	pe = &(psde->pixel_ext);
+	memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
+	cfg->enable = scale_v2.enable;
+	cfg->dir_en = scale_v2.dir_en;
+	for (i = 0; i < SDE_MAX_PLANES; i++) {
+		cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
+		cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
+		cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
+		cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
+
+		cfg->preload_x[i] = scale_v2.preload_x[i];
+		cfg->preload_y[i] = scale_v2.preload_y[i];
+		cfg->src_width[i] = scale_v2.src_width[i];
+		cfg->src_height[i] = scale_v2.src_height[i];
+	}
+	cfg->dst_width = scale_v2.dst_width;
+	cfg->dst_height = scale_v2.dst_height;
+
+	cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
+	cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
+	cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
+	cfg->blend_cfg = scale_v2.blend_cfg;
+
+	cfg->lut_flag = scale_v2.lut_flag;
+	cfg->dir_lut_idx = scale_v2.dir_lut_idx;
+	cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
+	cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
+	cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
+	cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
+
+	cfg->de.enable = scale_v2.de.enable;
+	cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
+	cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
+	cfg->de.clip = scale_v2.de.clip;
+	cfg->de.limit = scale_v2.de.limit;
+	cfg->de.thr_quiet = scale_v2.de.thr_quiet;
+	cfg->de.thr_dieout = scale_v2.de.thr_dieout;
+	cfg->de.thr_low = scale_v2.de.thr_low;
+	cfg->de.thr_high = scale_v2.de.thr_high;
+	cfg->de.prec_shift = scale_v2.de.prec_shift;
+	for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
+		cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
+		cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
+		cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
+	}
+	for (i = 0; i < SDE_MAX_PLANES; i++) {
+		pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
+		pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
+		pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
+		pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
+		pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
+
+		pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
+		pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
+		pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
+		pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
+		pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
+	}
+	psde->pixel_ext_usr = true;
+
+	SDE_DEBUG_PLANE(psde, "user property data copied\n");
+}
+
+static int sde_plane_atomic_set_property(struct drm_plane *plane,
+		struct drm_plane_state *state, struct drm_property *property,
+		uint64_t val)
+{
+	struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
+	struct sde_plane_state *pstate;
+	int idx, ret = -EINVAL;
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+	} else if (!state) {
+		SDE_ERROR_PLANE(psde, "invalid state\n");
+	} else {
+		pstate = to_sde_plane_state(state);
+		ret = msm_property_atomic_set(&psde->property_info,
+				pstate->property_values, pstate->property_blobs,
+				property, val);
+		if (!ret) {
+			idx = msm_property_index(&psde->property_info,
+					property);
+			switch (idx) {
+			case PLANE_PROP_INPUT_FENCE:
+				_sde_plane_set_input_fence(psde, pstate, val);
+				break;
+			case PLANE_PROP_CSC_V1:
+				_sde_plane_set_csc_v1(psde, (void *)val);
+				break;
+			case PLANE_PROP_SCALER_V1:
+				_sde_plane_set_scaler_v1(psde, (void *)val);
+				break;
+			case PLANE_PROP_SCALER_V2:
+				_sde_plane_set_scaler_v2(psde, pstate,
+					(void *)val);
+				break;
+			default:
+				/* nothing to do */
+				break;
+			}
+		}
+	}
+
+	return ret;
+}
+
+static int sde_plane_set_property(struct drm_plane *plane,
+		struct drm_property *property, uint64_t val)
+{
+	SDE_DEBUG("\n");
+
+	return sde_plane_atomic_set_property(plane,
+			plane->state, property, val);
+}
+
+static int sde_plane_atomic_get_property(struct drm_plane *plane,
+		const struct drm_plane_state *state,
+		struct drm_property *property, uint64_t *val)
+{
+	struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
+	struct sde_plane_state *pstate;
+	int ret = -EINVAL;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+	} else if (!state) {
+		SDE_ERROR("invalid state\n");
+	} else {
+		SDE_DEBUG_PLANE(psde, "\n");
+		pstate = to_sde_plane_state(state);
+		ret = msm_property_atomic_get(&psde->property_info,
+				pstate->property_values, pstate->property_blobs,
+				property, val);
+	}
+
+	return ret;
+}
+
+static void sde_plane_destroy(struct drm_plane *plane)
+{
+	struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	if (psde) {
+		_sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
+
+		debugfs_remove_recursive(psde->debugfs_root);
+
+		if (psde->blob_info)
+			drm_property_unreference_blob(psde->blob_info);
+		msm_property_destroy(&psde->property_info);
+		mutex_destroy(&psde->lock);
+
+		drm_plane_helper_disable(plane);
+
+		/* this will destroy the states as well */
+		drm_plane_cleanup(plane);
+
+		if (psde->pipe_hw)
+			sde_hw_sspp_destroy(psde->pipe_hw);
+
+		kfree(psde);
+	}
+}
+
+static void sde_plane_destroy_state(struct drm_plane *plane,
+		struct drm_plane_state *state)
+{
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+
+	if (!plane || !state) {
+		SDE_ERROR("invalid arg(s), plane %d state %d\n",
+				plane != 0, state != 0);
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+	pstate = to_sde_plane_state(state);
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	/* remove ref count for frame buffers */
+	if (state->fb)
+		drm_framebuffer_unreference(state->fb);
+
+	/* remove ref count for fence */
+	if (pstate->input_fence)
+		sde_sync_put(pstate->input_fence);
+
+	/* destroy value helper */
+	msm_property_destroy_state(&psde->property_info, pstate,
+			pstate->property_values, pstate->property_blobs);
+}
+
+static struct drm_plane_state *
+sde_plane_duplicate_state(struct drm_plane *plane)
+{
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+	struct sde_plane_state *old_state;
+	uint64_t input_fence_default;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+		return NULL;
+	} else if (!plane->state) {
+		SDE_ERROR("invalid plane state\n");
+		return NULL;
+	}
+
+	old_state = to_sde_plane_state(plane->state);
+	psde = to_sde_plane(plane);
+	pstate = msm_property_alloc_state(&psde->property_info);
+	if (!pstate) {
+		SDE_ERROR_PLANE(psde, "failed to allocate state\n");
+		return NULL;
+	}
+
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	/* duplicate value helper */
+	msm_property_duplicate_state(&psde->property_info, old_state, pstate,
+			pstate->property_values, pstate->property_blobs);
+
+	/* add ref count for frame buffer */
+	if (pstate->base.fb)
+		drm_framebuffer_reference(pstate->base.fb);
+
+	/* clear out any input fence */
+	pstate->input_fence = 0;
+	input_fence_default = msm_property_get_default(
+			&psde->property_info, PLANE_PROP_INPUT_FENCE);
+	msm_property_set_property(&psde->property_info, pstate->property_values,
+			PLANE_PROP_INPUT_FENCE, input_fence_default);
+
+	pstate->dirty = 0x0;
+	pstate->pending = false;
+
+	return &pstate->base;
+}
+
+static void sde_plane_reset(struct drm_plane *plane)
+{
+	struct sde_plane *psde;
+	struct sde_plane_state *pstate;
+
+	if (!plane) {
+		SDE_ERROR("invalid plane\n");
+		return;
+	}
+
+	psde = to_sde_plane(plane);
+	SDE_DEBUG_PLANE(psde, "\n");
+
+	/* remove previous state, if present */
+	if (plane->state) {
+		sde_plane_destroy_state(plane, plane->state);
+		plane->state = 0;
+	}
+
+	pstate = msm_property_alloc_state(&psde->property_info);
+	if (!pstate) {
+		SDE_ERROR_PLANE(psde, "failed to allocate state\n");
+		return;
+	}
+
+	/* reset value helper */
+	msm_property_reset_state(&psde->property_info, pstate,
+			pstate->property_values, pstate->property_blobs);
+
+	pstate->base.plane = plane;
+
+	plane->state = &pstate->base;
+}
+
+static const struct drm_plane_funcs sde_plane_funcs = {
+		.update_plane = drm_atomic_helper_update_plane,
+		.disable_plane = drm_atomic_helper_disable_plane,
+		.destroy = sde_plane_destroy,
+		.set_property = sde_plane_set_property,
+		.atomic_set_property = sde_plane_atomic_set_property,
+		.atomic_get_property = sde_plane_atomic_get_property,
+		.reset = sde_plane_reset,
+		.atomic_duplicate_state = sde_plane_duplicate_state,
+		.atomic_destroy_state = sde_plane_destroy_state,
+};
+
+static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
+		.prepare_fb = sde_plane_prepare_fb,
+		.cleanup_fb = sde_plane_cleanup_fb,
+		.atomic_check = sde_plane_atomic_check,
+		.atomic_update = sde_plane_atomic_update,
+};
+
+enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
+{
+	return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
+}
+
+static ssize_t _sde_plane_danger_read(struct file *file,
+			char __user *buff, size_t count, loff_t *ppos)
+{
+	struct sde_kms *kms = file->private_data;
+	struct sde_mdss_cfg *cfg = kms->catalog;
+	int len = 0;
+	char buf[40] = {'\0'};
+
+	if (!cfg)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0; /* the end */
+
+	len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
+	if (len < 0 || len >= sizeof(buf))
+		return 0;
+
+	if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
+		return -EFAULT;
+
+	*ppos += len;   /* increase offset */
+
+	return len;
+}
+
+static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
+{
+	struct drm_plane *plane;
+
+	drm_for_each_plane(plane, kms->dev) {
+		if (plane->fb && plane->state) {
+			sde_plane_danger_signal_ctrl(plane, enable);
+			SDE_DEBUG("plane:%d img:%dx%d ",
+				plane->base.id, plane->fb->width,
+				plane->fb->height);
+			SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
+				plane->state->src_x >> 16,
+				plane->state->src_y >> 16,
+				plane->state->src_w >> 16,
+				plane->state->src_h >> 16,
+				plane->state->crtc_x, plane->state->crtc_y,
+				plane->state->crtc_w, plane->state->crtc_h);
+		} else {
+			SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
+		}
+	}
+}
+
+static ssize_t _sde_plane_danger_write(struct file *file,
+		    const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct sde_kms *kms = file->private_data;
+	struct sde_mdss_cfg *cfg = kms->catalog;
+	int disable_panic;
+	char buf[10];
+
+	if (!cfg)
+		return -EFAULT;
+
+	if (count >= sizeof(buf))
+		return -EFAULT;
+
+	if (copy_from_user(buf, user_buf, count))
+		return -EFAULT;
+
+	buf[count] = 0;	/* end of string */
+
+	if (kstrtoint(buf, 0, &disable_panic))
+		return -EFAULT;
+
+	if (disable_panic) {
+		/* Disable panic signal for all active pipes */
+		SDE_DEBUG("Disabling danger:\n");
+		_sde_plane_set_danger_state(kms, false);
+		kms->has_danger_ctrl = false;
+	} else {
+		/* Enable panic signal for all active pipes */
+		SDE_DEBUG("Enabling danger:\n");
+		kms->has_danger_ctrl = true;
+		_sde_plane_set_danger_state(kms, true);
+	}
+
+	return count;
+}
+
+static const struct file_operations sde_plane_danger_enable = {
+	.open = simple_open,
+	.read = _sde_plane_danger_read,
+	.write = _sde_plane_danger_write,
+};
+
+static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
+{
+	const struct sde_sspp_sub_blks *sblk = 0;
+	const struct sde_sspp_cfg *cfg = 0;
+
+	if (psde && psde->pipe_hw)
+		cfg = psde->pipe_hw->cap;
+	if (cfg)
+		sblk = cfg->sblk;
+
+	if (kms && sblk) {
+		/* create overall sub-directory for the pipe */
+		psde->debugfs_root =
+			debugfs_create_dir(psde->pipe_name,
+					sde_debugfs_get_root(kms));
+		if (psde->debugfs_root) {
+			/* don't error check these */
+			debugfs_create_x32("features", S_IRUGO | S_IWUSR,
+					psde->debugfs_root, &psde->features);
+
+			/* add register dump support */
+			sde_debugfs_setup_regset32(&psde->debugfs_src,
+					sblk->src_blk.base + cfg->base,
+					sblk->src_blk.len,
+					kms);
+			sde_debugfs_create_regset32("src_blk", S_IRUGO,
+					psde->debugfs_root, &psde->debugfs_src);
+
+			sde_debugfs_setup_regset32(&psde->debugfs_scaler,
+					sblk->scaler_blk.base + cfg->base,
+					sblk->scaler_blk.len,
+					kms);
+			sde_debugfs_create_regset32("scaler_blk", S_IRUGO,
+					psde->debugfs_root,
+					&psde->debugfs_scaler);
+
+			sde_debugfs_setup_regset32(&psde->debugfs_csc,
+					sblk->csc_blk.base + cfg->base,
+					sblk->csc_blk.len,
+					kms);
+			sde_debugfs_create_regset32("csc_blk", S_IRUGO,
+					psde->debugfs_root, &psde->debugfs_csc);
+
+			debugfs_create_u32("xin_id",
+					S_IRUGO,
+					psde->debugfs_root,
+					(u32 *) &cfg->xin_id);
+			debugfs_create_u32("clk_ctrl",
+					S_IRUGO,
+					psde->debugfs_root,
+					(u32 *) &cfg->clk_ctrl);
+			debugfs_create_x32("creq_vblank",
+					S_IRUGO | S_IWUSR,
+					psde->debugfs_root,
+					(u32 *) &sblk->creq_vblank);
+			debugfs_create_x32("danger_vblank",
+					S_IRUGO | S_IWUSR,
+					psde->debugfs_root,
+					(u32 *) &sblk->danger_vblank);
+
+			debugfs_create_file("disable_danger",
+					S_IRUGO | S_IWUSR,
+					psde->debugfs_root,
+					kms, &sde_plane_danger_enable);
+		}
+	}
+}
+
+/* initialize plane */
+struct drm_plane *sde_plane_init(struct drm_device *dev,
+		uint32_t pipe, bool primary_plane,
+		unsigned long possible_crtcs)
+{
+	struct drm_plane *plane = NULL;
+	struct sde_plane *psde;
+	struct msm_drm_private *priv;
+	struct sde_kms *kms;
+	enum drm_plane_type type;
+	int ret = -EINVAL;
+
+	if (!dev) {
+		SDE_ERROR("[%u]device is NULL\n", pipe);
+		goto exit;
+	}
+
+	priv = dev->dev_private;
+	if (!priv) {
+		SDE_ERROR("[%u]private data is NULL\n", pipe);
+		goto exit;
+	}
+
+	if (!priv->kms) {
+		SDE_ERROR("[%u]invalid KMS reference\n", pipe);
+		goto exit;
+	}
+	kms = to_sde_kms(priv->kms);
+
+	if (!kms->catalog) {
+		SDE_ERROR("[%u]invalid catalog reference\n", pipe);
+		goto exit;
+	}
+
+	/* create and zero local structure */
+	psde = kzalloc(sizeof(*psde), GFP_KERNEL);
+	if (!psde) {
+		SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	/* cache local stuff for later */
+	plane = &psde->base;
+	psde->pipe = pipe;
+	psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
+
+	/* initialize underlying h/w driver */
+	psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
+	if (IS_ERR(psde->pipe_hw)) {
+		SDE_ERROR("[%u]SSPP init failed\n", pipe);
+		ret = PTR_ERR(psde->pipe_hw);
+		goto clean_plane;
+	} else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
+		SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
+		goto clean_sspp;
+	}
+
+	/* cache features mask for later */
+	psde->features = psde->pipe_hw->cap->features;
+	psde->pipe_sblk = psde->pipe_hw->cap->sblk;
+	if (!psde->pipe_sblk) {
+		SDE_ERROR("[%u]invalid sblk\n", pipe);
+		goto clean_sspp;
+	}
+
+	if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
+		psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
+			GFP_KERNEL);
+		if (!psde->scaler3_cfg) {
+			SDE_ERROR("[%u]failed to allocate scale struct\n",
+				pipe);
+			ret = -ENOMEM;
+			goto clean_sspp;
+		}
+	}
+
+	/* add plane to DRM framework */
+	psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
+			psde->formats,
+			0,
+			ARRAY_SIZE(psde->formats));
+
+	if (!psde->nformats) {
+		SDE_ERROR("[%u]no valid formats for plane\n", pipe);
+		goto clean_sspp;
+	}
+
+	if (psde->features & BIT(SDE_SSPP_CURSOR))
+		type = DRM_PLANE_TYPE_CURSOR;
+	else if (primary_plane)
+		type = DRM_PLANE_TYPE_PRIMARY;
+	else
+		type = DRM_PLANE_TYPE_OVERLAY;
+	ret = drm_universal_plane_init(dev, plane, possible_crtcs,
+			&sde_plane_funcs, psde->formats, psde->nformats, type);
+	if (ret)
+		goto clean_sspp;
+
+	/* success! finalize initialization */
+	drm_plane_helper_add(plane, &sde_plane_helper_funcs);
+
+	msm_property_init(&psde->property_info, &plane->base, dev,
+			priv->plane_property, psde->property_data,
+			PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
+			sizeof(struct sde_plane_state));
+
+	_sde_plane_install_properties(plane, kms->catalog);
+
+	/* save user friendly pipe name for later */
+	snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
+
+	mutex_init(&psde->lock);
+
+	_sde_plane_init_debugfs(psde, kms);
+
+	DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
+	return plane;
+
+clean_sspp:
+	if (psde && psde->pipe_hw)
+		sde_hw_sspp_destroy(psde->pipe_hw);
+
+	if (psde && psde->scaler3_cfg)
+		kfree(psde->scaler3_cfg);
+clean_plane:
+	kfree(psde);
+exit:
+	return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h
new file mode 100644
index 0000000000000000000000000000000000000000..1514f633c61e63d39508aea2af1009637f41c134
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_plane.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDE_PLANE_H_
+#define _SDE_PLANE_H_
+
+#include <drm/drm_crtc.h>
+
+#include "msm_prop.h"
+#include "sde_hw_mdss.h"
+
+/**
+ * struct sde_plane_state: Define sde extension of drm plane state object
+ * @base:	base drm plane state object
+ * @property_values:	cached plane property values
+ * @property_blobs:	blob properties
+ * @input_fence:	dereferenced input fence pointer
+ * @stage:	assigned by crtc blender
+ * @dirty:	bitmask for which pipe h/w config functions need to be updated
+ * @pending:	whether the current update is still pending
+ */
+struct sde_plane_state {
+	struct drm_plane_state base;
+	uint64_t property_values[PLANE_PROP_COUNT];
+	struct drm_property_blob *property_blobs[PLANE_PROP_BLOBCOUNT];
+	void *input_fence;
+	enum sde_stage stage;
+	uint32_t dirty;
+	bool pending;
+};
+
+#define to_sde_plane_state(x) \
+	container_of(x, struct sde_plane_state, base)
+
+/**
+ * sde_plane_get_property - Query integer value of plane property
+ * @S: Pointer to plane state
+ * @X: Property index, from enum msm_mdp_plane_property
+ * Returns: Integer value of requested property
+ */
+#define sde_plane_get_property(S, X) \
+	((S) && ((X) < PLANE_PROP_COUNT) ? ((S)->property_values[(X)]) : 0)
+
+/**
+ * sde_plane_pipe - return sspp identifier for the given plane
+ * @plane:   Pointer to DRM plane object
+ * Returns: sspp identifier of the given plane
+ */
+enum sde_sspp sde_plane_pipe(struct drm_plane *plane);
+
+/**
+ * sde_plane_flush - final plane operations before commit flush
+ * @plane: Pointer to drm plane structure
+ */
+void sde_plane_flush(struct drm_plane *plane);
+
+/**
+ * sde_plane_init - create new sde plane for the given pipe
+ * @dev:   Pointer to DRM device
+ * @pipe:  sde hardware pipe identifier
+ * @primary_plane: true if this pipe is primary plane for crtc
+ * @possible_crtcs: bitmask of crtc that can be attached to the given pipe
+ */
+struct drm_plane *sde_plane_init(struct drm_device *dev,
+		uint32_t pipe, bool primary_plane,
+		unsigned long possible_crtcs);
+
+/**
+ * sde_plane_wait_input_fence - wait for input fence object
+ * @plane:   Pointer to DRM plane object
+ * @wait_ms: Wait timeout value
+ * Returns: Zero on success
+ */
+int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms);
+
+/**
+ * sde_plane_color_fill - enables color fill on plane
+ * @plane:  Pointer to DRM plane object
+ * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
+ * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
+ * Returns: 0 on success
+ */
+int sde_plane_color_fill(struct drm_plane *plane,
+		uint32_t color, uint32_t alpha);
+
+#endif /* _SDE_PLANE_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_rm.c b/drivers/gpu/drm/msm/sde/sde_rm.c
new file mode 100644
index 0000000000000000000000000000000000000000..1d27b27d265c0a9deb2509c8d12f90ac8a2c0575
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_rm.c
@@ -0,0 +1,1262 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"[drm:%s] " fmt, __func__
+#include "sde_kms.h"
+#include "sde_hw_lm.h"
+#include "sde_hw_ctl.h"
+#include "sde_hw_cdm.h"
+#include "sde_hw_dspp.h"
+#include "sde_hw_pingpong.h"
+#include "sde_hw_intf.h"
+#include "sde_hw_wb.h"
+#include "sde_encoder.h"
+#include "sde_connector.h"
+
+#define RESERVED_BY_OTHER(h, r) \
+	((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
+
+#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
+#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
+#define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
+#define RM_RQ_PPSPLIT(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_PPSPLIT))
+#define RM_RQ_FORCE_TILING(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_FORCE_TILING))
+
+/**
+ * struct sde_rm_requirements - Reservation requirements parameter bundle
+ * @top_name:	DRM<->HW topology use case user is trying to enable
+ * @dspp:	Whether the user requires a DSPP
+ * @num_lm:	Number of layer mixers needed in the use case
+ * @hw_res:	Hardware resources required as reported by the encoders
+ */
+struct sde_rm_requirements {
+	enum sde_rm_topology_name top_name;
+	uint64_t top_ctrl;
+	int num_lm;
+	int num_ctl;
+	bool needs_split_display;
+	struct sde_encoder_hw_resources hw_res;
+};
+
+/**
+ * struct sde_rm_rsvp - Use Case Reservation tagging structure
+ *	Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
+ *	By using as a tag, rather than lists of pointers to HW blocks used
+ *	we can avoid some list management since we don't know how many blocks
+ *	of each type a given use case may require.
+ * @list:	List head for list of all reservations
+ * @seq:	Global RSVP sequence number for debugging, especially for
+ *		differentiating differenct allocations for same encoder.
+ * @enc_id:	Reservations are tracked by Encoder DRM object ID.
+ *		CRTCs may be connected to multiple Encoders.
+ *		An encoder or connector id identifies the display path.
+ * @topology	DRM<->HW topology use case
+ */
+struct sde_rm_rsvp {
+	struct list_head list;
+	uint32_t seq;
+	uint32_t enc_id;
+	enum sde_rm_topology_name topology;
+};
+
+/**
+ * struct sde_rm_hw_blk - hardware block tracking list member
+ * @list:	List head for list of all hardware blocks tracking items
+ * @rsvp:	Pointer to use case reservation if reserved by a client
+ * @rsvp_nxt:	Temporary pointer used during reservation to the incoming
+ *		request. Will be swapped into rsvp if proposal is accepted
+ * @type:	Type of hardware block this structure tracks
+ * @id:		Hardware ID number, within it's own space, ie. LM_X
+ * @catalog:	Pointer to the hardware catalog entry for this block
+ * @hw:		Pointer to the hardware register access object for this block
+ */
+struct sde_rm_hw_blk {
+	struct list_head list;
+	struct sde_rm_rsvp *rsvp;
+	struct sde_rm_rsvp *rsvp_nxt;
+	enum sde_hw_blk_type type;
+	const char *type_name;
+	uint32_t id;
+	void *catalog;
+	void *hw;
+};
+
+/**
+ * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
+ */
+enum sde_rm_dbg_rsvp_stage {
+	SDE_RM_STAGE_BEGIN,
+	SDE_RM_STAGE_AFTER_CLEAR,
+	SDE_RM_STAGE_AFTER_RSVPNEXT,
+	SDE_RM_STAGE_FINAL
+};
+
+static void _sde_rm_print_rsvps(
+		struct sde_rm *rm,
+		enum sde_rm_dbg_rsvp_stage stage)
+{
+	struct sde_rm_rsvp *rsvp;
+	struct sde_rm_hw_blk *blk;
+	enum sde_hw_blk_type type;
+
+	SDE_DEBUG("%d\n", stage);
+
+	list_for_each_entry(rsvp, &rm->rsvps, list) {
+		SDE_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
+				rsvp->enc_id, rsvp->topology);
+		SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
+	}
+
+	for (type = 0; type < SDE_HW_BLK_MAX; type++) {
+		list_for_each_entry(blk, &rm->hw_blks[type], list) {
+			if (!blk->rsvp && !blk->rsvp_nxt)
+				continue;
+
+			SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %s %d\n", stage,
+				(blk->rsvp) ? blk->rsvp->seq : 0,
+				(blk->rsvp) ? blk->rsvp->enc_id : 0,
+				(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
+				(blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
+				blk->type_name, blk->id);
+
+			SDE_EVT32(stage,
+				(blk->rsvp) ? blk->rsvp->seq : 0,
+				(blk->rsvp) ? blk->rsvp->enc_id : 0,
+				(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
+				(blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
+				blk->type, blk->id);
+		}
+	}
+}
+
+struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
+{
+	return rm->hw_mdp;
+}
+
+void sde_rm_init_hw_iter(
+		struct sde_rm_hw_iter *iter,
+		uint32_t enc_id,
+		enum sde_hw_blk_type type)
+{
+	memset(iter, 0, sizeof(*iter));
+	iter->enc_id = enc_id;
+	iter->type = type;
+}
+
+bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
+{
+	struct list_head *blk_list;
+
+	if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
+		SDE_ERROR("invalid rm\n");
+		return false;
+	}
+
+	i->hw = NULL;
+	blk_list = &rm->hw_blks[i->type];
+
+	if (i->blk && (&i->blk->list == blk_list)) {
+		SDE_ERROR("attempt resume iteration past last\n");
+		return false;
+	}
+
+	i->blk = list_prepare_entry(i->blk, blk_list, list);
+
+	list_for_each_entry_continue(i->blk, blk_list, list) {
+		struct sde_rm_rsvp *rsvp = i->blk->rsvp;
+
+		if (i->blk->type != i->type) {
+			SDE_ERROR("found incorrect block type %d on %d list\n",
+					i->blk->type, i->type);
+			return false;
+		}
+
+		if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
+			i->hw = i->blk->hw;
+			SDE_DEBUG("found type %d %s id %d for enc %d\n",
+					i->type, i->blk->type_name, i->blk->id,
+					i->enc_id);
+			return true;
+		}
+	}
+
+	SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
+
+	return false;
+}
+
+static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, void *hw)
+{
+	switch (type) {
+	case SDE_HW_BLK_LM:
+		sde_hw_lm_destroy(hw);
+		break;
+	case SDE_HW_BLK_DSPP:
+		sde_hw_dspp_destroy(hw);
+		break;
+	case SDE_HW_BLK_CTL:
+		sde_hw_ctl_destroy(hw);
+		break;
+	case SDE_HW_BLK_CDM:
+		sde_hw_cdm_destroy(hw);
+		break;
+	case SDE_HW_BLK_PINGPONG:
+		sde_hw_pingpong_destroy(hw);
+		break;
+	case SDE_HW_BLK_INTF:
+		sde_hw_intf_destroy(hw);
+		break;
+	case SDE_HW_BLK_WB:
+		sde_hw_wb_destroy(hw);
+		break;
+	case SDE_HW_BLK_SSPP:
+		/* SSPPs are not managed by the resource manager */
+	case SDE_HW_BLK_TOP:
+		/* Top is a singleton, not managed in hw_blks list */
+	case SDE_HW_BLK_MAX:
+	default:
+		SDE_ERROR("unsupported block type %d\n", type);
+		break;
+	}
+}
+
+int sde_rm_destroy(struct sde_rm *rm)
+{
+
+	struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
+	struct sde_rm_hw_blk *hw_cur, *hw_nxt;
+	enum sde_hw_blk_type type;
+
+	if (!rm) {
+		SDE_ERROR("invalid rm\n");
+		return -EINVAL;
+	}
+
+	list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
+		list_del(&rsvp_cur->list);
+		kfree(rsvp_cur);
+	}
+
+
+	for (type = 0; type < SDE_HW_BLK_MAX; type++) {
+		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
+				list) {
+			list_del(&hw_cur->list);
+			_sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
+			kfree(hw_cur);
+		}
+	}
+
+	sde_hw_mdp_destroy(rm->hw_mdp);
+	rm->hw_mdp = NULL;
+
+	return 0;
+}
+
+static int _sde_rm_hw_blk_create(
+		struct sde_rm *rm,
+		struct sde_mdss_cfg *cat,
+		void *mmio,
+		enum sde_hw_blk_type type,
+		uint32_t id,
+		void *hw_catalog_info)
+{
+	struct sde_rm_hw_blk *blk;
+	struct sde_hw_mdp *hw_mdp;
+	const char *name;
+	void *hw;
+
+	hw_mdp = rm->hw_mdp;
+
+	switch (type) {
+	case SDE_HW_BLK_LM:
+		hw = sde_hw_lm_init(id, mmio, cat);
+		name = "lm";
+		break;
+	case SDE_HW_BLK_DSPP:
+		hw = sde_hw_dspp_init(id, mmio, cat);
+		name = "dspp";
+		break;
+	case SDE_HW_BLK_CTL:
+		hw = sde_hw_ctl_init(id, mmio, cat);
+		name = "ctl";
+		break;
+	case SDE_HW_BLK_CDM:
+		hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
+		name = "cdm";
+		break;
+	case SDE_HW_BLK_PINGPONG:
+		hw = sde_hw_pingpong_init(id, mmio, cat);
+		name = "pp";
+		break;
+	case SDE_HW_BLK_INTF:
+		hw = sde_hw_intf_init(id, mmio, cat);
+		name = "intf";
+		break;
+	case SDE_HW_BLK_WB:
+		hw = sde_hw_wb_init(id, mmio, cat, hw_mdp);
+		name = "wb";
+		break;
+	case SDE_HW_BLK_SSPP:
+		/* SSPPs are not managed by the resource manager */
+	case SDE_HW_BLK_TOP:
+		/* Top is a singleton, not managed in hw_blks list */
+	case SDE_HW_BLK_MAX:
+	default:
+		SDE_ERROR("unsupported block type %d\n", type);
+		return -EINVAL;
+	}
+
+	if (IS_ERR_OR_NULL(hw)) {
+		SDE_ERROR("failed hw object creation: type %d, err %ld\n",
+				type, PTR_ERR(hw));
+		return -EFAULT;
+	}
+
+	blk = kzalloc(sizeof(*blk), GFP_KERNEL);
+	if (!blk) {
+		_sde_rm_hw_destroy(type, hw);
+		return -ENOMEM;
+	}
+
+	blk->type_name = name;
+	blk->type = type;
+	blk->id = id;
+	blk->catalog = hw_catalog_info;
+	blk->hw = hw;
+	list_add_tail(&blk->list, &rm->hw_blks[type]);
+
+	return 0;
+}
+
+int sde_rm_init(struct sde_rm *rm,
+		struct sde_mdss_cfg *cat,
+		void *mmio,
+		struct drm_device *dev)
+{
+	int rc, i;
+	enum sde_hw_blk_type type;
+
+	if (!rm || !cat || !mmio || !dev) {
+		SDE_ERROR("invalid kms\n");
+		return -EINVAL;
+	}
+
+	/* Clear, setup lists */
+	memset(rm, 0, sizeof(*rm));
+	INIT_LIST_HEAD(&rm->rsvps);
+	for (type = 0; type < SDE_HW_BLK_MAX; type++)
+		INIT_LIST_HEAD(&rm->hw_blks[type]);
+
+	/* Some of the sub-blocks require an mdptop to be created */
+	rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
+	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
+		rc = PTR_ERR(rm->hw_mdp);
+		rm->hw_mdp = NULL;
+		SDE_ERROR("failed: mdp hw not available\n");
+		goto fail;
+	}
+
+	/* Interrogate HW catalog and create tracking items for hw blocks */
+	for (i = 0; i < cat->mixer_count; i++) {
+		struct sde_lm_cfg *lm = &cat->mixer[i];
+
+		if (lm->pingpong == PINGPONG_MAX) {
+			SDE_DEBUG("skip mixer %d without pingpong\n", lm->id);
+			continue;
+		}
+
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
+				cat->mixer[i].id, &cat->mixer[i]);
+		if (rc) {
+			SDE_ERROR("failed: lm hw not available\n");
+			goto fail;
+		}
+
+		if (!rm->lm_max_width) {
+			rm->lm_max_width = lm->sblk->maxwidth;
+		} else if (rm->lm_max_width != lm->sblk->maxwidth) {
+			/*
+			 * Don't expect to have hw where lm max widths differ.
+			 * If found, take the min.
+			 */
+			SDE_ERROR("unsupported: lm maxwidth differs\n");
+			if (rm->lm_max_width > lm->sblk->maxwidth)
+				rm->lm_max_width = lm->sblk->maxwidth;
+		}
+	}
+
+	for (i = 0; i < cat->dspp_count; i++) {
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
+				cat->dspp[i].id, &cat->dspp[i]);
+		if (rc) {
+			SDE_ERROR("failed: dspp hw not available\n");
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < cat->pingpong_count; i++) {
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
+				cat->pingpong[i].id, &cat->pingpong[i]);
+		if (rc) {
+			SDE_ERROR("failed: pp hw not available\n");
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < cat->intf_count; i++) {
+		if (cat->intf[i].type == INTF_NONE) {
+			SDE_DEBUG("skip intf %d with type none\n", i);
+			continue;
+		}
+
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
+				cat->intf[i].id, &cat->intf[i]);
+		if (rc) {
+			SDE_ERROR("failed: intf hw not available\n");
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < cat->wb_count; i++) {
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
+				cat->wb[i].id, &cat->wb[i]);
+		if (rc) {
+			SDE_ERROR("failed: wb hw not available\n");
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < cat->ctl_count; i++) {
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
+				cat->ctl[i].id, &cat->ctl[i]);
+		if (rc) {
+			SDE_ERROR("failed: ctl hw not available\n");
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < cat->cdm_count; i++) {
+		rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
+				cat->cdm[i].id, &cat->cdm[i]);
+		if (rc) {
+			SDE_ERROR("failed: cdm hw not available\n");
+			goto fail;
+		}
+	}
+
+	return 0;
+
+fail:
+	sde_rm_destroy(rm);
+
+	return rc;
+}
+
+/**
+ * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
+ *	proposed use case requirements, incl. hardwired dependent blocks like
+ *	pingpong, and dspp.
+ * @rm: sde resource manager handle
+ * @rsvp: reservation currently being created
+ * @reqs: proposed use case requirements
+ * @lm: proposed layer mixer, function checks if lm, and all other hardwired
+ *      blocks connected to the lm (pp, dspp) are available and appropriate
+ * @dspp: output parameter, dspp block attached to the layer mixer.
+ *        NULL if dspp was not available, or not matching requirements.
+ * @pp: output parameter, pingpong block attached to the layer mixer.
+ *      NULL if dspp was not available, or not matching requirements.
+ * @primary_lm: if non-null, this function check if lm is compatible primary_lm
+ *              as well as satisfying all other requirements
+ * @Return: true if lm matches all requirements, false otherwise
+ */
+static bool _sde_rm_check_lm_and_get_connected_blks(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct sde_rm_requirements *reqs,
+		struct sde_rm_hw_blk *lm,
+		struct sde_rm_hw_blk **dspp,
+		struct sde_rm_hw_blk **pp,
+		struct sde_rm_hw_blk *primary_lm)
+{
+	struct sde_lm_cfg *lm_cfg = (struct sde_lm_cfg *)lm->catalog;
+	struct sde_pingpong_cfg *pp_cfg;
+	struct sde_rm_hw_iter iter;
+
+	*dspp = NULL;
+	*pp = NULL;
+
+	SDE_DEBUG("check lm %d: dspp %d pp %d\n", lm_cfg->id, lm_cfg->dspp,
+			lm_cfg->pingpong);
+
+	/* Check if this layer mixer is a peer of the proposed primary LM */
+	if (primary_lm) {
+		struct sde_lm_cfg *prim_lm_cfg =
+				(struct sde_lm_cfg *)primary_lm->catalog;
+
+		if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
+			SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
+					prim_lm_cfg->id);
+			return false;
+		}
+	}
+
+	/* Matches user requirements? */
+	if ((RM_RQ_DSPP(reqs) && lm_cfg->dspp == DSPP_MAX) ||
+			(!RM_RQ_DSPP(reqs) && lm_cfg->dspp != DSPP_MAX)) {
+		SDE_DEBUG("dspp req mismatch lm %d reqdspp %d, lm->dspp %d\n",
+				lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
+				lm_cfg->dspp);
+		return false;
+	}
+
+	/* Already reserved? */
+	if (RESERVED_BY_OTHER(lm, rsvp)) {
+		SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
+		return false;
+	}
+
+	if (lm_cfg->dspp != DSPP_MAX) {
+		sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
+		while (sde_rm_get_hw(rm, &iter)) {
+			if (iter.blk->id == lm_cfg->dspp) {
+				*dspp = iter.blk;
+				break;
+			}
+		}
+
+		if (!*dspp) {
+			SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
+					lm_cfg->dspp);
+			return false;
+		}
+
+		if (RESERVED_BY_OTHER(*dspp, rsvp)) {
+			SDE_DEBUG("lm %d dspp %d already reserved\n",
+					lm->id, (*dspp)->id);
+			return false;
+		}
+	}
+
+	sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
+	while (sde_rm_get_hw(rm, &iter)) {
+		if (iter.blk->id == lm_cfg->pingpong) {
+			*pp = iter.blk;
+			break;
+		}
+	}
+
+	if (!*pp) {
+		SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
+		return false;
+	}
+
+	if (RESERVED_BY_OTHER(*pp, rsvp)) {
+		SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
+				(*pp)->id);
+		*dspp = NULL;
+		return false;
+	}
+
+	pp_cfg = (struct sde_pingpong_cfg *)((*pp)->catalog);
+	if ((reqs->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
+			!(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
+		SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
+		*dspp = NULL;
+		return false;
+	}
+
+	return true;
+}
+
+static int _sde_rm_reserve_lms(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct sde_rm_requirements *reqs)
+
+{
+	struct sde_rm_hw_blk *lm[MAX_BLOCKS];
+	struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
+	struct sde_rm_hw_blk *pp[MAX_BLOCKS];
+	struct sde_rm_hw_iter iter_i, iter_j;
+	int lm_count = 0;
+	int i, rc = 0;
+
+	if (!reqs->num_lm) {
+		SDE_ERROR("invalid number of lm: %d\n", reqs->num_lm);
+		return -EINVAL;
+	}
+
+	/* Find a primary mixer */
+	sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
+	while (lm_count != reqs->num_lm && sde_rm_get_hw(rm, &iter_i)) {
+		memset(&lm, 0, sizeof(lm));
+		memset(&dspp, 0, sizeof(dspp));
+		memset(&pp, 0, sizeof(pp));
+
+		lm_count = 0;
+		lm[lm_count] = iter_i.blk;
+
+		if (!_sde_rm_check_lm_and_get_connected_blks(rm, rsvp, reqs,
+				lm[lm_count], &dspp[lm_count], &pp[lm_count],
+				NULL))
+			continue;
+
+		++lm_count;
+
+		/* Valid primary mixer found, find matching peers */
+		sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
+
+		while (lm_count != reqs->num_lm && sde_rm_get_hw(rm, &iter_j)) {
+			if (iter_i.blk == iter_j.blk)
+				continue;
+
+			if (!_sde_rm_check_lm_and_get_connected_blks(rm, rsvp,
+					reqs, iter_j.blk, &dspp[lm_count],
+					&pp[lm_count], iter_i.blk))
+				continue;
+
+			lm[lm_count] = iter_j.blk;
+			++lm_count;
+		}
+	}
+
+	if (lm_count != reqs->num_lm) {
+		SDE_DEBUG("unable to find appropriate mixers\n");
+		return -ENAVAIL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lm); i++) {
+		if (!lm[i])
+			break;
+
+		lm[i]->rsvp_nxt = rsvp;
+		pp[i]->rsvp_nxt = rsvp;
+		if (dspp[i])
+			dspp[i]->rsvp_nxt = rsvp;
+
+		SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
+				dspp[i] ? dspp[i]->id : 0);
+	}
+
+	if (reqs->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
+		/* reserve a free PINGPONG_SLAVE block */
+		rc = -ENAVAIL;
+		sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
+		while (sde_rm_get_hw(rm, &iter_i)) {
+			struct sde_pingpong_cfg *pp_cfg =
+				(struct sde_pingpong_cfg *)
+				(iter_i.blk->catalog);
+
+			if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
+				continue;
+			if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
+				continue;
+
+			iter_i.blk->rsvp_nxt = rsvp;
+			rc = 0;
+			break;
+		}
+	}
+
+	return rc;
+}
+
+static int _sde_rm_reserve_ctls(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct sde_rm_requirements *reqs)
+{
+	struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
+	struct sde_rm_hw_iter iter;
+	int i = 0;
+
+	memset(&ctls, 0, sizeof(ctls));
+
+	sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
+	while (sde_rm_get_hw(rm, &iter)) {
+		unsigned long caps;
+		bool has_split_display, has_ppsplit;
+
+		if (RESERVED_BY_OTHER(iter.blk, rsvp))
+			continue;
+
+		caps = ((struct sde_ctl_cfg *)iter.blk->catalog)->features;
+		has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & caps;
+		has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & caps;
+
+		SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, caps);
+
+		if (reqs->needs_split_display != has_split_display)
+			continue;
+
+		if (reqs->top_name == SDE_RM_TOPOLOGY_PPSPLIT && !has_ppsplit)
+			continue;
+
+		ctls[i] = iter.blk;
+		SDE_DEBUG("ctl %d match\n", iter.blk->id);
+
+		if (++i == reqs->num_ctl)
+			break;
+	}
+
+	if (i != reqs->num_ctl)
+		return -ENAVAIL;
+
+	for (i = 0; i < ARRAY_SIZE(ctls) && i < reqs->num_ctl; i++) {
+		ctls[i]->rsvp_nxt = rsvp;
+		SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
+	}
+
+	return 0;
+}
+
+static int _sde_rm_reserve_cdm(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		uint32_t id,
+		enum sde_hw_blk_type type)
+{
+	struct sde_rm_hw_iter iter;
+	struct sde_cdm_cfg *cdm;
+
+	sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
+	while (sde_rm_get_hw(rm, &iter)) {
+		bool match = false;
+
+		if (RESERVED_BY_OTHER(iter.blk, rsvp))
+			continue;
+
+		cdm = (struct sde_cdm_cfg *)(iter.blk->catalog);
+
+		if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
+			match = test_bit(id, &cdm->intf_connect);
+		else if (type == SDE_HW_BLK_WB && id != WB_MAX)
+			match = test_bit(id, &cdm->wb_connect);
+
+		SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
+				type, id, cdm->intf_connect, cdm->wb_connect,
+				match);
+
+		if (!match)
+			continue;
+
+		iter.blk->rsvp_nxt = rsvp;
+		SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
+		break;
+	}
+
+	if (!iter.hw) {
+		SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
+		return -ENAVAIL;
+	}
+
+	return 0;
+}
+
+static int _sde_rm_reserve_intf_or_wb(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		uint32_t id,
+		enum sde_hw_blk_type type,
+		bool needs_cdm)
+{
+	struct sde_rm_hw_iter iter;
+	int ret = 0;
+
+	/* Find the block entry in the rm, and note the reservation */
+	sde_rm_init_hw_iter(&iter, 0, type);
+	while (sde_rm_get_hw(rm, &iter)) {
+		if (iter.blk->id != id)
+			continue;
+
+		if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
+			SDE_ERROR("type %d id %d already reserved\n", type, id);
+			return -ENAVAIL;
+		}
+
+		iter.blk->rsvp_nxt = rsvp;
+		SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
+		break;
+	}
+
+	/* Shouldn't happen since wbs / intfs are fixed at probe */
+	if (!iter.hw) {
+		SDE_ERROR("couldn't find type %d id %d\n", type, id);
+		return -EINVAL;
+	}
+
+	/* Expected only one intf or wb will request cdm */
+	if (needs_cdm)
+		ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
+
+	return ret;
+}
+
+static int _sde_rm_reserve_intf_related_hw(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct sde_encoder_hw_resources *hw_res)
+{
+	int i, ret = 0;
+	u32 id;
+
+	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
+		if (hw_res->intfs[i] == INTF_MODE_NONE)
+			continue;
+		id = i + INTF_0;
+		ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
+				SDE_HW_BLK_INTF, hw_res->needs_cdm);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
+		if (hw_res->wbs[i] == INTF_MODE_NONE)
+			continue;
+		id = i + WB_0;
+		ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
+				SDE_HW_BLK_WB, hw_res->needs_cdm);
+		if (ret)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int _sde_rm_make_next_rsvp(
+		struct sde_rm *rm,
+		struct drm_encoder *enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state,
+		struct sde_rm_rsvp *rsvp,
+		struct sde_rm_requirements *reqs)
+{
+	int ret;
+
+	/* Create reservation info, tag reserved blocks with it as we go */
+	rsvp->seq = ++rm->rsvp_next_seq;
+	rsvp->enc_id = enc->base.id;
+	rsvp->topology = reqs->top_name;
+	list_add_tail(&rsvp->list, &rm->rsvps);
+
+	/*
+	 * Assign LMs and blocks whose usage is tied to them: DSPP & Pingpong.
+	 * Do assignment preferring to give away low-resource mixers first:
+	 * - Check mixers without DSPPs
+	 * - Only then allow to grab from mixers with DSPP capability
+	 */
+	ret = _sde_rm_reserve_lms(rm, rsvp, reqs);
+	if (ret && !RM_RQ_DSPP(reqs)) {
+		reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
+		ret = _sde_rm_reserve_lms(rm, rsvp, reqs);
+	}
+
+	if (ret) {
+		SDE_ERROR("unable to find appropriate mixers\n");
+		return ret;
+	}
+
+	/*
+	 * Do assignment preferring to give away low-resource CTLs first:
+	 * - Check mixers without Split Display
+	 * - Only then allow to grab from CTLs with split display capability
+	 */
+	_sde_rm_reserve_ctls(rm, rsvp, reqs);
+	if (ret && !reqs->needs_split_display) {
+		reqs->needs_split_display = true;
+		_sde_rm_reserve_ctls(rm, rsvp, reqs);
+	}
+	if (ret) {
+		SDE_ERROR("unable to find appropriate CTL\n");
+		return ret;
+	}
+
+	/* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
+	ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static int _sde_rm_populate_requirements(
+		struct sde_rm *rm,
+		struct drm_encoder *enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state,
+		struct sde_rm_requirements *reqs)
+{
+	const struct drm_display_mode *mode = &crtc_state->mode;
+
+	/**
+	 * DRM<->HW Topologies
+	 *
+	 * Name: SINGLEPIPE
+	 * Description: 1 LM, 1 PP, 1 INTF
+	 * Condition: 1 DRM Encoder w/ 1 Display Tiles (Default)
+	 *
+	 * Name: DUALPIPE
+	 * Description: 2 LM, 2 PP, 2 INTF
+	 * Condition: 1 DRM Encoder w/ 2 Display Tiles
+	 *
+	 * Name: PPSPLIT
+	 * Description: 1 LM, 1 PP + 1 Slave PP, 2 INTF
+	 * Condition:
+	 *	1 DRM Encoder w/ 2 Display Tiles
+	 *	topology_control & SDE_TOPREQ_PPSPLIT
+	 *
+	 * Name: DUALPIPEMERGE
+	 * Description: 2 LM, 2 PP, 3DMux, 1 INTF
+	 * Condition:
+	 *	1 DRM Encoder w/ 1 Display Tiles
+	 *	display_info.max_width >= layer_mixer.max_width
+	 *
+	 * Name: DUALPIPEMERGE
+	 * Description: 2 LM, 2 PP, 3DMux, 1 INTF
+	 * Condition:
+	 *	1 DRM Encoder w/ 1 Display Tiles
+	 *	display_info.max_width <= layer_mixer.max_width
+	 *	topology_control & SDE_TOPREQ_FORCE_TILING
+	 */
+
+	memset(reqs, 0, sizeof(*reqs));
+
+	reqs->top_ctrl = sde_connector_get_property(conn_state,
+			CONNECTOR_PROP_TOPOLOGY_CONTROL);
+	sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
+
+	/* Base assumption is LMs = h_tiles, conditions below may override */
+	reqs->num_lm = reqs->hw_res.display_num_of_h_tiles;
+
+	if (reqs->num_lm == 2) {
+		if (RM_RQ_PPSPLIT(reqs)) {
+			/* user requests serving dual display with 1 lm */
+			reqs->top_name = SDE_RM_TOPOLOGY_PPSPLIT;
+			reqs->num_lm = 1;
+			reqs->num_ctl = 1;
+			reqs->needs_split_display = true;
+		} else {
+			/* dual display, serve with 2 lms */
+			reqs->top_name = SDE_RM_TOPOLOGY_DUALPIPE;
+			reqs->num_ctl = 2;
+			reqs->needs_split_display = true;
+		}
+
+	} else if (reqs->num_lm == 1) {
+		if (mode->hdisplay > rm->lm_max_width) {
+			/* wide display, must split across 2 lm and merge */
+			reqs->top_name = SDE_RM_TOPOLOGY_DUALPIPEMERGE;
+			reqs->num_lm = 2;
+			reqs->num_ctl = 1;
+			reqs->needs_split_display = false;
+		} else if (RM_RQ_FORCE_TILING(reqs)) {
+			/* thin display, but user requests 2 lm and merge */
+			reqs->top_name = SDE_RM_TOPOLOGY_DUALPIPEMERGE;
+			reqs->num_lm = 2;
+			reqs->num_ctl = 1;
+			reqs->needs_split_display = false;
+		} else {
+			/* thin display, serve with only 1 lm */
+			reqs->top_name = SDE_RM_TOPOLOGY_SINGLEPIPE;
+			reqs->num_ctl = 1;
+			reqs->needs_split_display = false;
+		}
+
+	} else {
+		/* Currently no configurations with # LM > 2 */
+		SDE_ERROR("unsupported # of mixers %d\n", reqs->num_lm);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("top_ctrl 0x%llX num_h_tiles %d\n", reqs->top_ctrl,
+			reqs->hw_res.display_num_of_h_tiles);
+	SDE_DEBUG("display_max_width %d rm->lm_max_width %d\n",
+			mode->hdisplay, rm->lm_max_width);
+	SDE_DEBUG("num_lm %d num_ctl %d topology_name %d\n", reqs->num_lm,
+			reqs->num_ctl, reqs->top_name);
+	SDE_DEBUG("num_lm %d topology_name %d\n", reqs->num_lm,
+			reqs->top_name);
+	SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->num_lm,
+			reqs->top_ctrl, reqs->top_name, reqs->num_ctl);
+
+	return 0;
+}
+
+static struct sde_rm_rsvp *_sde_rm_get_rsvp(
+		struct sde_rm *rm,
+		struct drm_encoder *enc)
+{
+	struct sde_rm_rsvp *i;
+
+	if (!rm || !enc) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	if (list_empty(&rm->rsvps))
+		return NULL;
+
+	list_for_each_entry(i, &rm->rsvps, list)
+		if (i->enc_id == enc->base.id)
+			return i;
+
+	return NULL;
+}
+
+static struct drm_connector *_sde_rm_get_connector(
+		struct drm_encoder *enc)
+{
+	struct drm_connector *conn = NULL;
+	struct list_head *connector_list =
+			&enc->dev->mode_config.connector_list;
+
+	list_for_each_entry(conn, connector_list, head)
+		if (conn->encoder == enc)
+			return conn;
+
+	return NULL;
+}
+
+/**
+ * _sde_rm_release_rsvp - release resources and release a reservation
+ * @rm:	KMS handle
+ * @rsvp:	RSVP pointer to release and release resources for
+ */
+void _sde_rm_release_rsvp(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct drm_connector *conn)
+{
+	struct sde_rm_rsvp *rsvp_c, *rsvp_n;
+	struct sde_rm_hw_blk *blk;
+	enum sde_hw_blk_type type;
+
+	if (!rsvp)
+		return;
+
+	SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
+
+	list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
+		if (rsvp == rsvp_c) {
+			list_del(&rsvp_c->list);
+			break;
+		}
+	}
+
+	for (type = 0; type < SDE_HW_BLK_MAX; type++) {
+		list_for_each_entry(blk, &rm->hw_blks[type], list) {
+			if (blk->rsvp == rsvp) {
+				blk->rsvp = NULL;
+				SDE_DEBUG("rel rsvp %d enc %d %s %d\n",
+						rsvp->seq, rsvp->enc_id,
+						blk->type_name, blk->id);
+			}
+			if (blk->rsvp_nxt == rsvp) {
+				blk->rsvp_nxt = NULL;
+				SDE_DEBUG("rel rsvp_nxt %d enc %d %s %d\n",
+						rsvp->seq, rsvp->enc_id,
+						blk->type_name, blk->id);
+			}
+		}
+	}
+
+	kfree(rsvp);
+
+	(void) msm_property_set_property(
+			sde_connector_get_propinfo(conn),
+			sde_connector_get_property_values(conn->state),
+			CONNECTOR_PROP_TOPOLOGY_NAME,
+			SDE_RM_TOPOLOGY_UNKNOWN);
+}
+
+void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc)
+{
+	struct sde_rm_rsvp *rsvp;
+	struct drm_connector *conn;
+	uint64_t top_ctrl;
+
+	if (!rm || !enc) {
+		SDE_ERROR("invalid params\n");
+		return;
+	}
+
+	rsvp = _sde_rm_get_rsvp(rm, enc);
+	if (!rsvp) {
+		SDE_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
+		return;
+	}
+
+	conn = _sde_rm_get_connector(enc);
+	if (!conn) {
+		SDE_ERROR("failed to get connector for enc %d\n", enc->base.id);
+		return;
+	}
+
+	top_ctrl = sde_connector_get_property(conn->state,
+			CONNECTOR_PROP_TOPOLOGY_CONTROL);
+
+	if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
+		SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
+				rsvp->seq, rsvp->enc_id);
+	} else {
+		SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
+				rsvp->enc_id);
+		_sde_rm_release_rsvp(rm, rsvp, conn);
+	}
+}
+
+static int _sde_rm_commit_rsvp(
+		struct sde_rm *rm,
+		struct sde_rm_rsvp *rsvp,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_rm_hw_blk *blk;
+	enum sde_hw_blk_type type;
+	int ret = 0;
+
+	ret = msm_property_set_property(
+			sde_connector_get_propinfo(conn_state->connector),
+			sde_connector_get_property_values(conn_state),
+			CONNECTOR_PROP_TOPOLOGY_NAME,
+			rsvp->topology);
+	if (ret)
+		_sde_rm_release_rsvp(rm, rsvp, conn_state->connector);
+
+	/* Swap next rsvp to be the active */
+	for (type = 0; type < SDE_HW_BLK_MAX; type++) {
+		list_for_each_entry(blk, &rm->hw_blks[type], list) {
+			if (blk->rsvp_nxt) {
+				blk->rsvp = blk->rsvp_nxt;
+				blk->rsvp_nxt = NULL;
+			}
+		}
+	}
+
+	if (!ret) {
+		SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
+				rsvp->topology);
+		SDE_EVT32(rsvp->enc_id, rsvp->topology);
+	}
+
+	return ret;
+}
+
+int sde_rm_check_property_topctl(uint64_t val)
+{
+	if ((BIT(SDE_RM_TOPCTL_FORCE_TILING) & val) &&
+			(BIT(SDE_RM_TOPCTL_PPSPLIT) & val)) {
+		SDE_ERROR("ppsplit & force_tiling are incompatible\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sde_rm_reserve(
+		struct sde_rm *rm,
+		struct drm_encoder *enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state,
+		bool test_only)
+{
+	struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
+	struct sde_rm_requirements reqs;
+	int ret;
+
+	if (!rm || !enc || !crtc_state || !conn_state) {
+		SDE_ERROR("invalid arguments\n");
+		return -EINVAL;
+	}
+
+	/* Check if this is just a page-flip */
+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
+		return 0;
+
+	SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
+			conn_state->connector->base.id, enc->base.id,
+			crtc_state->crtc->base.id, test_only);
+	SDE_EVT32(enc->base.id, conn_state->connector->base.id);
+
+	_sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
+
+	ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
+			conn_state, &reqs);
+	if (ret) {
+		SDE_ERROR("failed to populate hw requirements\n");
+		return ret;
+	}
+
+	/*
+	 * We only support one active reservation per-hw-block. But to implement
+	 * transactional semantics for test-only, and for allowing failure while
+	 * modifying your existing reservation, over the course of this
+	 * function we can have two reservations:
+	 * Current: Existing reservation
+	 * Next: Proposed reservation. The proposed reservation may fail, or may
+	 *       be discarded if in test-only mode.
+	 * If reservation is successful, and we're not in test-only, then we
+	 * replace the current with the next.
+	 */
+	rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
+	if (!rsvp_nxt)
+		return -ENOMEM;
+
+	rsvp_cur = _sde_rm_get_rsvp(rm, enc);
+
+	/*
+	 * User can request that we clear out any reservation during the
+	 * atomic_check phase by using this CLEAR bit
+	 */
+	if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
+		SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
+				rsvp_cur->seq, rsvp_cur->enc_id);
+		_sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
+		rsvp_cur = NULL;
+		_sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
+	}
+
+	/* Check the proposed reservation, store it in hw's "next" field */
+	ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
+			rsvp_nxt, &reqs);
+
+	_sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
+
+	if (ret) {
+		SDE_ERROR("failed to reserve hw resources: %d\n", ret);
+		_sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
+	} else if (test_only && !RM_RQ_LOCK(&reqs)) {
+		/*
+		 * Normally, if test_only, test the reservation and then undo
+		 * However, if the user requests LOCK, then keep the reservation
+		 * made during the atomic_check phase.
+		 */
+		SDE_DEBUG("test_only: discard test rsvp[s%de%d]\n",
+				rsvp_nxt->seq, rsvp_nxt->enc_id);
+		_sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
+	} else {
+		if (test_only && RM_RQ_LOCK(&reqs))
+			SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
+					rsvp_nxt->seq, rsvp_nxt->enc_id);
+
+		_sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
+
+		ret = _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
+	}
+
+	_sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_rm.h b/drivers/gpu/drm/msm/sde/sde_rm.h
new file mode 100644
index 0000000000000000000000000000000000000000..855b12ce81508ead090599343bf166d6af59a764
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_rm.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SDE_RM_H__
+#define __SDE_RM_H__
+
+#include <linux/list.h>
+
+#include "msm_kms.h"
+#include "sde_hw_top.h"
+
+/**
+ * enum sde_rm_topology_name - HW resource use case in use by connector
+ * @SDE_RM_TOPOLOGY_UNKNOWN: No topology in use currently
+ * @SDE_RM_TOPOLOGY_SINGLEPIPE: 1 LM, 1 PP, 1 INTF/WB
+ * @SDE_RM_TOPOLOGY_DUALPIPE: 2 LM, 2 PP, 2 INTF/WB
+ * @SDE_RM_TOPOLOGY_PPSPLIT: 1 LM, 2 PPs, 2 INTF/WB
+ * @SDE_RM_TOPOLOGY_DUALPIPEMERGE: 2 LM, 2 PP, 3DMux, 1 INTF/WB
+ */
+enum sde_rm_topology_name {
+	SDE_RM_TOPOLOGY_UNKNOWN = 0,
+	SDE_RM_TOPOLOGY_SINGLEPIPE,
+	SDE_RM_TOPOLOGY_DUALPIPE,
+	SDE_RM_TOPOLOGY_PPSPLIT,
+	SDE_RM_TOPOLOGY_DUALPIPEMERGE,
+};
+
+/**
+ * enum sde_rm_topology_control - HW resource use case in use by connector
+ * @SDE_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful
+ *                              test, reserve the resources for this display.
+ *                              Normal behavior would not impact the reservation
+ *                              list during the AtomicTest phase.
+ * @SDE_RM_TOPCTL_RESERVE_CLEAR: If set, in AtomicTest phase, before testing,
+ *                               release any reservation held by this display.
+ *                               Normal behavior would not impact the
+ *                               reservation list during the AtomicTest phase.
+ * @SDE_RM_TOPCTL_DSPP: Require layer mixers with DSPP capabilities
+ * @SDE_RM_TOPCTL_FORCE_TILING: Require kernel to split across multiple layer
+ *                              mixers, despite width fitting within capability
+ *                              of a single layer mixer.
+ * @SDE_RM_TOPCTL_PPSPLIT: Require kernel to use pingpong split pipe
+ *                         configuration instead of dual pipe.
+ */
+enum sde_rm_topology_control {
+	SDE_RM_TOPCTL_RESERVE_LOCK,
+	SDE_RM_TOPCTL_RESERVE_CLEAR,
+	SDE_RM_TOPCTL_DSPP,
+	SDE_RM_TOPCTL_FORCE_TILING,
+	SDE_RM_TOPCTL_PPSPLIT,
+};
+
+/**
+ * struct sde_rm - SDE dynamic hardware resource manager
+ * @dev: device handle for event logging purposes
+ * @rsvps: list of hardware reservations by each crtc->encoder->connector
+ * @hw_blks: array of lists of hardware resources present in the system, one
+ *	list per type of hardware block
+ * @hw_mdp: hardware object for mdp_top
+ * @lm_max_width: cached layer mixer maximum width
+ * @rsvp_next_seq: sequence number for next reservation for debugging purposes
+ */
+struct sde_rm {
+	struct drm_device *dev;
+	struct list_head rsvps;
+	struct list_head hw_blks[SDE_HW_BLK_MAX];
+	struct sde_hw_mdp *hw_mdp;
+	uint32_t lm_max_width;
+	uint32_t rsvp_next_seq;
+};
+
+/**
+ *  struct sde_rm_hw_blk - resource manager internal structure
+ *	forward declaration for single iterator definition without void pointer
+ */
+struct sde_rm_hw_blk;
+
+/**
+ * struct sde_rm_hw_iter - iterator for use with sde_rm
+ * @hw: sde_hw object requested, or NULL on failure
+ * @blk: sde_rm internal block representation. Clients ignore. Used as iterator.
+ * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
+ * @type: Hardware Block Type client wishes to search for.
+ */
+struct sde_rm_hw_iter {
+	void *hw;
+	struct sde_rm_hw_blk *blk;
+	uint32_t enc_id;
+	enum sde_hw_blk_type type;
+};
+
+/**
+ * sde_rm_init - Read hardware catalog and create reservation tracking objects
+ *	for all HW blocks.
+ * @rm: SDE Resource Manager handle
+ * @cat: Pointer to hardware catalog
+ * @mmio: mapped register io address of MDP
+ * @dev: device handle for event logging purposes
+ * @Return: 0 on Success otherwise -ERROR
+ */
+int sde_rm_init(struct sde_rm *rm,
+		struct sde_mdss_cfg *cat,
+		void *mmio,
+		struct drm_device *dev);
+
+/**
+ * sde_rm_destroy - Free all memory allocated by sde_rm_init
+ * @rm: SDE Resource Manager handle
+ * @Return: 0 on Success otherwise -ERROR
+ */
+int sde_rm_destroy(struct sde_rm *rm);
+
+/**
+ * sde_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
+ *	the use connections and user requirements, specified through related
+ *	topology control properties, and reserve hardware blocks to that
+ *	display chain.
+ *	HW blocks can then be accessed through sde_rm_get_* functions.
+ *	HW Reservations should be released via sde_rm_release_hw.
+ * @rm: SDE Resource Manager handle
+ * @drm_enc: DRM Encoder handle
+ * @crtc_state: Proposed Atomic DRM CRTC State handle
+ * @conn_state: Proposed Atomic DRM Connector State handle
+ * @test_only: Atomic-Test phase, discard results (unless property overrides)
+ * @Return: 0 on Success otherwise -ERROR
+ */
+int sde_rm_reserve(struct sde_rm *rm,
+		struct drm_encoder *drm_enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state,
+		bool test_only);
+
+/**
+ * sde_rm_reserve - Given the encoder for the display chain, release any
+ *	HW blocks previously reserved for that use case.
+ * @rm: SDE Resource Manager handle
+ * @enc: DRM Encoder handle
+ * @Return: 0 on Success otherwise -ERROR
+ */
+void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc);
+
+/**
+ * sde_rm_get_mdp - Retrieve HW block for MDP TOP.
+ *	This is never reserved, and is usable by any display.
+ * @rm: SDE Resource Manager handle
+ * @Return: Pointer to hw block or NULL
+ */
+struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm);
+
+/**
+ * sde_rm_init_hw_iter - setup given iterator for new iteration over hw list
+ *	using sde_rm_get_hw
+ * @iter: iter object to initialize
+ * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
+ * @type: Hardware Block Type client wishes to search for.
+ */
+void sde_rm_init_hw_iter(
+		struct sde_rm_hw_iter *iter,
+		uint32_t enc_id,
+		enum sde_hw_blk_type type);
+/**
+ * sde_rm_get_hw - retrieve reserved hw object given encoder and hw type
+ *	Meant to do a single pass through the hardware list to iteratively
+ *	retrieve hardware blocks of a given type for a given encoder.
+ *	Initialize an iterator object.
+ *	Set hw block type of interest. Set encoder id of interest, 0 for any.
+ *	Function returns first hw of type for that encoder.
+ *	Subsequent calls will return the next reserved hw of that type in-order.
+ *	Iterator HW pointer will be null on failure to find hw.
+ * @rm: SDE Resource Manager handle
+ * @iter: iterator object
+ * @Return: true on match found, false on no match found
+ */
+bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *iter);
+
+/**
+ * sde_rm_check_property_topctl - validate property bitmask before it is set
+ * @val: user's proposed topology control bitmask
+ * @Return: 0 on success or error
+ */
+int sde_rm_check_property_topctl(uint64_t val);
+
+/**
+ * sde_rm_check_property_topctl - validate property bitmask before it is set
+ * @val: user's proposed topology control bitmask
+ * @Return: 0 on success or error
+ */
+int sde_rm_check_property_topctl(uint64_t val);
+
+#endif /* __SDE_RM_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_trace.h b/drivers/gpu/drm/msm/sde/sde_trace.h
new file mode 100644
index 0000000000000000000000000000000000000000..2a4e6b59a08c3c58ef73aeb60b830515cacff3f9
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_trace.h
@@ -0,0 +1,195 @@
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#if !defined(_SDE_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _SDE_TRACE_H_
+
+#include <linux/stringify.h>
+#include <linux/types.h>
+#include <linux/tracepoint.h>
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM sde
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE sde_trace
+
+TRACE_EVENT(sde_perf_set_qos_luts,
+	TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
+		u32 lut, bool linear),
+	TP_ARGS(pnum, fmt, rt, fl, lut, linear),
+	TP_STRUCT__entry(
+			__field(u32, pnum)
+			__field(u32, fmt)
+			__field(bool, rt)
+			__field(u32, fl)
+			__field(u32, lut)
+			__field(bool, linear)
+	),
+	TP_fast_assign(
+			__entry->pnum = pnum;
+			__entry->fmt = fmt;
+			__entry->rt = rt;
+			__entry->fl = fl;
+			__entry->lut = lut;
+			__entry->linear = linear;
+	),
+	TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%x lin=%d",
+			__entry->pnum, __entry->fmt,
+			__entry->rt, __entry->fl,
+			__entry->lut, __entry->linear)
+);
+
+TRACE_EVENT(sde_perf_set_danger_luts,
+	TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
+		u32 safe_lut),
+	TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
+	TP_STRUCT__entry(
+			__field(u32, pnum)
+			__field(u32, fmt)
+			__field(u32, mode)
+			__field(u32, danger_lut)
+			__field(u32, safe_lut)
+	),
+	TP_fast_assign(
+			__entry->pnum = pnum;
+			__entry->fmt = fmt;
+			__entry->mode = mode;
+			__entry->danger_lut = danger_lut;
+			__entry->safe_lut = safe_lut;
+	),
+	TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
+			__entry->pnum, __entry->fmt,
+			__entry->mode, __entry->danger_lut,
+			__entry->safe_lut)
+);
+
+TRACE_EVENT(sde_perf_set_ot,
+	TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
+	TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
+	TP_STRUCT__entry(
+			__field(u32, pnum)
+			__field(u32, xin_id)
+			__field(u32, rd_lim)
+			__field(u32, vbif_idx)
+	),
+	TP_fast_assign(
+			__entry->pnum = pnum;
+			__entry->xin_id = xin_id;
+			__entry->rd_lim = rd_lim;
+			__entry->vbif_idx = vbif_idx;
+	),
+	TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
+			__entry->pnum, __entry->xin_id, __entry->rd_lim,
+			__entry->vbif_idx)
+)
+
+TRACE_EVENT(sde_perf_update_bus,
+	TP_PROTO(int client, unsigned long long ab_quota,
+	unsigned long long ib_quota),
+	TP_ARGS(client, ab_quota, ib_quota),
+	TP_STRUCT__entry(
+			__field(int, client)
+			__field(u64, ab_quota)
+			__field(u64, ib_quota)
+	),
+	TP_fast_assign(
+			__entry->client = client;
+			__entry->ab_quota = ab_quota;
+			__entry->ib_quota = ib_quota;
+	),
+	TP_printk("Request client:%d ab=%llu ib=%llu",
+			__entry->client,
+			__entry->ab_quota,
+			__entry->ib_quota)
+)
+
+
+TRACE_EVENT(sde_cmd_release_bw,
+	TP_PROTO(u32 crtc_id),
+	TP_ARGS(crtc_id),
+	TP_STRUCT__entry(
+			__field(u32, crtc_id)
+	),
+	TP_fast_assign(
+			__entry->crtc_id = crtc_id;
+	),
+	TP_printk("crtc:%d", __entry->crtc_id)
+);
+
+TRACE_EVENT(sde_mark_write,
+	TP_PROTO(int pid, const char *name, bool trace_begin),
+	TP_ARGS(pid, name, trace_begin),
+	TP_STRUCT__entry(
+			__field(int, pid)
+			__string(trace_name, name)
+			__field(bool, trace_begin)
+	),
+	TP_fast_assign(
+			__entry->pid = pid;
+			__assign_str(trace_name, name);
+			__entry->trace_begin = trace_begin;
+	),
+	TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
+		__entry->pid, __get_str(trace_name))
+)
+
+TRACE_EVENT(sde_trace_counter,
+	TP_PROTO(int pid, char *name, int value),
+	TP_ARGS(pid, name, value),
+	TP_STRUCT__entry(
+			__field(int, pid)
+			__string(counter_name, name)
+			__field(int, value)
+	),
+	TP_fast_assign(
+			__entry->pid = current->tgid;
+			__assign_str(counter_name, name);
+			__entry->value = value;
+	),
+	TP_printk("%d|%s|%d", __entry->pid,
+			__get_str(counter_name), __entry->value)
+)
+
+TRACE_EVENT(sde_evtlog,
+	TP_PROTO(const char *tag, u32 tag_id, u64 value1, u64 value2),
+	TP_ARGS(tag, tag_id, value1, value2),
+	TP_STRUCT__entry(
+			__field(int, pid)
+			__string(evtlog_tag, tag)
+			__field(u32, tag_id)
+			__field(u64, value1)
+			__field(u64, value2)
+	),
+	TP_fast_assign(
+			__entry->pid = current->tgid;
+			__assign_str(evtlog_tag, tag);
+			__entry->tag_id = tag_id;
+			__entry->value1 = value1;
+			__entry->value2 = value2;
+	),
+	TP_printk("%d|%s:%d|%llu|%llu", __entry->pid, __get_str(evtlog_tag),
+			__entry->tag_id, __entry->value1, __entry->value2)
+)
+
+#define SDE_ATRACE_END(name) trace_sde_mark_write(current->tgid, name, 0)
+#define SDE_ATRACE_BEGIN(name) trace_sde_mark_write(current->tgid, name, 1)
+#define SDE_ATRACE_FUNC() SDE_ATRACE_BEGIN(__func__)
+
+#define SDE_ATRACE_INT(name, value) \
+	trace_sde_trace_counter(current->tgid, name, value)
+
+#endif /* _SDE_TRACE_H_ */
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#include <trace/define_trace.h>
diff --git a/drivers/gpu/drm/msm/sde/sde_vbif.c b/drivers/gpu/drm/msm/sde/sde_vbif.c
new file mode 100644
index 0000000000000000000000000000000000000000..b114840d741c8d1c7f2104b973e277c623e10cfd
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_vbif.c
@@ -0,0 +1,284 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/debugfs.h>
+
+#include "sde_vbif.h"
+#include "sde_hw_vbif.h"
+#include "sde_trace.h"
+
+/**
+ * _sde_vbif_wait_for_xin_halt - wait for the xin to halt
+ * @vbif:	Pointer to hardware vbif driver
+ * @xin_id:	Client interface identifier
+ * @return:	0 if success; error code otherwise
+ */
+static int _sde_vbif_wait_for_xin_halt(struct sde_hw_vbif *vbif, u32 xin_id)
+{
+	ktime_t timeout;
+	bool status;
+	int rc;
+
+	if (!vbif || !vbif->cap || !vbif->ops.get_halt_ctrl) {
+		SDE_ERROR("invalid arguments vbif %d\n", vbif != 0);
+		return -EINVAL;
+	}
+
+	timeout = ktime_add_us(ktime_get(), vbif->cap->xin_halt_timeout);
+	for (;;) {
+		status = vbif->ops.get_halt_ctrl(vbif, xin_id);
+		if (status)
+			break;
+		if (ktime_compare_safe(ktime_get(), timeout) > 0) {
+			status = vbif->ops.get_halt_ctrl(vbif, xin_id);
+			break;
+		}
+		usleep_range(501, 1000);
+	}
+
+	if (!status) {
+		rc = -ETIMEDOUT;
+		SDE_ERROR("VBIF %d client %d not halting. TIMEDOUT.\n",
+				vbif->idx - VBIF_0, xin_id);
+	} else {
+		rc = 0;
+		SDE_DEBUG("VBIF %d client %d is halted\n",
+				vbif->idx - VBIF_0, xin_id);
+	}
+
+	return rc;
+}
+
+/**
+ * _sde_vbif_apply_dynamic_ot_limit - determine OT based on usecase parameters
+ * @vbif:	Pointer to hardware vbif driver
+ * @ot_lim:	Pointer to OT limit to be modified
+ * @params:	Pointer to usecase parameters
+ */
+static void _sde_vbif_apply_dynamic_ot_limit(struct sde_hw_vbif *vbif,
+		u32 *ot_lim, struct sde_vbif_set_ot_params *params)
+{
+	u64 pps;
+	const struct sde_vbif_dynamic_ot_tbl *tbl;
+	u32 i;
+
+	if (!vbif || !(vbif->cap->features & BIT(SDE_VBIF_QOS_OTLIM)))
+		return;
+
+	/* Dynamic OT setting done only for WFD */
+	if (!params->is_wfd)
+		return;
+
+	pps = params->frame_rate;
+	pps *= params->width;
+	pps *= params->height;
+
+	tbl = params->rd ? &vbif->cap->dynamic_ot_rd_tbl :
+			&vbif->cap->dynamic_ot_wr_tbl;
+
+	for (i = 0; i < tbl->count; i++) {
+		if (pps <= tbl->cfg[i].pps) {
+			*ot_lim = tbl->cfg[i].ot_limit;
+			break;
+		}
+	}
+
+	SDE_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
+			vbif->idx - VBIF_0, params->xin_id,
+			params->width, params->height, params->frame_rate,
+			pps, *ot_lim);
+}
+
+/**
+ * _sde_vbif_get_ot_limit - get OT based on usecase & configuration parameters
+ * @vbif:	Pointer to hardware vbif driver
+ * @params:	Pointer to usecase parameters
+ * @return:	OT limit
+ */
+static u32 _sde_vbif_get_ot_limit(struct sde_hw_vbif *vbif,
+	struct sde_vbif_set_ot_params *params)
+{
+	u32 ot_lim = 0;
+	u32 val;
+
+	if (!vbif || !vbif->cap) {
+		SDE_ERROR("invalid arguments vbif %d\n", vbif != 0);
+		return -EINVAL;
+	}
+
+	if (vbif->cap->default_ot_wr_limit && !params->rd)
+		ot_lim = vbif->cap->default_ot_wr_limit;
+	else if (vbif->cap->default_ot_rd_limit && params->rd)
+		ot_lim = vbif->cap->default_ot_rd_limit;
+
+	/*
+	 * If default ot is not set from dt/catalog,
+	 * then do not configure it.
+	 */
+	if (ot_lim == 0)
+		goto exit;
+
+	/* Modify the limits if the target and the use case requires it */
+	_sde_vbif_apply_dynamic_ot_limit(vbif, &ot_lim, params);
+
+	if (vbif && vbif->ops.get_limit_conf) {
+		val = vbif->ops.get_limit_conf(vbif,
+				params->xin_id, params->rd);
+		if (val == ot_lim)
+			ot_lim = 0;
+	}
+
+exit:
+	SDE_DEBUG("vbif:%d xin:%d ot_lim:%d\n",
+			vbif->idx - VBIF_0, params->xin_id, ot_lim);
+	return ot_lim;
+}
+
+/**
+ * sde_vbif_set_ot_limit - set OT based on usecase & configuration parameters
+ * @vbif:	Pointer to hardware vbif driver
+ * @params:	Pointer to usecase parameters
+ *
+ * Note this function would block waiting for bus halt.
+ */
+void sde_vbif_set_ot_limit(struct sde_kms *sde_kms,
+		struct sde_vbif_set_ot_params *params)
+{
+	struct sde_hw_vbif *vbif = NULL;
+	struct sde_hw_mdp *mdp;
+	bool forced_on = false;
+	u32 ot_lim;
+	int ret, i;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid arguments\n");
+		return;
+	}
+	mdp = sde_kms->hw_mdp;
+
+	for (i = 0; i < ARRAY_SIZE(sde_kms->hw_vbif); i++) {
+		if (sde_kms->hw_vbif[i] &&
+				sde_kms->hw_vbif[i]->idx == params->vbif_idx)
+			vbif = sde_kms->hw_vbif[i];
+	}
+
+	if (!vbif || !mdp) {
+		SDE_DEBUG("invalid arguments vbif %d mdp %d\n",
+				vbif != 0, mdp != 0);
+		return;
+	}
+
+	if (!mdp->ops.setup_clk_force_ctrl ||
+			!vbif->ops.set_limit_conf ||
+			!vbif->ops.set_halt_ctrl)
+		return;
+
+	ot_lim = _sde_vbif_get_ot_limit(vbif, params) & 0xFF;
+
+	if (ot_lim == 0)
+		goto exit;
+
+	trace_sde_perf_set_ot(params->num, params->xin_id, ot_lim,
+		params->vbif_idx);
+
+	forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
+
+	vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim);
+
+	vbif->ops.set_halt_ctrl(vbif, params->xin_id, true);
+
+	ret = _sde_vbif_wait_for_xin_halt(vbif, params->xin_id);
+	if (ret)
+		SDE_EVT32(vbif->idx, params->xin_id);
+
+	vbif->ops.set_halt_ctrl(vbif, params->xin_id, false);
+
+	if (forced_on)
+		mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false);
+exit:
+	return;
+}
+
+#ifdef CONFIG_DEBUG_FS
+void sde_debugfs_vbif_destroy(struct sde_kms *sde_kms)
+{
+	debugfs_remove_recursive(sde_kms->debugfs_vbif);
+	sde_kms->debugfs_vbif = NULL;
+}
+
+int sde_debugfs_vbif_init(struct sde_kms *sde_kms, struct dentry *debugfs_root)
+{
+	char vbif_name[32];
+	struct dentry *debugfs_vbif;
+	int i, j;
+
+	sde_kms->debugfs_vbif = debugfs_create_dir("vbif",
+			sde_kms->debugfs_root);
+	if (!sde_kms->debugfs_vbif) {
+		SDE_ERROR("failed to create vbif debugfs\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
+		struct sde_vbif_cfg *vbif = &sde_kms->catalog->vbif[i];
+
+		snprintf(vbif_name, sizeof(vbif_name), "%d", vbif->id);
+
+		debugfs_vbif = debugfs_create_dir(vbif_name,
+				sde_kms->debugfs_vbif);
+
+		debugfs_create_u32("features", 0644, debugfs_vbif,
+			(u32 *)&vbif->features);
+
+		debugfs_create_u32("xin_halt_timeout", S_IRUGO, debugfs_vbif,
+			(u32 *)&vbif->xin_halt_timeout);
+
+		debugfs_create_u32("default_rd_ot_limit", S_IRUGO, debugfs_vbif,
+			(u32 *)&vbif->default_ot_rd_limit);
+
+		debugfs_create_u32("default_wr_ot_limit", S_IRUGO, debugfs_vbif,
+			(u32 *)&vbif->default_ot_wr_limit);
+
+		for (j = 0; j < vbif->dynamic_ot_rd_tbl.count; j++) {
+			struct sde_vbif_dynamic_ot_cfg *cfg =
+					&vbif->dynamic_ot_rd_tbl.cfg[j];
+
+			snprintf(vbif_name, sizeof(vbif_name),
+					"dynamic_ot_rd_%d_pps", j);
+			debugfs_create_u64(vbif_name, S_IRUGO, debugfs_vbif,
+					(u64 *)&cfg->pps);
+			snprintf(vbif_name, sizeof(vbif_name),
+					"dynamic_ot_rd_%d_ot_limit", j);
+			debugfs_create_u32(vbif_name, S_IRUGO, debugfs_vbif,
+					(u32 *)&cfg->ot_limit);
+		}
+
+		for (j = 0; j < vbif->dynamic_ot_wr_tbl.count; j++) {
+			struct sde_vbif_dynamic_ot_cfg *cfg =
+					&vbif->dynamic_ot_wr_tbl.cfg[j];
+
+			snprintf(vbif_name, sizeof(vbif_name),
+					"dynamic_ot_wr_%d_pps", j);
+			debugfs_create_u64(vbif_name, S_IRUGO, debugfs_vbif,
+					(u64 *)&cfg->pps);
+			snprintf(vbif_name, sizeof(vbif_name),
+					"dynamic_ot_wr_%d_ot_limit", j);
+			debugfs_create_u32(vbif_name, S_IRUGO, debugfs_vbif,
+					(u32 *)&cfg->ot_limit);
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_vbif.h b/drivers/gpu/drm/msm/sde/sde_vbif.h
new file mode 100644
index 0000000000000000000000000000000000000000..33f16a867a6007226afa141a2d0f745c08298d63
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_vbif.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_VBIF_H__
+#define __SDE_VBIF_H__
+
+#include "sde_kms.h"
+
+struct sde_vbif_set_ot_params {
+	u32 xin_id;
+	u32 num;
+	u32 width;
+	u32 height;
+	u32 frame_rate;
+	bool rd;
+	bool is_wfd;
+	u32 vbif_idx;
+	u32 clk_ctrl;
+};
+
+/**
+ * sde_vbif_set_ot_limit - set OT limit for vbif client
+ * @sde_kms:	SDE handler
+ * @params:	Pointer to OT configuration parameters
+ */
+void sde_vbif_set_ot_limit(struct sde_kms *sde_kms,
+		struct sde_vbif_set_ot_params *params);
+
+#ifdef CONFIG_DEBUG_FS
+int sde_debugfs_vbif_init(struct sde_kms *sde_kms, struct dentry *debugfs_root);
+void sde_debugfs_vbif_destroy(struct sde_kms *sde_kms);
+#else
+static inline int sde_debugfs_vbif_init(struct sde_kms *sde_kms,
+		struct dentry *debugfs_root)
+{
+	return 0;
+}
+static inline void sde_debugfs_vbif_destroy(struct sde_kms *sde_kms)
+{
+}
+#endif
+#endif /* __SDE_VBIF_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.c b/drivers/gpu/drm/msm/sde/sde_wb.c
new file mode 100644
index 0000000000000000000000000000000000000000..647cb58911539221761e12b44fd8aee8dd6ee45d
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_wb.c
@@ -0,0 +1,745 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include "msm_kms.h"
+#include "sde_kms.h"
+#include "sde_wb.h"
+#include "sde_formats.h"
+
+/* maximum display mode resolution if not available from catalog */
+#define SDE_WB_MODE_MAX_WIDTH	4096
+#define SDE_WB_MODE_MAX_HEIGHT	4096
+
+/* Serialization lock for sde_wb_list */
+static DEFINE_MUTEX(sde_wb_list_lock);
+
+/* List of all writeback devices installed */
+static LIST_HEAD(sde_wb_list);
+
+/**
+ * sde_wb_is_format_valid - check if given format/modifier is supported
+ * @wb_dev:	Pointer to writeback device
+ * @pixel_format:	Fourcc pixel format
+ * @format_modifier:	Format modifier
+ * Returns:		true if valid; false otherwise
+ */
+static int sde_wb_is_format_valid(struct sde_wb_device *wb_dev,
+		u32 pixel_format, u64 format_modifier)
+{
+	const struct sde_format_extended *fmts = wb_dev->wb_cfg->format_list;
+	int i;
+
+	if (!fmts)
+		return false;
+
+	for (i = 0; fmts[i].fourcc_format; i++)
+		if ((fmts[i].modifier == format_modifier) &&
+				(fmts[i].fourcc_format == pixel_format))
+			return true;
+
+	return false;
+}
+
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display)
+{
+	enum drm_connector_status rc = connector_status_unknown;
+
+	SDE_DEBUG("\n");
+
+	if (display)
+		rc = ((struct sde_wb_device *)display)->detect_status;
+
+	return rc;
+}
+
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display)
+{
+	struct sde_wb_device *wb_dev;
+	int num_modes = 0;
+
+	if (!connector || !display)
+		return 0;
+
+	wb_dev = display;
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	if (wb_dev->count_modes && wb_dev->modes) {
+		struct drm_display_mode *mode;
+		int i, ret;
+
+		for (i = 0; i < wb_dev->count_modes; i++) {
+			mode = drm_mode_create(connector->dev);
+			if (!mode) {
+				SDE_ERROR("failed to create mode\n");
+				break;
+			}
+			ret = drm_mode_convert_umode(mode,
+					&wb_dev->modes[i]);
+			if (ret) {
+				SDE_ERROR("failed to convert mode %d\n", ret);
+				break;
+			}
+
+			drm_mode_probed_add(connector, mode);
+			num_modes++;
+		}
+	} else {
+		u32 max_width = (wb_dev->wb_cfg && wb_dev->wb_cfg->sblk) ?
+				wb_dev->wb_cfg->sblk->maxlinewidth :
+				SDE_WB_MODE_MAX_WIDTH;
+
+		num_modes = drm_add_modes_noedid(connector, max_width,
+				SDE_WB_MODE_MAX_HEIGHT);
+	}
+	mutex_unlock(&wb_dev->wb_lock);
+	return num_modes;
+}
+
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state)
+{
+	if (!state || !state->connector ||
+		(state->connector->connector_type !=
+				DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return sde_connector_get_out_fb(state);
+}
+
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi)
+{
+	if (!state || !roi || !state->connector ||
+		(state->connector->connector_type !=
+				DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	roi->x = sde_connector_get_property(state, CONNECTOR_PROP_DST_X);
+	roi->y = sde_connector_get_property(state, CONNECTOR_PROP_DST_Y);
+	roi->w = sde_connector_get_property(state, CONNECTOR_PROP_DST_W);
+	roi->h = sde_connector_get_property(state, CONNECTOR_PROP_DST_H);
+
+	return 0;
+}
+
+/**
+ * sde_wb_connector_set_modes - set writeback modes and connection status
+ * @wb_dev:	Pointer to write back device
+ * @count_modes:	Count of modes
+ * @modes:	Pointer to writeback mode requested
+ * @connected:	Connection status requested
+ * Returns:	0 if success; error code otherwise
+ */
+static
+int sde_wb_connector_set_modes(struct sde_wb_device *wb_dev,
+		u32 count_modes, struct drm_mode_modeinfo __user *modes,
+		bool connected)
+{
+	int ret = 0;
+
+	if (!wb_dev || !wb_dev->connector ||
+			(wb_dev->connector->connector_type !=
+			 DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	if (connected) {
+		SDE_DEBUG("connect\n");
+
+		if (wb_dev->modes) {
+			wb_dev->count_modes = 0;
+
+			kfree(wb_dev->modes);
+			wb_dev->modes = NULL;
+		}
+
+		if (count_modes && modes) {
+			wb_dev->modes = kcalloc(count_modes,
+					sizeof(struct drm_mode_modeinfo),
+					GFP_KERNEL);
+			if (!wb_dev->modes) {
+				SDE_ERROR("invalid params\n");
+				ret = -ENOMEM;
+				goto error;
+			}
+
+			if (copy_from_user(wb_dev->modes, modes,
+					count_modes *
+					sizeof(struct drm_mode_modeinfo))) {
+				SDE_ERROR("failed to copy modes\n");
+				kfree(wb_dev->modes);
+				wb_dev->modes = NULL;
+				ret = -EFAULT;
+				goto error;
+			}
+
+			wb_dev->count_modes = count_modes;
+		}
+
+		wb_dev->detect_status = connector_status_connected;
+	} else {
+		SDE_DEBUG("disconnect\n");
+
+		if (wb_dev->modes) {
+			wb_dev->count_modes = 0;
+
+			kfree(wb_dev->modes);
+			wb_dev->modes = NULL;
+		}
+
+		wb_dev->detect_status = connector_status_disconnected;
+	}
+
+error:
+	return ret;
+}
+
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display)
+{
+	struct sde_wb_device *wb_dev = display;
+	struct drm_framebuffer *out_fb;
+	int rc = 0;
+
+	SDE_DEBUG("\n");
+
+	if (state && (property_index == CONNECTOR_PROP_OUT_FB)) {
+		const struct sde_format *sde_format;
+
+		out_fb = sde_connector_get_out_fb(state);
+		if (!out_fb)
+			goto done;
+
+		sde_format = sde_get_sde_format_ext(out_fb->pixel_format,
+				out_fb->modifier,
+				drm_format_num_planes(out_fb->pixel_format));
+		if (!sde_format) {
+			SDE_ERROR("failed to get sde format\n");
+			rc = -EINVAL;
+			goto done;
+		}
+
+		if (!sde_wb_is_format_valid(wb_dev, out_fb->pixel_format,
+				out_fb->modifier[0])) {
+			SDE_ERROR("unsupported writeback format 0x%x/0x%llx\n",
+					out_fb->pixel_format,
+					out_fb->modifier[0]);
+			rc = -EINVAL;
+			goto done;
+		}
+	}
+
+done:
+	return rc;
+}
+
+int sde_wb_get_info(struct msm_display_info *info, void *display)
+{
+	struct sde_wb_device *wb_dev = display;
+
+	if (!info || !wb_dev) {
+		pr_err("invalid params\n");
+		return -EINVAL;
+	}
+
+	info->intf_type = DRM_MODE_CONNECTOR_VIRTUAL;
+	info->num_of_h_tiles = 1;
+	info->h_tile_instance[0] = sde_wb_get_index(display);
+	info->is_connected = true;
+	info->capabilities = MSM_DISPLAY_CAP_HOT_PLUG | MSM_DISPLAY_CAP_EDID;
+	info->max_width = (wb_dev->wb_cfg && wb_dev->wb_cfg->sblk) ?
+			wb_dev->wb_cfg->sblk->maxlinewidth :
+			SDE_WB_MODE_MAX_WIDTH;
+	info->max_height = SDE_WB_MODE_MAX_HEIGHT;
+	info->compression = MSM_DISPLAY_COMPRESS_NONE;
+	return 0;
+}
+
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display)
+{
+	struct sde_connector *c_conn;
+	struct sde_wb_device *wb_dev = display;
+	const struct sde_format_extended *format_list;
+
+	if (!connector || !info || !display || !wb_dev->wb_cfg) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	c_conn = to_sde_connector(connector);
+	wb_dev->connector = connector;
+	wb_dev->detect_status = connector_status_connected;
+	format_list = wb_dev->wb_cfg->format_list;
+
+	/*
+	 * Add extra connector properties
+	 */
+	msm_property_install_range(&c_conn->property_info, "FB_ID",
+			0x0, 0, ~0, ~0, CONNECTOR_PROP_OUT_FB);
+	msm_property_install_range(&c_conn->property_info, "DST_X",
+			0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_X);
+	msm_property_install_range(&c_conn->property_info, "DST_Y",
+			0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_Y);
+	msm_property_install_range(&c_conn->property_info, "DST_W",
+			0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_W);
+	msm_property_install_range(&c_conn->property_info, "DST_H",
+			0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_H);
+
+	/*
+	 * Populate info buffer
+	 */
+	if (format_list) {
+		sde_kms_info_start(info, "pixel_formats");
+		while (format_list->fourcc_format) {
+			sde_kms_info_append_format(info,
+					format_list->fourcc_format,
+					format_list->modifier);
+			++format_list;
+		}
+		sde_kms_info_stop(info);
+	}
+
+	sde_kms_info_add_keyint(info,
+			"wb_intf_index",
+			wb_dev->wb_idx - WB_0);
+
+	sde_kms_info_add_keyint(info,
+			"maxlinewidth",
+			wb_dev->wb_cfg->sblk->maxlinewidth);
+
+	sde_kms_info_start(info, "features");
+	if (wb_dev->wb_cfg && (wb_dev->wb_cfg->features & SDE_WB_UBWC_1_0))
+		sde_kms_info_append(info, "wb_ubwc");
+	sde_kms_info_stop(info);
+
+	return 0;
+}
+
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev)
+{
+	struct drm_framebuffer *fb;
+
+	if (!wb_dev || !wb_dev->connector) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	fb = sde_wb_connector_state_get_output_fb(wb_dev->connector->state);
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return fb;
+}
+
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi)
+{
+	int rc;
+
+	if (!wb_dev || !wb_dev->connector || !roi) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	rc = sde_wb_connector_state_get_output_roi(
+			wb_dev->connector->state, roi);
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return rc;
+}
+
+u32 sde_wb_get_num_of_displays(void)
+{
+	u32 count = 0;
+	struct sde_wb_device *wb_dev;
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(wb_dev, &sde_wb_list, wb_list) {
+		count++;
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	return count;
+}
+
+int wb_display_get_displays(void **display_array, u32 max_display_count)
+{
+	struct sde_wb_device *curr;
+	int i = 0;
+
+	SDE_DEBUG("\n");
+
+	if (!display_array || !max_display_count) {
+		if (!display_array)
+			SDE_ERROR("invalid param\n");
+		return 0;
+	}
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(curr, &sde_wb_list, wb_list) {
+		if (i >= max_display_count)
+			break;
+		display_array[i++] = curr;
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	return i;
+}
+
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv)
+{
+	struct sde_drm_wb_cfg *config = data;
+	struct msm_drm_private *priv;
+	struct sde_wb_device *wb_dev = NULL;
+	struct sde_wb_device *curr;
+	struct drm_connector *connector;
+	uint32_t flags;
+	uint32_t connector_id;
+	uint32_t count_modes;
+	uint64_t modes;
+	int rc;
+
+	if (!drm_dev || !data) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	flags = config->flags;
+	connector_id = config->connector_id;
+	count_modes = config->count_modes;
+	modes = config->modes;
+
+	priv = drm_dev->dev_private;
+
+	connector = drm_connector_find(drm_dev, connector_id);
+	if (!connector) {
+		SDE_ERROR("failed to find connector\n");
+		rc = -ENOENT;
+		goto fail;
+	}
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(curr, &sde_wb_list, wb_list) {
+		if (curr->connector == connector) {
+			wb_dev = curr;
+			break;
+		}
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	if (!wb_dev) {
+		SDE_ERROR("failed to find wb device\n");
+		rc = -ENOENT;
+		goto fail;
+	}
+
+	mutex_lock(&wb_dev->wb_lock);
+
+	rc = sde_wb_connector_set_modes(wb_dev, count_modes,
+		(struct drm_mode_modeinfo __user *) (uintptr_t) modes,
+		(flags & SDE_DRM_WB_CFG_FLAGS_CONNECTED) ? true : false);
+
+	mutex_unlock(&wb_dev->wb_lock);
+	drm_helper_hpd_irq_event(drm_dev);
+fail:
+	return rc;
+}
+
+/**
+ * _sde_wb_dev_init - perform device initialization
+ * @wb_dev:	Pointer to writeback device
+ */
+static int _sde_wb_dev_init(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+/**
+ * _sde_wb_dev_deinit - perform device de-initialization
+ * @wb_dev:	Pointer to writeback device
+ */
+static int _sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+/**
+ * sde_wb_bind - bind writeback device with controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ * Returns:     Zero on success
+ */
+static int sde_wb_bind(struct device *dev, struct device *master, void *data)
+{
+	struct sde_wb_device *wb_dev;
+
+	if (!dev || !master) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	wb_dev = platform_get_drvdata(to_platform_device(dev));
+	if (!wb_dev) {
+		SDE_ERROR("invalid wb device\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	wb_dev->drm_dev = dev_get_drvdata(master);
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return 0;
+}
+
+/**
+ * sde_wb_unbind - unbind writeback from controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ */
+static void sde_wb_unbind(struct device *dev,
+		struct device *master, void *data)
+{
+	struct sde_wb_device *wb_dev;
+
+	if (!dev) {
+		SDE_ERROR("invalid params\n");
+		return;
+	}
+
+	wb_dev = platform_get_drvdata(to_platform_device(dev));
+	if (!wb_dev) {
+		SDE_ERROR("invalid wb device\n");
+		return;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	wb_dev->drm_dev = NULL;
+	mutex_unlock(&wb_dev->wb_lock);
+}
+
+static const struct component_ops sde_wb_comp_ops = {
+	.bind = sde_wb_bind,
+	.unbind = sde_wb_unbind,
+};
+
+/**
+ * sde_wb_drm_init - perform DRM initialization
+ * @wb_dev:	Pointer to writeback device
+ * @encoder:	Pointer to associated encoder
+ */
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
+{
+	int rc = 0;
+
+	if (!wb_dev || !wb_dev->drm_dev || !encoder) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+
+	if (wb_dev->drm_dev->dev_private) {
+		struct msm_drm_private *priv = wb_dev->drm_dev->dev_private;
+		struct sde_kms *sde_kms = to_sde_kms(priv->kms);
+
+		if (wb_dev->index < sde_kms->catalog->wb_count) {
+			wb_dev->wb_idx = sde_kms->catalog->wb[wb_dev->index].id;
+			wb_dev->wb_cfg = &sde_kms->catalog->wb[wb_dev->index];
+		}
+	}
+
+	wb_dev->drm_dev = encoder->dev;
+	wb_dev->encoder = encoder;
+	mutex_unlock(&wb_dev->wb_lock);
+	return rc;
+}
+
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+/**
+ * sde_wb_probe - load writeback module
+ * @pdev:	Pointer to platform device
+ */
+static int sde_wb_probe(struct platform_device *pdev)
+{
+	struct sde_wb_device *wb_dev;
+	int ret;
+
+	wb_dev = devm_kzalloc(&pdev->dev, sizeof(*wb_dev), GFP_KERNEL);
+	if (!wb_dev)
+		return -ENOMEM;
+
+	SDE_DEBUG("\n");
+
+	ret = of_property_read_u32(pdev->dev.of_node, "cell-index",
+			&wb_dev->index);
+	if (ret) {
+		SDE_DEBUG("cell index not set, default to 0\n");
+		wb_dev->index = 0;
+	}
+
+	wb_dev->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!wb_dev->name) {
+		SDE_DEBUG("label not set, default to unknown\n");
+		wb_dev->name = "unknown";
+	}
+
+	wb_dev->wb_idx = SDE_NONE;
+
+	mutex_init(&wb_dev->wb_lock);
+	platform_set_drvdata(pdev, wb_dev);
+
+	mutex_lock(&sde_wb_list_lock);
+	list_add(&wb_dev->wb_list, &sde_wb_list);
+	mutex_unlock(&sde_wb_list_lock);
+
+	if (!_sde_wb_dev_init(wb_dev)) {
+		ret = component_add(&pdev->dev, &sde_wb_comp_ops);
+		if (ret)
+			pr_err("component add failed\n");
+	}
+
+	return ret;
+}
+
+/**
+ * sde_wb_remove - unload writeback module
+ * @pdev:	Pointer to platform device
+ */
+static int sde_wb_remove(struct platform_device *pdev)
+{
+	struct sde_wb_device *wb_dev;
+	struct sde_wb_device *curr, *next;
+
+	wb_dev = platform_get_drvdata(pdev);
+	if (!wb_dev)
+		return 0;
+
+	SDE_DEBUG("\n");
+
+	(void)_sde_wb_dev_deinit(wb_dev);
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry_safe(curr, next, &sde_wb_list, wb_list) {
+		if (curr == wb_dev) {
+			list_del(&wb_dev->wb_list);
+			break;
+		}
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	kfree(wb_dev->modes);
+	mutex_destroy(&wb_dev->wb_lock);
+
+	platform_set_drvdata(pdev, NULL);
+	devm_kfree(&pdev->dev, wb_dev);
+
+	return 0;
+}
+
+static const struct of_device_id dt_match[] = {
+	{ .compatible = "qcom,wb-display"},
+	{}
+};
+
+static struct platform_driver sde_wb_driver = {
+	.probe = sde_wb_probe,
+	.remove = sde_wb_remove,
+	.driver = {
+		.name = "sde_wb",
+		.of_match_table = dt_match,
+	},
+};
+
+static int __init sde_wb_register(void)
+{
+	return platform_driver_register(&sde_wb_driver);
+}
+
+static void __exit sde_wb_unregister(void)
+{
+	platform_driver_unregister(&sde_wb_driver);
+}
+
+module_init(sde_wb_register);
+module_exit(sde_wb_unregister);
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.h b/drivers/gpu/drm/msm/sde/sde_wb.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e335956db550aa44ecf6b8036ebf2ff576b722d
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_wb.h
@@ -0,0 +1,321 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_WB_H__
+#define __SDE_WB_H__
+
+#include <linux/platform_device.h>
+
+#include "msm_kms.h"
+#include "sde_kms.h"
+#include "sde_connector.h"
+
+/**
+ * struct sde_wb_device - Writeback device context
+ * @drm_dev:		Pointer to controlling DRM device
+ * @index:		Index of hardware instance from device tree
+ * @wb_idx:		Writeback identifier of enum sde_wb
+ * @wb_cfg:		Writeback configuration catalog
+ * @name:		Name of writeback device from device tree
+ * @display_type:	Display type from device tree
+ * @wb_list		List of all writeback devices
+ * @wb_lock		Serialization lock for writeback context structure
+ * @connector:		Connector associated with writeback device
+ * @encoder:		Encoder associated with writeback device
+ * @count_modes:	Length of writeback connector modes array
+ * @modes:		Writeback connector modes array
+ */
+struct sde_wb_device {
+	struct drm_device *drm_dev;
+
+	u32 index;
+	u32 wb_idx;
+	struct sde_wb_cfg *wb_cfg;
+	const char *name;
+
+	struct list_head wb_list;
+	struct mutex wb_lock;
+
+	struct drm_connector *connector;
+	struct drm_encoder *encoder;
+
+	enum drm_connector_status detect_status;
+	u32 count_modes;
+	struct drm_mode_modeinfo *modes;
+};
+
+/**
+ * sde_wb_get_index - get device index of the given writeback device
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	Index of hardware instance
+ */
+static inline
+int sde_wb_get_index(struct sde_wb_device *wb_dev)
+{
+	return wb_dev ? wb_dev->index : -1;
+}
+
+#ifdef CONFIG_DRM_SDE_WB
+/**
+ * sde_wb_get_output_fb - get framebuffer in current atomic state
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	Pointer to framebuffer
+ */
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_get_output_roi - get region-of-interest in current atomic state
+ * @wb_dev:	Pointer to writeback device
+ * @roi:	Pointer to region of interest
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi);
+
+/**
+ * sde_wb_get_num_of_displays - get total number of writeback devices
+ * Returns:	Number of writeback devices
+ */
+u32 sde_wb_get_num_of_displays(void);
+
+/**
+ * wb_display_get_displays - returns pointers for supported display devices
+ * @display_array: Pointer to display array to be filled
+ * @max_display_count: Size of display_array
+ * @Returns: Number of display entries filled
+ */
+int wb_display_get_displays(void **display_array, u32 max_display_count);
+
+void sde_wb_set_active_state(struct sde_wb_device *wb_dev, bool is_active);
+bool sde_wb_is_active(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_drm_init - perform DRM initialization
+ * @wb_dev:	Pointer to writeback device
+ * @encoder:	Pointer to associated encoder
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder);
+
+/**
+ * sde_wb_drm_deinit - perform DRM de-initialization
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_config - setup connection status and available drm modes of the
+ *			given writeback connector
+ * @drm_dev:	Pointer to DRM device
+ * @data:	Pointer to writeback configuration
+ * @file_priv:	Pointer file private data
+ * Returns:	0 if success; error code otherwise
+ *
+ * This function will initiate hot-plug detection event.
+ */
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv);
+
+/**
+ * sde_wb_connector_post_init - perform writeback specific initialization
+ * @connector: Pointer to drm connector structure
+ * @info: Pointer to connector info
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display);
+
+/**
+ * sde_wb_connector_detect - perform writeback connection status detection
+ * @connector:	Pointer to connector
+ * @force:	Indicate force detection
+ * @display:	Pointer to writeback device
+ * Returns:	connector status
+ */
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display);
+
+/**
+ * sde_wb_connector_get_modes - get display modes of connector
+ * @connector:	Pointer to connector
+ * @display:	Pointer to writeback device
+ * Returns:	Number of modes
+ *
+ * If display modes are not specified in writeback configuration IOCTL, this
+ * function will install default EDID modes up to maximum resolution support.
+ */
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display);
+
+/**
+ * sde_wb_connector_set_property - set atomic connector property
+ * @connector: Pointer to drm connector structure
+ * @state: Pointer to drm connector state structure
+ * @property_index: DRM property index
+ * @value: Incoming property value
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display);
+
+/**
+ * sde_wb_get_info - retrieve writeback 'display' information
+ * @info: Pointer to display info structure
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_get_info(struct msm_display_info *info, void *display);
+
+/**
+ * sde_wb_connector_get_wb - retrieve writeback device of the given connector
+ * @connector: Pointer to drm connector
+ * Returns: Pointer to writeback device on success; NULL otherwise
+ */
+static inline
+struct sde_wb_device *sde_wb_connector_get_wb(struct drm_connector *connector)
+{
+	if (!connector ||
+		(connector->connector_type != DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	return sde_connector_get_display(connector);
+}
+
+/**
+ * sde_wb_connector_state_get_output_fb - get framebuffer of given state
+ * @state:	Pointer to connector state
+ * Returns:	Pointer to framebuffer
+ */
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state);
+
+/**
+ * sde_wb_connector_state_get_output_roi - get roi from given atomic state
+ * @state:	Pointer to atomic state
+ * @roi:	Pointer to region of interest
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi);
+
+#else
+static inline
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev)
+{
+	return NULL;
+}
+static inline
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi)
+{
+	return 0;
+}
+static inline
+u32 sde_wb_get_num_of_displays(void)
+{
+	return 0;
+}
+static inline
+int wb_display_get_displays(void **display_array, u32 max_display_count)
+{
+	return 0;
+}
+static inline
+void sde_wb_set_active_state(struct sde_wb_device *wb_dev, bool is_active)
+{
+}
+static inline
+bool sde_wb_is_active(struct sde_wb_device *wb_dev)
+{
+	return false;
+}
+static inline
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
+{
+	return 0;
+}
+static inline
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev)
+{
+	return 0;
+}
+static inline
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv)
+{
+	return 0;
+}
+static inline
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display)
+{
+	return 0;
+}
+static inline
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display)
+{
+	return connector_status_disconnected;
+}
+static inline
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display)
+{
+	return -EINVAL;
+}
+static inline
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display)
+{
+	return 0;
+}
+static inline
+int sde_wb_get_info(struct msm_display_info *info, void *display)
+{
+	return 0;
+}
+static inline
+struct sde_wb_device *sde_wb_connector_get_wb(struct drm_connector *connector)
+{
+	return NULL;
+}
+
+static inline
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state)
+{
+	return NULL;
+}
+
+static inline
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi)
+{
+	return 0;
+}
+
+#endif
+#endif /* __SDE_WB_H__ */
+
diff --git a/drivers/gpu/drm/msm/sde_dbg.h b/drivers/gpu/drm/msm/sde_dbg.h
new file mode 100644
index 0000000000000000000000000000000000000000..271c41f05ce5058d72db5ba6d00ae247ab6f43ef
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_dbg.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SDE_DBG_H_
+#define SDE_DBG_H_
+
+#include <stdarg.h>
+#include <linux/debugfs.h>
+#include <linux/list.h>
+
+#define SDE_EVTLOG_DATA_LIMITER	(-1)
+#define SDE_EVTLOG_FUNC_ENTRY	0x1111
+#define SDE_EVTLOG_FUNC_EXIT	0x2222
+
+#define SDE_DBG_DUMP_DATA_LIMITER (NULL)
+
+enum sde_dbg_evtlog_flag {
+	SDE_EVTLOG_DEFAULT = BIT(0),
+	SDE_EVTLOG_IRQ = BIT(1),
+	SDE_EVTLOG_ALL = BIT(7)
+};
+
+/**
+ * SDE_EVT32 - Write an list of 32bit values as an event into the event log
+ * ... - variable arguments
+ */
+#define SDE_EVT32(...) sde_evtlog(__func__, __LINE__, SDE_EVTLOG_DEFAULT, \
+		##__VA_ARGS__, SDE_EVTLOG_DATA_LIMITER)
+#define SDE_EVT32_IRQ(...) sde_evtlog(__func__, __LINE__, SDE_EVTLOG_IRQ, \
+		##__VA_ARGS__, SDE_EVTLOG_DATA_LIMITER)
+
+#define SDE_DBG_DUMP(...)	\
+	sde_dbg_dump(false, __func__, ##__VA_ARGS__, \
+		SDE_DBG_DUMP_DATA_LIMITER)
+
+#define SDE_DBG_DUMP_WQ(...)	\
+	sde_dbg_dump(true, __func__, ##__VA_ARGS__, \
+		SDE_DBG_DUMP_DATA_LIMITER)
+
+#if defined(CONFIG_DEBUG_FS)
+
+int sde_evtlog_init(struct dentry *debugfs_root);
+void sde_evtlog_destroy(void);
+void sde_evtlog(const char *name, int line, int flag, ...);
+void sde_dbg_dump(bool queue, const char *name, ...);
+#else
+static inline int sde_evtlog_init(struct dentry *debugfs_root) { return 0; }
+static inline void sde_evtlog(const char *name, int line,  flag, ...) {}
+static inline void sde_evtlog_destroy(void) { }
+static inline void sde_dbg_dump(bool queue, const char *name, ...) {}
+#endif
+
+#endif /* SDE_DBG_H_ */
diff --git a/drivers/gpu/drm/msm/sde_dbg_evtlog.c b/drivers/gpu/drm/msm/sde_dbg_evtlog.c
new file mode 100644
index 0000000000000000000000000000000000000000..72832776659d479faed3d85a3c047372d0f5e9c7
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_dbg_evtlog.c
@@ -0,0 +1,326 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"sde_evtlog:[%s] " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/ktime.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/dma-buf.h>
+
+#include "sde_dbg.h"
+#include "sde_trace.h"
+
+#ifdef CONFIG_DRM_SDE_EVTLOG_DEBUG
+#define SDE_EVTLOG_DEFAULT_ENABLE 1
+#else
+#define SDE_EVTLOG_DEFAULT_ENABLE 0
+#endif
+
+#define SDE_DBG_DEFAULT_PANIC		1
+
+/*
+ * evtlog will print this number of entries when it is called through
+ * sysfs node or panic. This prevents kernel log from evtlog message
+ * flood.
+ */
+#define SDE_EVTLOG_PRINT_ENTRY	256
+
+/*
+ * evtlog keeps this number of entries in memory for debug purpose. This
+ * number must be greater than print entry to prevent out of bound evtlog
+ * entry array access.
+ */
+#define SDE_EVTLOG_ENTRY	(SDE_EVTLOG_PRINT_ENTRY * 4)
+#define SDE_EVTLOG_MAX_DATA 15
+#define SDE_EVTLOG_BUF_MAX 512
+#define SDE_EVTLOG_BUF_ALIGN 32
+
+DEFINE_SPINLOCK(sde_evtloglock);
+
+struct tlog {
+	u32 counter;
+	s64 time;
+	const char *name;
+	int line;
+	u32 data[SDE_EVTLOG_MAX_DATA];
+	u32 data_cnt;
+	int pid;
+};
+
+static struct sde_dbg_evtlog {
+	struct tlog logs[SDE_EVTLOG_ENTRY];
+	u32 first;
+	u32 last;
+	u32 curr;
+	struct dentry *evtlog;
+	u32 evtlog_enable;
+	u32 panic_on_err;
+	struct work_struct evtlog_dump_work;
+	bool work_panic;
+} sde_dbg_evtlog;
+
+static inline bool sde_evtlog_is_enabled(u32 flag)
+{
+	return (flag & sde_dbg_evtlog.evtlog_enable) ||
+		(flag == SDE_EVTLOG_ALL && sde_dbg_evtlog.evtlog_enable);
+}
+
+void sde_evtlog(const char *name, int line, int flag, ...)
+{
+	unsigned long flags;
+	int i, val = 0;
+	va_list args;
+	struct tlog *log;
+
+	if (!sde_evtlog_is_enabled(flag))
+		return;
+
+	spin_lock_irqsave(&sde_evtloglock, flags);
+	log = &sde_dbg_evtlog.logs[sde_dbg_evtlog.curr];
+	log->time = ktime_to_us(ktime_get());
+	log->name = name;
+	log->line = line;
+	log->data_cnt = 0;
+	log->pid = current->pid;
+
+	va_start(args, flag);
+	for (i = 0; i < SDE_EVTLOG_MAX_DATA; i++) {
+
+		val = va_arg(args, int);
+		if (val == SDE_EVTLOG_DATA_LIMITER)
+			break;
+
+		log->data[i] = val;
+	}
+	va_end(args);
+	log->data_cnt = i;
+	sde_dbg_evtlog.curr = (sde_dbg_evtlog.curr + 1) % SDE_EVTLOG_ENTRY;
+	sde_dbg_evtlog.last++;
+
+	trace_sde_evtlog(name, line, i > 0 ? log->data[0] : 0,
+			i > 1 ? log->data[1] : 0);
+
+	spin_unlock_irqrestore(&sde_evtloglock, flags);
+}
+
+/* always dump the last entries which are not dumped yet */
+static bool _sde_evtlog_dump_calc_range(void)
+{
+	static u32 next;
+	bool need_dump = true;
+	unsigned long flags;
+	struct sde_dbg_evtlog *evtlog = &sde_dbg_evtlog;
+
+	spin_lock_irqsave(&sde_evtloglock, flags);
+
+	evtlog->first = next;
+
+	if (evtlog->last == evtlog->first) {
+		need_dump = false;
+		goto dump_exit;
+	}
+
+	if (evtlog->last < evtlog->first) {
+		evtlog->first %= SDE_EVTLOG_ENTRY;
+		if (evtlog->last < evtlog->first)
+			evtlog->last += SDE_EVTLOG_ENTRY;
+	}
+
+	if ((evtlog->last - evtlog->first) > SDE_EVTLOG_PRINT_ENTRY) {
+		pr_warn("evtlog buffer overflow before dump: %d\n",
+			evtlog->last - evtlog->first);
+		evtlog->first = evtlog->last - SDE_EVTLOG_PRINT_ENTRY;
+	}
+	next = evtlog->first + 1;
+
+dump_exit:
+	spin_unlock_irqrestore(&sde_evtloglock, flags);
+
+	return need_dump;
+}
+
+static ssize_t sde_evtlog_dump_entry(char *evtlog_buf, ssize_t evtlog_buf_size)
+{
+	int i;
+	ssize_t off = 0;
+	struct tlog *log, *prev_log;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sde_evtloglock, flags);
+
+	log = &sde_dbg_evtlog.logs[sde_dbg_evtlog.first %
+		SDE_EVTLOG_ENTRY];
+
+	prev_log = &sde_dbg_evtlog.logs[(sde_dbg_evtlog.first - 1) %
+		SDE_EVTLOG_ENTRY];
+
+	off = snprintf((evtlog_buf + off), (evtlog_buf_size - off), "%s:%-4d",
+		log->name, log->line);
+
+	if (off < SDE_EVTLOG_BUF_ALIGN) {
+		memset((evtlog_buf + off), 0x20, (SDE_EVTLOG_BUF_ALIGN - off));
+		off = SDE_EVTLOG_BUF_ALIGN;
+	}
+
+	off += snprintf((evtlog_buf + off), (evtlog_buf_size - off),
+		"=>[%-8d:%-11llu:%9llu][%-4d]:", sde_dbg_evtlog.first,
+		log->time, (log->time - prev_log->time), log->pid);
+
+	for (i = 0; i < log->data_cnt; i++)
+		off += snprintf((evtlog_buf + off), (evtlog_buf_size - off),
+			"%x ", log->data[i]);
+
+	off += snprintf((evtlog_buf + off), (evtlog_buf_size - off), "\n");
+
+	spin_unlock_irqrestore(&sde_evtloglock, flags);
+
+	return off;
+}
+
+static void _sde_evtlog_dump_all(void)
+{
+	char evtlog_buf[SDE_EVTLOG_BUF_MAX];
+
+	while (_sde_evtlog_dump_calc_range()) {
+		sde_evtlog_dump_entry(evtlog_buf, SDE_EVTLOG_BUF_MAX);
+		pr_info("%s", evtlog_buf);
+	}
+}
+
+static void _sde_dump_array(bool dead, const char *name)
+{
+	_sde_evtlog_dump_all();
+
+	if (dead && sde_dbg_evtlog.panic_on_err)
+		panic(name);
+}
+
+static void _sde_dump_work(struct work_struct *work)
+{
+	_sde_dump_array(sde_dbg_evtlog.work_panic, "evtlog_workitem");
+}
+
+void sde_dbg_dump(bool queue, const char *name, ...)
+{
+	int i;
+	bool dead = false;
+	va_list args;
+	char *blk_name = NULL;
+
+	if (!sde_evtlog_is_enabled(SDE_EVTLOG_DEFAULT))
+		return;
+
+	if (queue && work_pending(&sde_dbg_evtlog.evtlog_dump_work))
+		return;
+
+	va_start(args, name);
+	for (i = 0; i < SDE_EVTLOG_MAX_DATA; i++) {
+		blk_name = va_arg(args, char*);
+		if (IS_ERR_OR_NULL(blk_name))
+			break;
+
+		if (!strcmp(blk_name, "panic"))
+			dead = true;
+	}
+	va_end(args);
+
+	if (queue) {
+		/* schedule work to dump later */
+		sde_dbg_evtlog.work_panic = dead;
+		schedule_work(&sde_dbg_evtlog.evtlog_dump_work);
+	} else {
+		_sde_dump_array(dead, name);
+	}
+}
+
+static int sde_evtlog_dump_open(struct inode *inode, struct file *file)
+{
+	/* non-seekable */
+	file->f_mode &= ~(FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE);
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t sde_evtlog_dump_read(struct file *file, char __user *buff,
+		size_t count, loff_t *ppos)
+{
+	ssize_t len = 0;
+	char evtlog_buf[SDE_EVTLOG_BUF_MAX];
+
+	if (_sde_evtlog_dump_calc_range()) {
+		len = sde_evtlog_dump_entry(evtlog_buf, SDE_EVTLOG_BUF_MAX);
+		if (copy_to_user(buff, evtlog_buf, len))
+			return -EFAULT;
+		*ppos += len;
+	}
+
+	return len;
+}
+
+static ssize_t sde_evtlog_dump_write(struct file *file,
+	const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	_sde_evtlog_dump_all();
+
+	if (sde_dbg_evtlog.panic_on_err)
+		panic("sde");
+
+	return count;
+}
+
+static const struct file_operations sde_evtlog_fops = {
+	.open = sde_evtlog_dump_open,
+	.read = sde_evtlog_dump_read,
+	.write = sde_evtlog_dump_write,
+};
+
+int sde_evtlog_init(struct dentry *debugfs_root)
+{
+	int i;
+
+	sde_dbg_evtlog.evtlog = debugfs_create_dir("evt_dbg", debugfs_root);
+	if (IS_ERR_OR_NULL(sde_dbg_evtlog.evtlog)) {
+		pr_err("debugfs_create_dir fail, error %ld\n",
+		       PTR_ERR(sde_dbg_evtlog.evtlog));
+		sde_dbg_evtlog.evtlog = NULL;
+		return -ENODEV;
+	}
+
+	INIT_WORK(&sde_dbg_evtlog.evtlog_dump_work, _sde_dump_work);
+	sde_dbg_evtlog.work_panic = false;
+
+	for (i = 0; i < SDE_EVTLOG_ENTRY; i++)
+		sde_dbg_evtlog.logs[i].counter = i;
+
+	debugfs_create_file("dump", 0644, sde_dbg_evtlog.evtlog, NULL,
+						&sde_evtlog_fops);
+	debugfs_create_u32("enable", 0644, sde_dbg_evtlog.evtlog,
+			    &sde_dbg_evtlog.evtlog_enable);
+	debugfs_create_u32("panic", 0644, sde_dbg_evtlog.evtlog,
+			    &sde_dbg_evtlog.panic_on_err);
+
+	sde_dbg_evtlog.evtlog_enable = SDE_EVTLOG_DEFAULT_ENABLE;
+	sde_dbg_evtlog.panic_on_err = SDE_DBG_DEFAULT_PANIC;
+
+	pr_info("evtlog_status: enable:%d, panic:%d\n",
+		sde_dbg_evtlog.evtlog_enable, sde_dbg_evtlog.panic_on_err);
+
+	return 0;
+}
+
+void sde_evtlog_destroy(void)
+{
+	debugfs_remove(sde_dbg_evtlog.evtlog);
+}
diff --git a/drivers/gpu/drm/msm/sde_power_handle.c b/drivers/gpu/drm/msm/sde_power_handle.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c82a261e3fb49da508d71322273262f9aed8615
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_power_handle.c
@@ -0,0 +1,924 @@
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d]: " fmt, __func__, __LINE__
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/string.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+
+#include <linux/msm-bus.h>
+#include <linux/msm-bus-board.h>
+#include <linux/mdss_io_util.h>
+
+#include "sde_power_handle.h"
+#include "sde_trace.h"
+
+struct sde_power_client *sde_power_client_create(
+	struct sde_power_handle *phandle, char *client_name)
+{
+	struct sde_power_client *client;
+	static u32 id;
+
+	if (!client_name || !phandle) {
+		pr_err("client name is null or invalid power data\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	client = kzalloc(sizeof(struct sde_power_client), GFP_KERNEL);
+	if (!client)
+		return ERR_PTR(-ENOMEM);
+
+	mutex_lock(&phandle->phandle_lock);
+	strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN);
+	client->usecase_ndx = VOTE_INDEX_DISABLE;
+	client->id = id;
+	pr_debug("client %s created:%pK id :%d\n", client_name,
+		client, id);
+	id++;
+	list_add(&client->list, &phandle->power_client_clist);
+	mutex_unlock(&phandle->phandle_lock);
+
+	return client;
+}
+
+void sde_power_client_destroy(struct sde_power_handle *phandle,
+	struct sde_power_client *client)
+{
+	if (!client  || !phandle) {
+		pr_err("reg bus vote: invalid client handle\n");
+	} else {
+		pr_debug("bus vote client %s destroyed:%pK id:%u\n",
+			client->name, client, client->id);
+		mutex_lock(&phandle->phandle_lock);
+		list_del_init(&client->list);
+		mutex_unlock(&phandle->phandle_lock);
+		kfree(client);
+	}
+}
+
+static int sde_power_parse_dt_supply(struct platform_device *pdev,
+				struct dss_module_power *mp)
+{
+	int i = 0, rc = 0;
+	u32 tmp = 0;
+	struct device_node *of_node = NULL, *supply_root_node = NULL;
+	struct device_node *supply_node = NULL;
+
+	if (!pdev || !mp) {
+		pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
+		return -EINVAL;
+	}
+
+	of_node = pdev->dev.of_node;
+
+	mp->num_vreg = 0;
+	supply_root_node = of_get_child_by_name(of_node,
+						"qcom,platform-supply-entries");
+	if (!supply_root_node) {
+		pr_debug("no supply entry present\n");
+		return rc;
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node)
+		mp->num_vreg++;
+
+	if (mp->num_vreg == 0) {
+		pr_debug("no vreg\n");
+		return rc;
+	}
+
+	pr_debug("vreg found. count=%d\n", mp->num_vreg);
+	mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
+						mp->num_vreg, GFP_KERNEL);
+	if (!mp->vreg_config) {
+		rc = -ENOMEM;
+		return rc;
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node) {
+
+		const char *st = NULL;
+
+		rc = of_property_read_string(supply_node,
+						"qcom,supply-name", &st);
+		if (rc) {
+			pr_err("error reading name. rc=%d\n", rc);
+			goto error;
+		}
+
+		strlcpy(mp->vreg_config[i].vreg_name, st,
+					sizeof(mp->vreg_config[i].vreg_name));
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-min-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading min volt. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].min_voltage = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-max-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading max volt. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].max_voltage = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-enable-load", &tmp);
+		if (rc) {
+			pr_err("error reading enable load. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].enable_load = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-disable-load", &tmp);
+		if (rc) {
+			pr_err("error reading disable load. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].disable_load = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-pre-on-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply pre sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-pre-off-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply pre sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-post-on-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply post sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-post-off-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply post sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
+
+		pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
+					mp->vreg_config[i].vreg_name,
+					mp->vreg_config[i].min_voltage,
+					mp->vreg_config[i].max_voltage,
+					mp->vreg_config[i].enable_load,
+					mp->vreg_config[i].disable_load,
+					mp->vreg_config[i].pre_on_sleep,
+					mp->vreg_config[i].post_on_sleep,
+					mp->vreg_config[i].pre_off_sleep,
+					mp->vreg_config[i].post_off_sleep);
+		++i;
+
+		rc = 0;
+	}
+
+	return rc;
+
+error:
+	if (mp->vreg_config) {
+		devm_kfree(&pdev->dev, mp->vreg_config);
+		mp->vreg_config = NULL;
+		mp->num_vreg = 0;
+	}
+
+	return rc;
+}
+
+static int sde_power_parse_dt_clock(struct platform_device *pdev,
+					struct dss_module_power *mp)
+{
+	u32 i = 0, rc = 0;
+	const char *clock_name;
+	u32 clock_rate = 0;
+	u32 clock_max_rate = 0;
+	int num_clk = 0;
+
+	if (!pdev || !mp) {
+		pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
+		return -EINVAL;
+	}
+
+	mp->num_clk = 0;
+	num_clk = of_property_count_strings(pdev->dev.of_node,
+							"clock-names");
+	if (num_clk <= 0) {
+		pr_debug("clocks are not defined\n");
+		goto clk_err;
+	}
+
+	mp->num_clk = num_clk;
+	mp->clk_config = devm_kzalloc(&pdev->dev,
+			sizeof(struct dss_clk) * num_clk, GFP_KERNEL);
+	if (!mp->clk_config) {
+		rc = -ENOMEM;
+		mp->num_clk = 0;
+		goto clk_err;
+	}
+
+	for (i = 0; i < num_clk; i++) {
+		of_property_read_string_index(pdev->dev.of_node, "clock-names",
+							i, &clock_name);
+		strlcpy(mp->clk_config[i].clk_name, clock_name,
+				sizeof(mp->clk_config[i].clk_name));
+
+		of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
+							i, &clock_rate);
+		mp->clk_config[i].rate = clock_rate;
+
+		if (!clock_rate)
+			mp->clk_config[i].type = DSS_CLK_AHB;
+		else
+			mp->clk_config[i].type = DSS_CLK_PCLK;
+
+		clock_max_rate = 0;
+		of_property_read_u32_index(pdev->dev.of_node, "clock-max-rate",
+							i, &clock_max_rate);
+		mp->clk_config[i].max_rate = clock_max_rate;
+	}
+
+clk_err:
+	return rc;
+}
+
+#ifdef CONFIG_QCOM_BUS_SCALING
+
+#define MAX_AXI_PORT_COUNT 3
+
+static int _sde_power_data_bus_set_quota(
+		struct sde_power_data_bus_handle *pdbus,
+		u64 ab_quota_rt, u64 ab_quota_nrt,
+		u64 ib_quota_rt, u64 ib_quota_nrt)
+{
+	int new_uc_idx;
+	u64 ab_quota[MAX_AXI_PORT_COUNT] = {0, 0};
+	u64 ib_quota[MAX_AXI_PORT_COUNT] = {0, 0};
+	int rc;
+
+	if (pdbus->data_bus_hdl < 1) {
+		pr_err("invalid bus handle %d\n", pdbus->data_bus_hdl);
+		return -EINVAL;
+	}
+
+	if (!ab_quota_rt && !ab_quota_nrt && !ib_quota_rt && !ib_quota_nrt)  {
+		new_uc_idx = 0;
+	} else {
+		int i;
+		struct msm_bus_vectors *vect = NULL;
+		struct msm_bus_scale_pdata *bw_table =
+			pdbus->data_bus_scale_table;
+		u32 nrt_axi_port_cnt = pdbus->nrt_axi_port_cnt;
+		u32 total_axi_port_cnt = pdbus->axi_port_cnt;
+		u32 rt_axi_port_cnt = total_axi_port_cnt - nrt_axi_port_cnt;
+		int match_cnt = 0;
+
+		if (!bw_table || !total_axi_port_cnt ||
+		    total_axi_port_cnt > MAX_AXI_PORT_COUNT) {
+			pr_err("invalid input\n");
+			return -EINVAL;
+		}
+
+		if (pdbus->bus_channels) {
+			ib_quota_rt = div_u64(ib_quota_rt,
+						pdbus->bus_channels);
+			ib_quota_nrt = div_u64(ib_quota_nrt,
+						pdbus->bus_channels);
+		}
+
+		if (nrt_axi_port_cnt) {
+
+			ab_quota_rt = div_u64(ab_quota_rt, rt_axi_port_cnt);
+			ab_quota_nrt = div_u64(ab_quota_nrt, nrt_axi_port_cnt);
+
+			for (i = 0; i < total_axi_port_cnt; i++) {
+				if (i < rt_axi_port_cnt) {
+					ab_quota[i] = ab_quota_rt;
+					ib_quota[i] = ib_quota_rt;
+				} else {
+					ab_quota[i] = ab_quota_nrt;
+					ib_quota[i] = ib_quota_nrt;
+				}
+			}
+		} else {
+			ab_quota[0] = div_u64(ab_quota_rt + ab_quota_nrt,
+					total_axi_port_cnt);
+			ib_quota[0] = ib_quota_rt + ib_quota_nrt;
+
+			for (i = 1; i < total_axi_port_cnt; i++) {
+				ab_quota[i] = ab_quota[0];
+				ib_quota[i] = ib_quota[0];
+			}
+		}
+
+		for (i = 0; i < total_axi_port_cnt; i++) {
+			vect = &bw_table->usecase
+				[pdbus->curr_bw_uc_idx].vectors[i];
+			/* avoid performing updates for small changes */
+			if ((ab_quota[i] == vect->ab) &&
+				(ib_quota[i] == vect->ib))
+				match_cnt++;
+		}
+
+		if (match_cnt == total_axi_port_cnt) {
+			pr_debug("skip BW vote\n");
+			return 0;
+		}
+
+		new_uc_idx = (pdbus->curr_bw_uc_idx %
+			(bw_table->num_usecases - 1)) + 1;
+
+		for (i = 0; i < total_axi_port_cnt; i++) {
+			vect = &bw_table->usecase[new_uc_idx].vectors[i];
+			vect->ab = ab_quota[i];
+			vect->ib = ib_quota[i];
+
+			pr_debug("uc_idx=%d %s path idx=%d ab=%llu ib=%llu\n",
+				new_uc_idx, (i < rt_axi_port_cnt) ? "rt" : "nrt"
+				, i, vect->ab, vect->ib);
+		}
+	}
+	pdbus->curr_bw_uc_idx = new_uc_idx;
+	pdbus->ao_bw_uc_idx = new_uc_idx;
+
+	if ((pdbus->bus_ref_cnt == 0) && pdbus->curr_bw_uc_idx) {
+		rc = 0;
+	} else { /* vote BW if bus_bw_cnt > 0 or uc_idx is zero */
+		SDE_ATRACE_BEGIN("msm_bus_scale_req");
+		rc = msm_bus_scale_client_update_request(pdbus->data_bus_hdl,
+			new_uc_idx);
+		SDE_ATRACE_END("msm_bus_scale_req");
+	}
+	return rc;
+}
+
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota)
+{
+	int rc = 0;
+	int i;
+	u64 total_ab_rt = 0, total_ib_rt = 0;
+	u64 total_ab_nrt = 0, total_ib_nrt = 0;
+	struct sde_power_client *client;
+
+	if (!phandle || !pclient ||
+			bus_client >= SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX) {
+		pr_err("invalid parameters\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phandle->phandle_lock);
+
+	pclient->ab[bus_client] = ab_quota;
+	pclient->ib[bus_client] = ib_quota;
+	trace_sde_perf_update_bus(bus_client, ab_quota, ib_quota);
+
+	list_for_each_entry(client, &phandle->power_client_clist, list) {
+		for (i = 0; i < SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX; i++) {
+			if (i == SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT) {
+				total_ab_nrt += client->ab[i];
+				total_ib_nrt += client->ib[i];
+			} else {
+				total_ab_rt += client->ab[i];
+				total_ib_rt = max(total_ib_rt, client->ib[i]);
+			}
+		}
+	}
+
+	rc = _sde_power_data_bus_set_quota(&phandle->data_bus_handle,
+			total_ab_rt, total_ab_nrt,
+			total_ib_rt, total_ib_nrt);
+
+	mutex_unlock(&phandle->phandle_lock);
+
+	return rc;
+}
+
+static void sde_power_data_bus_unregister(
+		struct sde_power_data_bus_handle *pdbus)
+{
+	if (pdbus->data_bus_hdl) {
+		msm_bus_scale_unregister_client(pdbus->data_bus_hdl);
+		pdbus->data_bus_hdl = 0;
+	}
+}
+
+static int sde_power_data_bus_parse(struct platform_device *pdev,
+	struct sde_power_data_bus_handle *pdbus)
+{
+	struct device_node *node;
+	int rc = 0;
+	int paths;
+
+	pdbus->bus_channels = 1;
+	rc = of_property_read_u32(pdev->dev.of_node,
+		"qcom,sde-dram-channels", &pdbus->bus_channels);
+	if (rc) {
+		pr_debug("number of channels property not specified\n");
+		rc = 0;
+	}
+
+	pdbus->nrt_axi_port_cnt = 0;
+	rc = of_property_read_u32(pdev->dev.of_node,
+			"qcom,sde-num-nrt-paths",
+			&pdbus->nrt_axi_port_cnt);
+	if (rc) {
+		pr_debug("number of axi port property not specified\n");
+		rc = 0;
+	}
+
+	node = of_get_child_by_name(pdev->dev.of_node, "qcom,sde-data-bus");
+	if (node) {
+		rc = of_property_read_u32(node,
+				"qcom,msm-bus,num-paths", &paths);
+		if (rc) {
+			pr_err("Error. qcom,msm-bus,num-paths not found\n");
+			return rc;
+		}
+		pdbus->axi_port_cnt = paths;
+
+		pdbus->data_bus_scale_table =
+				msm_bus_pdata_from_node(pdev, node);
+		if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) {
+			pr_err("reg bus handle parsing failed\n");
+			rc = PTR_ERR(pdbus->data_bus_scale_table);
+			goto end;
+		}
+		pdbus->data_bus_hdl = msm_bus_scale_register_client(
+				pdbus->data_bus_scale_table);
+		if (!pdbus->data_bus_hdl) {
+			pr_err("data_bus_client register failed\n");
+			rc = -EINVAL;
+			goto end;
+		}
+		pr_debug("register data_bus_hdl=%x\n", pdbus->data_bus_hdl);
+
+		/*
+		 * Following call will not result in actual vote rather update
+		 * the current index and ab/ib value. When continuous splash
+		 * is enabled, actual vote will happen when splash handoff is
+		 * done.
+		 */
+		return _sde_power_data_bus_set_quota(pdbus,
+				SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA);
+	}
+
+end:
+	return rc;
+}
+
+static int sde_power_reg_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	struct device_node *node;
+	struct msm_bus_scale_pdata *bus_scale_table;
+	int rc = 0;
+
+	node = of_get_child_by_name(pdev->dev.of_node, "qcom,sde-reg-bus");
+	if (node) {
+		bus_scale_table = msm_bus_pdata_from_node(pdev, node);
+		if (IS_ERR_OR_NULL(bus_scale_table)) {
+			pr_err("reg bus handle parsing failed\n");
+			rc = PTR_ERR(bus_scale_table);
+			goto end;
+		}
+		phandle->reg_bus_hdl = msm_bus_scale_register_client(
+			      bus_scale_table);
+		if (!phandle->reg_bus_hdl) {
+			pr_err("reg_bus_client register failed\n");
+			rc = -EINVAL;
+			goto end;
+		}
+		pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl);
+	}
+
+end:
+	return rc;
+}
+
+static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
+{
+	if (reg_bus_hdl)
+		msm_bus_scale_unregister_client(reg_bus_hdl);
+}
+
+static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
+{
+	int rc = 0;
+
+	if (reg_bus_hdl)
+		rc = msm_bus_scale_client_update_request(reg_bus_hdl,
+								usecase_ndx);
+	if (rc)
+		pr_err("failed to set reg bus vote rc=%d\n", rc);
+
+	return rc;
+}
+#else
+static int sde_power_data_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	return 0;
+}
+
+static void sde_power_data_bus_unregister(u32 reg_bus_hdl)
+{
+}
+
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota)
+{
+	return 0;
+}
+
+static int sde_power_reg_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	return 0;
+}
+
+static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
+{
+}
+
+static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
+{
+	return 0;
+}
+#endif
+
+void sde_power_data_bus_bandwidth_ctrl(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient, int enable)
+{
+	struct sde_power_data_bus_handle *pdbus;
+	int changed = 0;
+
+	if (!phandle || !pclient) {
+		pr_err("invalid power/client handle\n");
+		return;
+	}
+
+	pdbus = &phandle->data_bus_handle;
+
+	mutex_lock(&phandle->phandle_lock);
+	if (enable) {
+		if (pdbus->bus_ref_cnt == 0)
+			changed++;
+		pdbus->bus_ref_cnt++;
+	} else {
+		if (pdbus->bus_ref_cnt) {
+			pdbus->bus_ref_cnt--;
+			if (pdbus->bus_ref_cnt == 0)
+				changed++;
+		} else {
+			pr_debug("Can not be turned off\n");
+		}
+	}
+
+	pr_debug("%pS: task:%s bw_cnt=%d changed=%d enable=%d\n",
+		__builtin_return_address(0), current->group_leader->comm,
+		pdbus->bus_ref_cnt, changed, enable);
+
+	if (changed) {
+		SDE_ATRACE_INT("data_bus_ctrl", enable);
+
+		if (!enable) {
+			if (!pdbus->handoff_pending) {
+				msm_bus_scale_client_update_request(
+						pdbus->data_bus_hdl, 0);
+				pdbus->ao_bw_uc_idx = 0;
+			}
+		} else {
+			msm_bus_scale_client_update_request(
+					pdbus->data_bus_hdl,
+					pdbus->curr_bw_uc_idx);
+		}
+	}
+
+	mutex_unlock(&phandle->phandle_lock);
+}
+
+int sde_power_resource_init(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	int rc = 0;
+	struct dss_module_power *mp;
+
+	if (!phandle || !pdev) {
+		pr_err("invalid input param\n");
+		rc = -EINVAL;
+		goto end;
+	}
+	mp = &phandle->mp;
+	phandle->dev = &pdev->dev;
+
+	rc = sde_power_parse_dt_clock(pdev, mp);
+	if (rc) {
+		pr_err("device clock parsing failed\n");
+		goto end;
+	}
+
+	rc = sde_power_parse_dt_supply(pdev, mp);
+	if (rc) {
+		pr_err("device vreg supply parsing failed\n");
+		goto parse_vreg_err;
+	}
+
+	rc = msm_dss_config_vreg(&pdev->dev,
+				mp->vreg_config, mp->num_vreg, 1);
+	if (rc) {
+		pr_err("vreg config failed rc=%d\n", rc);
+		goto vreg_err;
+	}
+
+	rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
+	if (rc) {
+		pr_err("clock get failed rc=%d\n", rc);
+		goto clk_err;
+	}
+
+	rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+	if (rc) {
+		pr_err("clock set rate failed rc=%d\n", rc);
+		goto bus_err;
+	}
+
+	rc = sde_power_reg_bus_parse(pdev, phandle);
+	if (rc) {
+		pr_err("register bus parse failed rc=%d\n", rc);
+		goto bus_err;
+	}
+
+	rc = sde_power_data_bus_parse(pdev, &phandle->data_bus_handle);
+	if (rc) {
+		pr_err("register data bus parse failed rc=%d\n", rc);
+		goto data_bus_err;
+	}
+
+	INIT_LIST_HEAD(&phandle->power_client_clist);
+	mutex_init(&phandle->phandle_lock);
+
+	return rc;
+
+data_bus_err:
+	sde_power_reg_bus_unregister(phandle->reg_bus_hdl);
+bus_err:
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+clk_err:
+	msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+	devm_kfree(&pdev->dev, mp->vreg_config);
+	mp->num_vreg = 0;
+parse_vreg_err:
+	devm_kfree(&pdev->dev, mp->clk_config);
+	mp->num_clk = 0;
+end:
+	return rc;
+}
+
+void sde_power_resource_deinit(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	struct dss_module_power *mp;
+
+	if (!phandle || !pdev) {
+		pr_err("invalid input param\n");
+		return;
+	}
+	mp = &phandle->mp;
+
+	sde_power_data_bus_unregister(&phandle->data_bus_handle);
+
+	sde_power_reg_bus_unregister(phandle->reg_bus_hdl);
+
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+
+	msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+
+	if (mp->clk_config)
+		devm_kfree(&pdev->dev, mp->clk_config);
+
+	if (mp->vreg_config)
+		devm_kfree(&pdev->dev, mp->vreg_config);
+
+	mp->num_vreg = 0;
+	mp->num_clk = 0;
+}
+
+int sde_power_resource_enable(struct sde_power_handle *phandle,
+	struct sde_power_client *pclient, bool enable)
+{
+	int rc = 0;
+	bool changed = false;
+	u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
+	struct sde_power_client *client;
+	struct dss_module_power *mp;
+
+	if (!phandle || !pclient) {
+		pr_err("invalid input argument\n");
+		return -EINVAL;
+	}
+
+	mp = &phandle->mp;
+
+	mutex_lock(&phandle->phandle_lock);
+	if (enable)
+		pclient->refcount++;
+	else if (pclient->refcount)
+		pclient->refcount--;
+
+	if (pclient->refcount)
+		pclient->usecase_ndx = VOTE_INDEX_LOW;
+	else
+		pclient->usecase_ndx = VOTE_INDEX_DISABLE;
+
+	list_for_each_entry(client, &phandle->power_client_clist, list) {
+		if (client->usecase_ndx < VOTE_INDEX_MAX &&
+		    client->usecase_ndx > max_usecase_ndx)
+			max_usecase_ndx = client->usecase_ndx;
+	}
+
+	if (phandle->current_usecase_ndx != max_usecase_ndx) {
+		changed = true;
+		prev_usecase_ndx = phandle->current_usecase_ndx;
+		phandle->current_usecase_ndx = max_usecase_ndx;
+	}
+
+	pr_debug("%pS: changed=%d current idx=%d request client %s id:%u enable:%d refcount:%d\n",
+		__builtin_return_address(0), changed, max_usecase_ndx,
+		pclient->name, pclient->id, enable, pclient->refcount);
+
+	if (!changed)
+		goto end;
+
+	if (enable) {
+		rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+		if (rc) {
+			pr_err("failed to enable vregs rc=%d\n", rc);
+			goto vreg_err;
+		}
+
+		rc = sde_power_reg_bus_update(phandle->reg_bus_hdl,
+							max_usecase_ndx);
+		if (rc) {
+			pr_err("failed to set reg bus vote rc=%d\n", rc);
+			goto reg_bus_hdl_err;
+		}
+
+		rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+		if (rc) {
+			pr_err("clock enable failed rc:%d\n", rc);
+			goto clk_err;
+		}
+	} else {
+		msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+
+		sde_power_reg_bus_update(phandle->reg_bus_hdl,
+							max_usecase_ndx);
+
+		msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+	}
+
+end:
+	mutex_unlock(&phandle->phandle_lock);
+	return rc;
+
+clk_err:
+	sde_power_reg_bus_update(phandle->reg_bus_hdl, prev_usecase_ndx);
+reg_bus_hdl_err:
+	msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+	phandle->current_usecase_ndx = prev_usecase_ndx;
+	mutex_unlock(&phandle->phandle_lock);
+	return rc;
+}
+
+int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name,
+	u64 rate)
+{
+	int i, rc = -EINVAL;
+	struct dss_module_power *mp;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return -EINVAL;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			if (mp->clk_config[i].max_rate &&
+					(rate > mp->clk_config[i].max_rate))
+				rate = mp->clk_config[i].max_rate;
+
+			mp->clk_config[i].rate = rate;
+			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+			break;
+		}
+	}
+
+	return rc;
+}
+
+u64 sde_power_clk_get_rate(struct sde_power_handle *phandle, char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	u64 rate = -EINVAL;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return -EINVAL;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			rate = clk_get_rate(mp->clk_config[i].clk);
+			break;
+		}
+	}
+
+	return rate;
+}
+
+u64 sde_power_clk_get_max_rate(struct sde_power_handle *phandle,
+		char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	u64 rate = 0;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return 0;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			rate = mp->clk_config[i].max_rate;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
+		char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	struct clk *clk = NULL;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return 0;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			clk = mp->clk_config[i].clk;
+			break;
+		}
+	}
+
+	return clk;
+}
diff --git a/drivers/gpu/drm/msm/sde_power_handle.h b/drivers/gpu/drm/msm/sde_power_handle.h
new file mode 100644
index 0000000000000000000000000000000000000000..b982d17043124a59e86ea115942d4ab6e0c0fe56
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_power_handle.h
@@ -0,0 +1,229 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SDE_POWER_HANDLE_H_
+#define _SDE_POWER_HANDLE_H_
+
+#define MAX_CLIENT_NAME_LEN 128
+
+#define SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA 2000000000
+#define SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA 2000000000
+
+/**
+ * mdss_bus_vote_type: register bus vote type
+ * VOTE_INDEX_DISABLE: removes the client vote
+ * VOTE_INDEX_LOW: keeps the lowest vote for register bus
+ * VOTE_INDEX_MAX: invalid
+ */
+enum mdss_bus_vote_type {
+	VOTE_INDEX_DISABLE,
+	VOTE_INDEX_LOW,
+	VOTE_INDEX_MAX,
+};
+
+/**
+ * enum sde_power_handle_data_bus_client - type of axi bus clients
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT: core real-time bus client
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT: core non-real-time bus client
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX: maximum number of bus client type
+ */
+enum sde_power_handle_data_bus_client {
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT,
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX
+};
+
+/**
+ * struct sde_power_client: stores the power client for sde driver
+ * @name:	name of the client
+ * @usecase_ndx: current regs bus vote type
+ * @refcount:	current refcount if multiple modules are using same
+ *              same client for enable/disable. Power module will
+ *              aggregate the refcount and vote accordingly for this
+ *              client.
+ * @id:		assigned during create. helps for debugging.
+ * @list:	list to attach power handle master list
+ * @ab:         arbitrated bandwidth for each bus client
+ * @ib:         instantaneous bandwidth for each bus client
+ */
+struct sde_power_client {
+	char name[MAX_CLIENT_NAME_LEN];
+	short usecase_ndx;
+	short refcount;
+	u32 id;
+	struct list_head list;
+	u64 ab[SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
+	u64 ib[SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
+};
+
+/**
+ * struct sde_power_data_handle: power handle struct for data bus
+ * @data_bus_scale_table: pointer to bus scaling table
+ * @data_bus_hdl: current data bus handle
+ * @axi_port_cnt: number of rt axi ports
+ * @nrt_axi_port_cnt: number of nrt axi ports
+ * @bus_channels: number of memory bus channels
+ * @curr_bw_uc_idx: current use case index of data bus
+ * @ao_bw_uc_idx: active only use case index of data bus
+ * @bus_ref_cnt: reference count of data bus enable request
+ * @handoff_pending: True to indicate if bootloader hand-over is pending
+ */
+struct sde_power_data_bus_handle {
+	struct msm_bus_scale_pdata *data_bus_scale_table;
+	u32 data_bus_hdl;
+	u32 axi_port_cnt;
+	u32 nrt_axi_port_cnt;
+	u32 bus_channels;
+	u32 curr_bw_uc_idx;
+	u32 ao_bw_uc_idx;
+	u32 bus_ref_cnt;
+	int handoff_pending;
+};
+
+/**
+ * struct sde_power_handle: power handle main struct
+ * @mp:		module power for clock and regulator
+ * @client_clist: master list to store all clients
+ * @phandle_lock: lock to synchronize the enable/disable
+ * @dev: pointer to device structure
+ * @usecase_ndx: current usecase index
+ * @reg_bus_hdl: current register bus handle
+ * @data_bus_handle: context structure for data bus control
+ */
+struct sde_power_handle {
+	struct dss_module_power mp;
+	struct list_head power_client_clist;
+	struct mutex phandle_lock;
+	struct device *dev;
+	u32 current_usecase_ndx;
+	u32 reg_bus_hdl;
+	struct sde_power_data_bus_handle data_bus_handle;
+};
+
+/**
+ * sde_power_resource_init() - initializes the sde power handle
+ * @pdev:   platform device to search the power resources
+ * @pdata:  power handle to store the power resources
+ *
+ * Return: error code.
+ */
+int sde_power_resource_init(struct platform_device *pdev,
+	struct sde_power_handle *pdata);
+
+/**
+ * sde_power_resource_deinit() - release the sde power handle
+ * @pdev:   platform device for power resources
+ * @pdata:  power handle containing the resources
+ *
+ * Return: error code.
+ */
+void sde_power_resource_deinit(struct platform_device *pdev,
+	struct sde_power_handle *pdata);
+
+/**
+ * sde_power_client_create() - create the client on power handle
+ * @pdata:  power handle containing the resources
+ * @client_name: new client name for registration
+ *
+ * Return: error code.
+ */
+struct sde_power_client *sde_power_client_create(struct sde_power_handle *pdata,
+	char *client_name);
+
+/**
+ * sde_power_client_destroy() - destroy the client on power handle
+ * @pdata:  power handle containing the resources
+ * @client_name: new client name for registration
+ *
+ * Return: none
+ */
+void sde_power_client_destroy(struct sde_power_handle *phandle,
+	struct sde_power_client *client);
+
+/**
+ * sde_power_resource_enable() - enable/disable the power resources
+ * @pdata:  power handle containing the resources
+ * @client: client information to enable/disable its vote
+ * @enable: boolean request for enable/disable
+ *
+ * Return: error code.
+ */
+int sde_power_resource_enable(struct sde_power_handle *pdata,
+	struct sde_power_client *pclient, bool enable);
+
+/**
+ * sde_power_clk_set_rate() - set the clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name which needs rate update.
+ * @rate:       Requested rate.
+ *
+ * Return: error code.
+ */
+int sde_power_clk_set_rate(struct sde_power_handle *pdata, char *clock_name,
+	u64 rate);
+
+/**
+ * sde_power_clk_get_rate() - get the clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the rate
+ *
+ * Return: current clock rate
+ */
+u64 sde_power_clk_get_rate(struct sde_power_handle *pdata, char *clock_name);
+
+/**
+ * sde_power_clk_get_max_rate() - get the maximum clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the max rate.
+ *
+ * Return: maximum clock rate or 0 if not found.
+ */
+u64 sde_power_clk_get_max_rate(struct sde_power_handle *pdata,
+		char *clock_name);
+
+/**
+ * sde_power_clk_get_clk() - get the clock
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the clk pointer.
+ *
+ * Return: Pointer to clock
+ */
+struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
+		char *clock_name);
+
+/**
+ * sde_power_data_bus_set_quota() - set data bus quota for power client
+ * @phandle:  power handle containing the resources
+ * @client: client information to set quota
+ * @bus_client: real-time or non-real-time bus client
+ * @ab_quota: arbitrated bus bandwidth
+ * @ib_quota: instantaneous bus bandwidth
+ *
+ * Return: zero if success, or error code otherwise
+ */
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota);
+
+/**
+ * sde_power_data_bus_bandwidth_ctrl() - control data bus bandwidth enable
+ * @phandle:  power handle containing the resources
+ * @client: client information to bandwidth control
+ * @enable: true to enable bandwidth for data base
+ *
+ * Return: none
+ */
+void sde_power_data_bus_bandwidth_ctrl(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient, int enable);
+
+#endif /* _SDE_POWER_HANDLE_H_ */
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 3f0c6909dda17f9ec14959353a440da171a87ca6..aab1530661a5d05ee40f457b684c6b62408c0245 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -61,7 +61,7 @@ struct drm_mode_object {
 	struct drm_object_properties *properties;
 };
 
-#define DRM_OBJECT_MAX_PROPERTY 24
+#define DRM_OBJECT_MAX_PROPERTY 64
 struct drm_object_properties {
 	int count, atomic_count;
 	/* NOTE: if we ever start dynamically destroying properties (ie.
diff --git a/include/linux/mdss_io_util.h b/include/linux/mdss_io_util.h
index 6ad21e88787745fd11baf6a10feac0d0bb2a831b..5b2587b28737d23a3aa698e27b4b8bbffd226df5 100644
--- a/include/linux/mdss_io_util.h
+++ b/include/linux/mdss_io_util.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -77,6 +77,7 @@ struct dss_clk {
 	char clk_name[32];
 	enum dss_clk_type type;
 	unsigned long rate;
+	unsigned long max_rate;
 };
 
 struct dss_module_power {
diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
index 38d437096c358c884a403e4f3f5be5fb86f21d3b..c3c78a0d0052273b126d20a8822a3e699620090b 100644
--- a/include/uapi/drm/Kbuild
+++ b/include/uapi/drm/Kbuild
@@ -18,3 +18,5 @@ header-y += via_drm.h
 header-y += vmwgfx_drm.h
 header-y += msm_drm.h
 header-y += virtgpu_drm.h
+header-y += sde_drm.h
+header-y += msm_drm_pp.h
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b69a7753558ff27a07748f2d5ca7f3f054b2ba2..53d7c80f5eb0041555bf70a5076d25a1499736dc 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -229,4 +229,12 @@
  */
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
 
+/*
+ * Qualcomm Compressed Format
+ *
+ * Refers to a compressed variant of the base format that is compressed.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
+
 #endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca401de8b4f4400478f500352ddd48380644..09c22caf34dd24debeedb579a013b63daf05f118 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -72,6 +72,7 @@
 #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6<<14)
 #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7<<14)
 #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8<<14)
+#define  DRM_MODE_FLAG_SEAMLESS			(1<<19)
 
 
 /* DPMS flags */
@@ -354,6 +355,7 @@ struct drm_mode_fb_cmd {
 
 #define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
 #define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_SECURE	(1<<2) /* for secure framebuffers */
 
 struct drm_mode_fb_cmd2 {
 	__u32 fb_id;
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 75a232b9a970db9e8c8886f1fcd0f4f1f834ed94..fd1be42188cd96bbb6a5e889f887e78c933b6092 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -20,6 +20,7 @@
 
 #include <stddef.h>
 #include <drm/drm.h>
+#include <drm/sde_drm.h>
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints:
@@ -196,6 +197,39 @@ struct drm_msm_wait_fence {
 	struct drm_msm_timespec timeout;   /* in */
 };
 
+/**
+ * struct drm_msm_event_req - Payload to event enable/disable ioctls.
+ * @object_id: DRM object id. Ex: for crtc pass crtc id.
+ * @object_type: DRM object type. Ex: for crtc set it to DRM_MODE_OBJECT_CRTC.
+ * @event: Event for which notification is being enabled/disabled.
+ *         Ex: for Histogram set - DRM_EVENT_HISTOGRAM.
+ * @client_context: Opaque pointer that will be returned during event response
+ *                  notification.
+ * @index: Object index(ex: crtc index), optional for user-space to set.
+ *         Driver will override value based on object_id and object_type.
+ */
+struct drm_msm_event_req {
+	__u32 object_id;
+	__u32 object_type;
+	__u32 event;
+	__u64 client_context;
+	__u32 index;
+};
+
+/**
+ * struct drm_msm_event_resp - payload returned when read is called for
+ *                            custom notifications.
+ * @base: Event type and length of complete notification payload.
+ * @info: Contains information about DRM that which raised this event.
+ * @data: Custom payload that driver returns for event type.
+ *        size of data = base.length - (sizeof(base) + sizeof(info))
+ */
+struct drm_msm_event_resp {
+	struct drm_event base;
+	struct drm_msm_event_req info;
+	__u8 data[];
+};
+
 #define DRM_MSM_GET_PARAM              0x00
 /* placeholder:
 #define DRM_MSM_SET_PARAM              0x01
@@ -206,7 +240,18 @@ struct drm_msm_wait_fence {
 #define DRM_MSM_GEM_CPU_FINI           0x05
 #define DRM_MSM_GEM_SUBMIT             0x06
 #define DRM_MSM_WAIT_FENCE             0x07
-#define DRM_MSM_NUM_IOCTLS             0x08
+#define DRM_SDE_WB_CONFIG              0x08
+#define DRM_MSM_REGISTER_EVENT         0x09
+#define DRM_MSM_DEREGISTER_EVENT       0x0A
+#define DRM_MSM_NUM_IOCTLS             0x0B
+
+/**
+ * Currently DRM framework supports only VSYNC event.
+ * Starting the custom events at 0xff to provide space for DRM
+ * framework to add new events.
+ */
+#define DRM_EVENT_HISTOGRAM 0xff
+#define DRM_EVENT_AD 0x100
 
 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
@@ -215,5 +260,10 @@ struct drm_msm_wait_fence {
 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
-
+#define DRM_IOCTL_SDE_WB_CONFIG \
+	DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
+#define DRM_IOCTL_MSM_REGISTER_EVENT   DRM_IOW((DRM_COMMAND_BASE + \
+			DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
+#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
+			DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
 #endif /* __MSM_DRM_H__ */
diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ed3a13953ef4f910de95c6bd9c8cbfd39bce19f
--- /dev/null
+++ b/include/uapi/drm/msm_drm_pp.h
@@ -0,0 +1,82 @@
+#ifndef _MSM_DRM_PP_H_
+#define _MSM_DRM_PP_H_
+
+#include <drm/drm.h>
+
+/**
+ * struct drm_msm_pcc_coeff - PCC coefficient structure for each color
+ *                            component.
+ * @c: constant coefficient.
+ * @r: red coefficient.
+ * @g: green coefficient.
+ * @b: blue coefficient.
+ * @rg: red green coefficient.
+ * @gb: green blue coefficient.
+ * @rb: red blue coefficient.
+ * @rgb: red blue green coefficient.
+ */
+
+struct drm_msm_pcc_coeff {
+	__u32 c;
+	__u32 r;
+	__u32 g;
+	__u32 b;
+	__u32 rg;
+	__u32 gb;
+	__u32 rb;
+	__u32 rgb;
+};
+
+/**
+ * struct drm_msm_pcc - pcc feature structure
+ * flags: for customizing operations
+ * r: red coefficients.
+ * g: green coefficients.
+ * b: blue coefficients.
+ */
+
+struct drm_msm_pcc {
+	__u64 flags;
+	struct drm_msm_pcc_coeff r;
+	struct drm_msm_pcc_coeff g;
+	struct drm_msm_pcc_coeff b;
+};
+
+/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
+ * flags: for customizing vlut operation
+ * val: vLUT values
+ */
+#define PA_VLUT_SIZE 256
+struct drm_msm_pa_vlut {
+	__u64 flags;
+	__u32 val[PA_VLUT_SIZE];
+};
+
+/* struct drm_msm_memcol - Memory color feature strucuture.
+ *                         Skin, sky, foliage features are supported.
+ * @prot_flags: Bit mask for enabling protection feature.
+ * @color_adjust_p0: Adjustment curve.
+ * @color_adjust_p1: Adjustment curve.
+ * @color_adjust_p2: Adjustment curve.
+ * @blend_gain: Blend gain weightage from othe PA features.
+ * @sat_hold: Saturation hold value.
+ * @val_hold: Value hold info.
+ * @hue_region: Hue qualifier.
+ * @sat_region: Saturation qualifier.
+ * @val_region: Value qualifier.
+ */
+#define DRM_MSM_MEMCOL
+struct drm_msm_memcol {
+	__u64 prot_flags;
+	__u32 color_adjust_p0;
+	__u32 color_adjust_p1;
+	__u32 color_adjust_p2;
+	__u32 blend_gain;
+	__u32 sat_hold;
+	__u32 val_hold;
+	__u32 hue_region;
+	__u32 sat_region;
+	__u32 val_region;
+};
+
+#endif /* _MSM_DRM_PP_H_ */
diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h
new file mode 100644
index 0000000000000000000000000000000000000000..c7bed3b1ccf3dfafb03d68dc7006fa67fea5faf9
--- /dev/null
+++ b/include/uapi/drm/sde_drm.h
@@ -0,0 +1,298 @@
+#ifndef _SDE_DRM_H_
+#define _SDE_DRM_H_
+
+/* Total number of supported color planes */
+#define SDE_MAX_PLANES  4
+
+/* Total number of parameterized detail enhancer mapping curves */
+#define SDE_MAX_DE_CURVES 3
+
+ /* Y/RGB and UV filter configuration */
+#define FILTER_EDGE_DIRECTED_2D		0x0
+#define FILTER_CIRCULAR_2D		0x1
+#define FILTER_SEPARABLE_1D		0x2
+#define FILTER_BILINEAR			0x3
+
+/* Alpha filters */
+#define FILTER_ALPHA_DROP_REPEAT	0x0
+#define FILTER_ALPHA_BILINEAR		0x1
+#define FILTER_ALPHA_2D			0x3
+
+/* Blend filters */
+#define FILTER_BLEND_CIRCULAR_2D	0x0
+#define FILTER_BLEND_SEPARABLE_1D	0x1
+
+/* LUT configuration flags */
+#define SCALER_LUT_SWAP			0x1
+#define SCALER_LUT_DIR_WR		0x2
+#define SCALER_LUT_Y_CIR_WR		0x4
+#define SCALER_LUT_UV_CIR_WR		0x8
+#define SCALER_LUT_Y_SEP_WR		0x10
+#define SCALER_LUT_UV_SEP_WR		0x20
+
+/**
+ * Blend operations for "blend_op" property
+ *
+ * @SDE_DRM_BLEND_OP_NOT_DEFINED:   No blend operation defined for the layer.
+ * @SDE_DRM_BLEND_OP_OPAQUE:        Apply a constant blend operation. The layer
+ *                                  would appear opaque in case fg plane alpha
+ *                                  is 0xff.
+ * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
+ *                                  has alpha pre-multiplication done. If the fg
+ *                                  plane alpha is less than 0xff, apply
+ *                                  modulation as well. This operation is
+ *                                  intended on layers having alpha channel.
+ * @SDE_DRM_BLEND_OP_COVERAGE:      Apply source over blend rule. Layer is not
+ *                                  alpha pre-multiplied. Apply
+ *                                  pre-multiplication. If fg plane alpha is
+ *                                  less than 0xff, apply modulation as well.
+ * @SDE_DRM_BLEND_OP_MAX:           Used to track maximum blend operation
+ *                                  possible by mdp.
+ */
+#define SDE_DRM_BLEND_OP_NOT_DEFINED    0
+#define SDE_DRM_BLEND_OP_OPAQUE         1
+#define SDE_DRM_BLEND_OP_PREMULTIPLIED  2
+#define SDE_DRM_BLEND_OP_COVERAGE       3
+#define SDE_DRM_BLEND_OP_MAX            4
+
+/**
+ * Bit masks for "src_config" property
+ * construct bitmask via (1UL << SDE_DRM_<flag>)
+ */
+#define SDE_DRM_DEINTERLACE         0   /* Specifies interlaced input */
+
+/* DRM bitmasks are restricted to 0..63 */
+#define SDE_DRM_BITMASK_COUNT       64
+
+/**
+ * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure
+ * @num_ext_pxls_lr: Number of total horizontal pixels
+ * @num_ext_pxls_tb: Number of total vertical lines
+ * @left_ftch:       Number of extra pixels to overfetch from left
+ * @right_ftch:      Number of extra pixels to overfetch from right
+ * @top_ftch:        Number of extra lines to overfetch from top
+ * @btm_ftch:        Number of extra lines to overfetch from bottom
+ * @left_rpt:        Number of extra pixels to repeat from left
+ * @right_rpt:       Number of extra pixels to repeat from right
+ * @top_rpt:         Number of extra lines to repeat from top
+ * @btm_rpt:         Number of extra lines to repeat from bottom
+ */
+struct sde_drm_pix_ext_v1 {
+	/*
+	 * Number of pixels ext in left, right, top and bottom direction
+	 * for all color components.
+	 */
+	int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
+	int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
+
+	/*
+	 * Number of pixels needs to be overfetched in left, right, top
+	 * and bottom directions from source image for scaling.
+	 */
+	int32_t left_ftch[SDE_MAX_PLANES];
+	int32_t right_ftch[SDE_MAX_PLANES];
+	int32_t top_ftch[SDE_MAX_PLANES];
+	int32_t btm_ftch[SDE_MAX_PLANES];
+	/*
+	 * Number of pixels needs to be repeated in left, right, top and
+	 * bottom directions for scaling.
+	 */
+	int32_t left_rpt[SDE_MAX_PLANES];
+	int32_t right_rpt[SDE_MAX_PLANES];
+	int32_t top_rpt[SDE_MAX_PLANES];
+	int32_t btm_rpt[SDE_MAX_PLANES];
+
+};
+
+/**
+ * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler
+ * @lr:            Pixel extension settings for left/right
+ * @tb:            Pixel extension settings for top/botton
+ * @init_phase_x:  Initial scaler phase values for x
+ * @phase_step_x:  Phase step values for x
+ * @init_phase_y:  Initial scaler phase values for y
+ * @phase_step_y:  Phase step values for y
+ * @horz_filter:   Horizontal filter array
+ * @vert_filter:   Vertical filter array
+ */
+struct sde_drm_scaler_v1 {
+	/*
+	 * Pix ext settings
+	 */
+	struct sde_drm_pix_ext_v1 pe;
+	/*
+	 * Phase settings
+	 */
+	int32_t init_phase_x[SDE_MAX_PLANES];
+	int32_t phase_step_x[SDE_MAX_PLANES];
+	int32_t init_phase_y[SDE_MAX_PLANES];
+	int32_t phase_step_y[SDE_MAX_PLANES];
+
+	/*
+	 * Filter type to be used for scaling in horizontal and vertical
+	 * directions
+	 */
+	uint32_t horz_filter[SDE_MAX_PLANES];
+	uint32_t vert_filter[SDE_MAX_PLANES];
+};
+
+/**
+ * struct sde_drm_de_v1 - version 1 of detail enhancer structure
+ * @enable:         Enables/disables detail enhancer
+ * @sharpen_level1: Sharpening strength for noise
+ * @sharpen_level2: Sharpening strength for context
+ * @clip:           Clip coefficient
+ * @limit:          Detail enhancer limit factor
+ * @thr_quiet:      Quite zone threshold
+ * @thr_dieout:     Die-out zone threshold
+ * @thr_low:        Linear zone left threshold
+ * @thr_high:       Linear zone right threshold
+ * @prec_shift:     Detail enhancer precision
+ * @adjust_a:       Mapping curves A coefficients
+ * @adjust_b:       Mapping curves B coefficients
+ * @adjust_c:       Mapping curves C coefficients
+ */
+struct sde_drm_de_v1 {
+	uint32_t enable;
+	int16_t sharpen_level1;
+	int16_t sharpen_level2;
+	uint16_t clip;
+	uint16_t limit;
+	uint16_t thr_quiet;
+	uint16_t thr_dieout;
+	uint16_t thr_low;
+	uint16_t thr_high;
+	uint16_t prec_shift;
+	int16_t adjust_a[SDE_MAX_DE_CURVES];
+	int16_t adjust_b[SDE_MAX_DE_CURVES];
+	int16_t adjust_c[SDE_MAX_DE_CURVES];
+};
+
+/**
+ * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
+ * @enable:            Scaler enable
+ * @dir_en:            Detail enhancer enable
+ * @pe:                Pixel extension settings
+ * @horz_decimate:     Horizontal decimation factor
+ * @vert_decimate:     Vertical decimation factor
+ * @init_phase_x:      Initial scaler phase values for x
+ * @phase_step_x:      Phase step values for x
+ * @init_phase_y:      Initial scaler phase values for y
+ * @phase_step_y:      Phase step values for y
+ * @preload_x:         Horizontal preload value
+ * @preload_y:         Vertical preload value
+ * @src_width:         Source width
+ * @src_height:        Source height
+ * @dst_width:         Destination width
+ * @dst_height:        Destination height
+ * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
+ * @uv_filter_cfg:     UV plane filter configuration
+ * @alpha_filter_cfg:  Alpha filter configuration
+ * @blend_cfg:         Selection of blend coefficients
+ * @lut_flag:          LUT configuration flags
+ * @dir_lut_idx:       2d 4x4 LUT index
+ * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
+ * @uv_cir_lut_idx:    UV circular LUT index
+ * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
+ * @uv_sep_lut_idx:    UV separable LUT index
+ * @de:                Detail enhancer settings
+*/
+struct sde_drm_scaler_v2 {
+	/*
+	 * General definitions
+	 */
+	uint32_t enable;
+	uint32_t dir_en;
+
+	/*
+	 * Pix ext settings
+	 */
+	struct sde_drm_pix_ext_v1 pe;
+
+	/*
+	 * Decimation settings
+	 */
+	uint32_t horz_decimate;
+	uint32_t vert_decimate;
+
+	/*
+	 * Phase settings
+	 */
+	int32_t init_phase_x[SDE_MAX_PLANES];
+	int32_t phase_step_x[SDE_MAX_PLANES];
+	int32_t init_phase_y[SDE_MAX_PLANES];
+	int32_t phase_step_y[SDE_MAX_PLANES];
+
+	uint32_t preload_x[SDE_MAX_PLANES];
+	uint32_t preload_y[SDE_MAX_PLANES];
+	uint32_t src_width[SDE_MAX_PLANES];
+	uint32_t src_height[SDE_MAX_PLANES];
+
+	uint32_t dst_width;
+	uint32_t dst_height;
+
+	uint32_t y_rgb_filter_cfg;
+	uint32_t uv_filter_cfg;
+	uint32_t alpha_filter_cfg;
+	uint32_t blend_cfg;
+
+	uint32_t lut_flag;
+	uint32_t dir_lut_idx;
+
+	/* for Y(RGB) and UV planes*/
+	uint32_t y_rgb_cir_lut_idx;
+	uint32_t uv_cir_lut_idx;
+	uint32_t y_rgb_sep_lut_idx;
+	uint32_t uv_sep_lut_idx;
+
+	/*
+	 * Detail enhancer settings
+	 */
+	struct sde_drm_de_v1 de;
+};
+
+
+/*
+ * Define constants for struct sde_drm_csc
+ */
+#define SDE_CSC_MATRIX_COEFF_SIZE   9
+#define SDE_CSC_CLAMP_SIZE          6
+#define SDE_CSC_BIAS_SIZE           3
+
+/**
+ * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc
+ * @ctm_coeff:          Matrix coefficients, in S31.32 format
+ * @pre_bias:           Pre-bias array values
+ * @post_bias:          Post-bias array values
+ * @pre_clamp:          Pre-clamp array values
+ * @post_clamp:         Post-clamp array values
+ */
+struct sde_drm_csc_v1 {
+	int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
+	uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
+	uint32_t post_bias[SDE_CSC_BIAS_SIZE];
+	uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
+	uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
+};
+
+/* Writeback Config version definition */
+#define SDE_DRM_WB_CFG		0x1
+
+/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
+#define SDE_DRM_WB_CFG_FLAGS_CONNECTED	(1<<0)
+
+/**
+ * struct sde_drm_wb_cfg - Writeback configuration structure
+ * @flags:		see DRM_MSM_WB_CONFIG_FLAGS
+ * @connector_id:	writeback connector identifier
+ * @count_modes:	Count of modes in modes_ptr
+ * @modes:		Pointer to struct drm_mode_modeinfo
+ */
+struct sde_drm_wb_cfg {
+	uint32_t flags;
+	uint32_t connector_id;
+	uint32_t count_modes;
+	uint64_t modes;
+};
+
+#endif /* _SDE_DRM_H_ */