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Commit 60a29414 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Sandeep Panda
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msm: mdss: update the wait logic for sending DSI commands



For video mode panels, the assumption is that the vertical
blanking region will be maximum of 4 ms and hence, we wait for
4 ms before queuing the DSI DMA commands. With the incell panels
having huge vertical blanking region and dynamic fps feature,
this assumption is no longer safe. Update the wait logic by
calculating the vertical blanking duration.

Change-Id: I69fdc182342493a54d78ae3ce5f4729e17452155
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent 59a631bc
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+16 −2
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@
#define LANE_SWAP_CTRL			0x0B0
#define LOGICAL_LANE_SWAP_CTRL		0x310

#define CEIL(x, y)		(((x) + ((y)-1)) / (y))

struct mdss_dsi_ctrl_pdata *ctrl_list[DSI_CTRL_MAX];

struct mdss_hw mdss_dsi0_hw = {
@@ -2369,14 +2371,26 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl)
static int mdss_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl)
{
	int ret = 0;
	u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0;
	struct mdss_panel_info *pinfo = &ctrl->panel_data.panel_info;

	if (ctrl->panel_mode == DSI_CMD_MODE)
		return ret;

	if (ctrl->ctrl_state & CTRL_STATE_MDP_ACTIVE) {
		mdss_dsi_wait4video_done(ctrl);
		/* delay 4 ms to skip BLLP */
		usleep_range(4000, 4000);
		v_total = mdss_panel_get_vtotal(pinfo);
		v_blank = pinfo->lcdc.v_back_porch + pinfo->lcdc.v_front_porch +
			pinfo->lcdc.v_pulse_width;
		if (pinfo->dynamic_fps && pinfo->current_fps)
			fps = pinfo->current_fps;
		else
			fps = pinfo->mipi.frame_rate;

		sleep_ms = CEIL((v_blank * 1000), (v_total * fps)) + 1;
		/* delay sleep_ms to skip BLLP */
		if (sleep_ms)
			udelay(sleep_ms * 1000);
		ret = 1;
	}