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Commit 5d536e28 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: dvo needs a P2 divisor of 4 



Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23
"FPA0/A1 P2 Clock Divide":

0 = Divide by 2
1 = Divide by 4. This bit must be set in DVO non-gang mode

So copy the current limits (which should be good for i8xx) and create
a new set for dvo encoders.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.oc.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4a33e48d

drivers/gpu/drm/i915/intel_display.c

+17 −2
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ intel_fdi_link_freq(struct drm_device *dev) 
		return 27;

}



static const intel_limit_t intel_limits_i8xx_dvo = {

static const intel_limit_t intel_limits_i8xx_dac = {

	.dot = { .min = 25000, .max = 350000 },

	.vco = { .min = 930000, .max = 1400000 },

	.n = { .min = 3, .max = 16 },
@@ -102,6 +102,19 @@ static const intel_limit_t intel_limits_i8xx_dvo = { 
		.p2_slow = 4, .p2_fast = 2 },

};



static const intel_limit_t intel_limits_i8xx_dvo = {

	.dot = { .min = 25000, .max = 350000 },

	.vco = { .min = 930000, .max = 1400000 },

	.n = { .min = 3, .max = 16 },

	.m = { .min = 96, .max = 140 },

	.m1 = { .min = 18, .max = 26 },

	.m2 = { .min = 6, .max = 16 },

	.p = { .min = 4, .max = 128 },

	.p1 = { .min = 2, .max = 33 },

	.p2 = { .dot_limit = 165000,

		.p2_slow = 4, .p2_fast = 4 },

};



static const intel_limit_t intel_limits_i8xx_lvds = {

	.dot = { .min = 25000, .max = 350000 },

	.vco = { .min = 930000, .max = 1400000 },
@@ -410,8 +423,10 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 
	} else {

		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

			limit = &intel_limits_i8xx_lvds;

		else

		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))

			limit = &intel_limits_i8xx_dvo;

		else

			limit = &intel_limits_i8xx_dac;

	}

	return limit;

}