Merge "drm/msm: add support for HDR playback control sequence" (5d3a6dd4) · Commits · e / devices / android_kernel_sony_msm8998

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c

+40 −3

Original line number	Diff line number	Diff line
		@@ -1961,6 +1961,30 @@ enable_packet_control:
		hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control);
		}

		static void sde_hdmi_clear_hdr_infoframe(struct sde_hdmi *display)
		{
		struct hdmi *hdmi;
		struct drm_connector *connector;
		u32 packet_control = 0;

		if (!display) {
		SDE_ERROR("invalid input\n");
		return;
		}

		hdmi = display->ctrl.ctrl;
		connector = display->ctrl.ctrl->connector;

		if (!hdmi \|\| !connector) {
		SDE_ERROR("invalid input\n");
		return;
		}

		packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL);
		packet_control &= ~HDMI_GEN_PKT_CTRL_CLR_MASK;
		hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control);
		}

		int sde_hdmi_set_property(struct drm_connector *connector,
		struct drm_connector_state *state,
		int property_index,
		@@ -2305,15 +2329,28 @@ int sde_hdmi_pre_kickoff(struct drm_connector *connector,
		void *display,
		struct msm_display_kickoff_params *params)
		{
		struct sde_hdmi hdmi_display = (struct sde_hdmi )display;
		struct drm_msm_ext_panel_hdr_ctrl *hdr_ctrl;
		u8 hdr_op;

		if (!connector \|\| !display \|\| !params) {
		pr_err("Invalid params\n");
		return -EINVAL;
		}

		hdr_ctrl = params->hdr_ctrl;

		hdr_op = sde_hdmi_hdr_get_ops(hdmi_display->curr_hdr_state,
		hdr_ctrl->hdr_state);

		if (hdr_op == HDR_SEND_INFO) {
		if (connector->hdr_supported)
		sde_hdmi_panel_set_hdr_infoframe(display,
		params->hdr_metadata);
		&hdr_ctrl->hdr_meta);
		} else if (hdr_op == HDR_CLEAR_INFO)
		sde_hdmi_clear_hdr_infoframe(display);

		hdmi_display->curr_hdr_state = hdr_ctrl->hdr_state;

		return 0;
		}

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -147,6 +147,7 @@ struct sde_hdmi {
		u32 hdcp22_present;
		u8 hdcp_status;
		u32 enc_lvl;
		u8 curr_hdr_state;
		bool auth_state;
		bool sink_hdcp22_support;
		bool src_hdcp22_support;
		@@ -198,6 +199,8 @@ enum hdmi_tx_scdc_access_type {
		#define HDMI_YUV420_24BPP_PCLK_TMDS_CH_RATE_RATIO 2
		#define HDMI_RGB_24BPP_PCLK_TMDS_CH_RATE_RATIO 1

		#define HDMI_GEN_PKT_CTRL_CLR_MASK 0x7

		/* Maximum pixel clock rates for hdmi tx */
		#define HDMI_DEFAULT_MAX_PCLK_RATE 148500
		#define HDMI_TX_3_MAX_PCLK_RATE 297000

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -518,12 +518,17 @@ static void _sde_hdmi_bridge_enable(struct drm_bridge *bridge)
		{
		struct sde_hdmi_bridge *sde_hdmi_bridge = to_hdmi_bridge(bridge);
		struct hdmi *hdmi = sde_hdmi_bridge->hdmi;
		struct sde_connector *c_conn = to_sde_connector(hdmi->connector);
		struct sde_hdmi display = (struct sde_hdmi )c_conn->display;

		/* need to update hdcp info here to ensure right HDCP support*/
		sde_hdmi_update_hdcp_info(hdmi->connector);

		/* start HDCP authentication */
		sde_hdmi_start_hdcp(hdmi->connector);

		/* reset HDR state */
		display->curr_hdr_state = HDR_DISABLE;
		}

		static void _sde_hdmi_bridge_disable(struct drm_bridge *bridge)

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.c

+56 −0

Original line number	Diff line number	Diff line
		@@ -68,6 +68,15 @@ static void sde_hdmi_hdcp2p2_ddc_clear_status(struct sde_hdmi *display)
		hdmi_write(hdmi, HDMI_HDCP2P2_DDC_STATUS, reg_val);
		}

		static const char *sde_hdmi_hdr_sname(enum sde_hdmi_hdr_state hdr_state)
		{
		switch (hdr_state) {
		case HDR_DISABLE: return "HDR_DISABLE";
		case HDR_ENABLE: return "HDR_ENABLE";
		default: return "HDR_INVALID_STATE";
		}
		}

		/**
		* sde_hdmi_dump_regs - utility to dump HDMI regs
		* @hdmi_display: Pointer to private display handle
		@@ -898,3 +907,50 @@ int sde_hdmi_sink_dc_support(struct drm_connector *connector,

		return dc_format;
		}

		u8 sde_hdmi_hdr_get_ops(u8 curr_state,
		u8 new_state)
		{

		/** There could be 3 valid state transitions:
		* 1. HDR_DISABLE -> HDR_ENABLE
		*
		* In this transition, we shall start sending
		* HDR metadata with metadata from the HDR clip
		*
		* 2. HDR_ENABLE -> HDR_ENABLE
		*
		* In this transition, we will keep sending
		* HDR metadata but with EOTF and metadata as 0
		*
		* 3. HDR_ENABLE -> HDR_DISABLE
		*
		* In this transition, we will stop sending
		* metadata to the sink and clear PKT_CTRL register
		* bits.
		*/

		if ((curr_state == HDR_DISABLE)
		&& (new_state == HDR_ENABLE)) {
		HDMI_UTIL_DEBUG("State changed %s ---> %s\n",
		sde_hdmi_hdr_sname(curr_state),
		sde_hdmi_hdr_sname(new_state));
		return HDR_SEND_INFO;
		} else if ((curr_state == HDR_ENABLE)
		&& (new_state == HDR_ENABLE)) {
		HDMI_UTIL_DEBUG("State changed %s ---> %s\n",
		sde_hdmi_hdr_sname(curr_state),
		sde_hdmi_hdr_sname(new_state));
		return HDR_SEND_INFO;
		} else if ((curr_state == HDR_ENABLE)
		&& (new_state == HDR_DISABLE)) {
		HDMI_UTIL_DEBUG("State changed %s ---> %s\n",
		sde_hdmi_hdr_sname(curr_state),
		sde_hdmi_hdr_sname(new_state));
		return HDR_CLEAR_INFO;
		}

		HDMI_UTIL_DEBUG("Unsupported OR no state change\n");
		return HDR_UNSUPPORTED_OP;
		}

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,17 @@ enum sde_hdmi_tx_hdcp2p2_rxstatus_intr_mask {
		RXSTATUS_REAUTH_REQ = BIT(14),
		};

		enum sde_hdmi_hdr_state {
		HDR_DISABLE,
		HDR_ENABLE
		};

		enum sde_hdmi_hdr_op {
		HDR_UNSUPPORTED_OP,
		HDR_SEND_INFO,
		HDR_CLEAR_INFO
		};

		struct sde_hdmi_tx_hdcp2p2_ddc_data {
		enum sde_hdmi_tx_hdcp2p2_rxstatus_intr_mask intr_mask;
		u32 timeout_ms;
		@@ -170,4 +181,6 @@ bool sde_hdmi_validate_pixclk(struct drm_connector *connector,
		unsigned long pclk);
		int sde_hdmi_sink_dc_support(struct drm_connector *connector,
		struct drm_display_mode *mode);
		u8 sde_hdmi_hdr_get_ops(u8 curr_state,
		u8 new_state);
		#endif /* _SDE_HDMI_UTIL_H_ */