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Commit 5ccce180 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: also reset the media engine on gen4/5 



... we actually use it.

Unfortunately we can't reset both at the same time without also
resetting the display unit, so do render and media separately.

Also replace magic constants with proper #defines.

Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d4b8bb2a

drivers/gpu/drm/i915/i915_drv.c

+25 −3
Original line number Original line Diff line number Diff line
@@ -712,6 +712,7 @@ static int i965_reset_complete(struct drm_device *dev) 




static int i965_do_reset(struct drm_device *dev)

static int i965_do_reset(struct drm_device *dev)

{

{

	int ret;

	u8 gdrst;

	u8 gdrst;





	/*

	/*
@@ -721,7 +722,17 @@ static int i965_do_reset(struct drm_device *dev) 
	 */

	 */

	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);

	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);

	pci_write_config_byte(dev->pdev, I965_GDRST,

	pci_write_config_byte(dev->pdev, I965_GDRST,

			      gdrst | GRDOM_RENDER | 0x1);

			      gdrst | GRDOM_RENDER |

			      GRDOM_RESET_ENABLE);

	ret =  wait_for(i965_reset_complete(dev), 500);

	if (ret)

		return ret;



	/* We can't reset render&media without also resetting display ... */

	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);

	pci_write_config_byte(dev->pdev, I965_GDRST,

			      gdrst | GRDOM_MEDIA |

			      GRDOM_RESET_ENABLE);





	return wait_for(i965_reset_complete(dev), 500);

	return wait_for(i965_reset_complete(dev), 500);

}

}
@@ -729,9 +740,20 @@ static int i965_do_reset(struct drm_device *dev) 
static int ironlake_do_reset(struct drm_device *dev)

static int ironlake_do_reset(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);

	u32 gdrst;

	int ret;



	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);

	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,

		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);

	ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);

	if (ret)

		return ret;



	/* We can't reset render&media without also resetting display ... */

	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);

	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,

	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,

		   gdrst | GRDOM_RENDER | 0x1);

		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);

	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);

	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);

}

}

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -82,6 +82,7 @@ 
#define  GRDOM_FULL	(0<<2)

#define  GRDOM_FULL	(0<<2)

#define  GRDOM_RENDER	(1<<2)

#define  GRDOM_RENDER	(1<<2)

#define  GRDOM_MEDIA	(3<<2)

#define  GRDOM_MEDIA	(3<<2)

#define  GRDOM_RESET_ENABLE (1<<0)





#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */

#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */

#define   GEN6_MBC_SNPCR_SHIFT	21

#define   GEN6_MBC_SNPCR_SHIFT	21