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Commit 5c2a834f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: support configurable wr halt size for PCIe"

parents 2db8e297 c25e50ab

Documentation/devicetree/bindings/pci/msm_pcie.txt

+3 −0
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ Optional Properties: 
    and assign for each endpoint.

  - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become

    stable after power on, before de-assert the PERST to the endpoint.

  - qcom,wr-halt-size: With base 2, this exponent determines the size of the

    data that PCIe core will halt on for each write transaction.

  - qcom,cpl-timeout: Completion timeout value. This value specifies the time range

    which the root complex will send out a completion packet if there is no response

    from the endpoint.
@@ -270,6 +272,7 @@ Example: 
		qcom,smmu-exist;

		qcom,smmu-sid-base = <0x1480>;

		qcom,ep-latency = <100>;

		qcom,wr-halt-size = <0xa>; /* 1KB */

		qcom,cpl-timeout = <0x2>;



		iommus = <&anoc0_smmu>;

drivers/pci/host/pci-msm.c

+28 −2
Original line number Diff line number Diff line
@@ -619,6 +619,7 @@ struct msm_pcie_dev_t { 
	bool				 ext_ref_clk;

	bool				common_phy;

	uint32_t			   ep_latency;

	uint32_t			wr_halt_size;

	uint32_t			cpl_timeout;

	uint32_t			current_bdf;

	short				current_short_bdf;
@@ -1976,6 +1977,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->common_phy);

	PCIE_DBG_FS(dev, "ep_latency: %dms\n",

		dev->ep_latency);

	PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",

		dev->wr_halt_size);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",

		dev->cpl_timeout);

	PCIE_DBG_FS(dev, "current_bdf: 0x%x\n",
@@ -4495,8 +4498,19 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 


	if (dev->use_msi) {

		PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx);

		msm_pcie_write_mask(dev->parf +

			PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, 0, BIT(31));

		val = dev->wr_halt_size ? dev->wr_halt_size :

			readl_relaxed(dev->parf +

				PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);



		msm_pcie_write_reg(dev->parf,

			PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,

			BIT(31) | val);



		PCIE_DBG(dev,

			"RC%d: PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT: 0x%x.\n",

			dev->rc_idx,

			readl_relaxed(dev->parf +

				PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT));

	}



	mutex_lock(&com_phy_lock);
@@ -6068,6 +6082,18 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].ep_latency);



	msm_pcie_dev[rc_idx].wr_halt_size = 0;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,wr-halt-size",

				&msm_pcie_dev[rc_idx].wr_halt_size);

	if (ret)

		PCIE_DBG(&msm_pcie_dev[rc_idx],

			"RC%d: wr-halt-size not specified in dt. Use default value.\n",

			rc_idx);

	else

		PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: wr-halt-size: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].wr_halt_size);



	msm_pcie_dev[rc_idx].cpl_timeout = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,cpl-timeout",