Loading Documentation/devicetree/bindings/fb/mdss-dp.txt +2 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ Optional properties: device node. Refer to pinctrl-bindings.txt - qcom,logical2physical-lane-map: An array that specifies the DP logical to physical lane map setting. - qcom,phy-register-offset: An integer specifying the offset value of DP PHY register space. - qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. Example: mdss_dp_ctrl: qcom,dp_ctrl@c990000 { Loading Loading @@ -89,6 +90,7 @@ Example: qcom,aux-cfg-settings = [00 13 00 10 0a 26 0a 03 8b 03]; qcom,logical2physical-lane-map = [02 03 01 00]; qcom,phy-register-offset = <0x4>; qcom,max-pclk-frequency-khz = <593470>; qcom,core-supply-entries { #address-cells = <1>; Loading drivers/video/fbdev/msm/mdss_dp.c +6 −2 Original line number Diff line number Diff line Loading @@ -132,7 +132,7 @@ static int mdss_dp_is_clk_prefix(const char *clk_prefix, const char *clk_name) static int mdss_dp_parse_prop(struct platform_device *pdev, struct mdss_dp_drv_pdata *dp_drv) { int len = 0, i = 0; int len = 0, i = 0, rc = 0; const char *data; data = of_get_property(pdev->dev.of_node, Loading Loading @@ -160,6 +160,11 @@ static int mdss_dp_parse_prop(struct platform_device *pdev, dp_drv->l_map[i] = data[i]; } rc = of_property_read_u32(pdev->dev.of_node, "qcom,max-pclk-frequency-khz", &dp_drv->max_pclk_khz); if (rc) dp_drv->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; return 0; } Loading Loading @@ -1683,7 +1688,6 @@ static int mdss_dp_edid_init(struct mdss_panel_data *pdata) dp_drv = container_of(pdata, struct mdss_dp_drv_pdata, panel_data); dp_drv->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; edid_init_data.kobj = dp_drv->kobj; edid_init_data.max_pclk_khz = dp_drv->max_pclk_khz; Loading Loading
Documentation/devicetree/bindings/fb/mdss-dp.txt +2 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ Optional properties: device node. Refer to pinctrl-bindings.txt - qcom,logical2physical-lane-map: An array that specifies the DP logical to physical lane map setting. - qcom,phy-register-offset: An integer specifying the offset value of DP PHY register space. - qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. Example: mdss_dp_ctrl: qcom,dp_ctrl@c990000 { Loading Loading @@ -89,6 +90,7 @@ Example: qcom,aux-cfg-settings = [00 13 00 10 0a 26 0a 03 8b 03]; qcom,logical2physical-lane-map = [02 03 01 00]; qcom,phy-register-offset = <0x4>; qcom,max-pclk-frequency-khz = <593470>; qcom,core-supply-entries { #address-cells = <1>; Loading
drivers/video/fbdev/msm/mdss_dp.c +6 −2 Original line number Diff line number Diff line Loading @@ -132,7 +132,7 @@ static int mdss_dp_is_clk_prefix(const char *clk_prefix, const char *clk_name) static int mdss_dp_parse_prop(struct platform_device *pdev, struct mdss_dp_drv_pdata *dp_drv) { int len = 0, i = 0; int len = 0, i = 0, rc = 0; const char *data; data = of_get_property(pdev->dev.of_node, Loading Loading @@ -160,6 +160,11 @@ static int mdss_dp_parse_prop(struct platform_device *pdev, dp_drv->l_map[i] = data[i]; } rc = of_property_read_u32(pdev->dev.of_node, "qcom,max-pclk-frequency-khz", &dp_drv->max_pclk_khz); if (rc) dp_drv->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; return 0; } Loading Loading @@ -1683,7 +1688,6 @@ static int mdss_dp_edid_init(struct mdss_panel_data *pdata) dp_drv = container_of(pdata, struct mdss_dp_drv_pdata, panel_data); dp_drv->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; edid_init_data.kobj = dp_drv->kobj; edid_init_data.max_pclk_khz = dp_drv->max_pclk_khz; Loading