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Commit 5ab134ad authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: dt: add L2 cache controller 



Add L2 cache controller binding into DT for Tegra.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d534b5d4

arch/arm/boot/dts/tegra20.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -4,6 +4,15 @@ 
	compatible = "nvidia,tegra20";

	interrupt-parent = <&intc>;



	cache-controller@50043000 {

		compatible = "arm,pl310-cache";

		reg = <0x50043000 0x1000>;

		arm,data-latency = <5 5 2>;

		arm,tag-latency = <4 4 2>;

		cache-unified;

		cache-level = <2>;

	};



	intc: interrupt-controller {

		compatible = "arm,cortex-a9-gic";

		reg = <0x50041000 0x1000

arch/arm/boot/dts/tegra30.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -4,6 +4,15 @@ 
	compatible = "nvidia,tegra30";

	interrupt-parent = <&intc>;



	cache-controller@50043000 {

		compatible = "arm,pl310-cache";

		reg = <0x50043000 0x1000>;

		arm,data-latency = <6 6 2>;

		arm,tag-latency = <5 5 2>;

		cache-unified;

		cache-level = <2>;

	};



	intc: interrupt-controller {

		compatible = "arm,cortex-a9-gic";

		reg = <0x50041000 0x1000