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Commit 58f02db4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, cacheinfo: Enable L3 CID only on AMD
  x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1
  x86, cpu: Print AMD virtualization features in /proc/cpuinfo
  x86, cacheinfo: Calculate L3 indices
  x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches
  x86, cacheinfo: Fix disabling of L3 cache indices
  intel-agp: Switch to wbinvd_on_all_cpus
  x86, lib: Add wbinvd smp helpers
parents 43a834d8 cb19060a

arch/x86/include/asm/cpufeature.h

+4 −0
Original line number Diff line number Diff line
@@ -168,6 +168,10 @@ 
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */

#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */

#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */

#define X86_FEATURE_NPT		(8*32+5)  /* AMD Nested Page Table support */

#define X86_FEATURE_LBRV	(8*32+6)  /* AMD LBR Virtualization support */

#define X86_FEATURE_SVML	(8*32+7)  /* "svm_lock" AMD SVM locking MSR */

#define X86_FEATURE_NRIPS	(8*32+8)  /* "nrip_save" AMD SVM next_rip save */



#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

arch/x86/include/asm/smp.h

+9 −0
Original line number Diff line number Diff line
@@ -135,6 +135,8 @@ int native_cpu_disable(void); 
void native_cpu_die(unsigned int cpu);

void native_play_dead(void);

void play_dead_common(void);

void wbinvd_on_cpu(int cpu);

int wbinvd_on_all_cpus(void);



void native_send_call_func_ipi(const struct cpumask *mask);

void native_send_call_func_single_ipi(int cpu);
@@ -147,6 +149,13 @@ static inline int num_booting_cpus(void) 
{

	return cpumask_weight(cpu_callout_mask);

}

#else /* !CONFIG_SMP */

#define wbinvd_on_cpu(cpu)     wbinvd()

static inline int wbinvd_on_all_cpus(void)

{

	wbinvd();

	return 0;

}

#endif /* CONFIG_SMP */



extern unsigned disabled_cpus __cpuinitdata;

arch/x86/kernel/cpu/addon_cpuid_features.c

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,10 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) 
	static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {

		{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },

		{ X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 },

		{ X86_FEATURE_NPT,   CR_EDX, 0, 0x8000000a },

		{ X86_FEATURE_LBRV,  CR_EDX, 1, 0x8000000a },

		{ X86_FEATURE_SVML,  CR_EDX, 2, 0x8000000a },

		{ X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a },

		{ 0, 0, 0, 0 }

	};

arch/x86/kernel/cpu/intel_cacheinfo.c

+156 −94
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <asm/processor.h>

#include <linux/smp.h>

#include <asm/k8.h>

#include <asm/smp.h>



#define LVL_1_INST	1

#define LVL_1_DATA	2
@@ -152,7 +153,8 @@ struct _cpuid4_info { 
	union _cpuid4_leaf_ebx ebx;

	union _cpuid4_leaf_ecx ecx;

	unsigned long size;

	unsigned long can_disable;

	bool can_disable;

	unsigned int l3_indices;

	DECLARE_BITMAP(shared_cpu_map, NR_CPUS);

};
@@ -162,7 +164,8 @@ struct _cpuid4_info_regs { 
	union _cpuid4_leaf_ebx ebx;

	union _cpuid4_leaf_ecx ecx;

	unsigned long size;

	unsigned long can_disable;

	bool can_disable;

	unsigned int l3_indices;

};



unsigned short			num_cache_leaves;
@@ -292,6 +295,36 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, 
		(ebx->split.ways_of_associativity + 1) - 1;

}



struct _cache_attr {

	struct attribute attr;

	ssize_t (*show)(struct _cpuid4_info *, char *);

	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);

};



#ifdef CONFIG_CPU_SUP_AMD

static unsigned int __cpuinit amd_calc_l3_indices(void)

{

	/*

	 * We're called over smp_call_function_single() and therefore

	 * are on the correct cpu.

	 */

	int cpu = smp_processor_id();

	int node = cpu_to_node(cpu);

	struct pci_dev *dev = node_to_k8_nb_misc(node);

	unsigned int sc0, sc1, sc2, sc3;

	u32 val = 0;



	pci_read_config_dword(dev, 0x1C4, &val);



	/* calculate subcache sizes */

	sc0 = !(val & BIT(0));

	sc1 = !(val & BIT(4));

	sc2 = !(val & BIT(8))  + !(val & BIT(9));

	sc3 = !(val & BIT(12)) + !(val & BIT(13));



	return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;

}



static void __cpuinit

amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)

{
@@ -301,13 +334,104 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf) 
	if (boot_cpu_data.x86 == 0x11)

		return;



	/* see erratum #382 */

	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))

	/* see errata #382 and #388 */

	if ((boot_cpu_data.x86 == 0x10) &&

	    ((boot_cpu_data.x86_model < 0x8) ||

	     (boot_cpu_data.x86_mask  < 0x1)))

		return;



	this_leaf->can_disable = 1;

	this_leaf->can_disable = true;

	this_leaf->l3_indices  = amd_calc_l3_indices();

}



static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,

				  unsigned int index)

{

	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));

	int node = amd_get_nb_id(cpu);

	struct pci_dev *dev = node_to_k8_nb_misc(node);

	unsigned int reg = 0;



	if (!this_leaf->can_disable)

		return -EINVAL;



	if (!dev)

		return -EINVAL;



	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);

	return sprintf(buf, "0x%08x\n", reg);

}



#define SHOW_CACHE_DISABLE(index)					\

static ssize_t								\

show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)	\

{									\

	return show_cache_disable(this_leaf, buf, index);		\

}

SHOW_CACHE_DISABLE(0)

SHOW_CACHE_DISABLE(1)



static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,

	const char *buf, size_t count, unsigned int index)

{

	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));

	int node = amd_get_nb_id(cpu);

	struct pci_dev *dev = node_to_k8_nb_misc(node);

	unsigned long val = 0;



#define SUBCACHE_MASK	(3UL << 20)

#define SUBCACHE_INDEX	0xfff



	if (!this_leaf->can_disable)

		return -EINVAL;



	if (!capable(CAP_SYS_ADMIN))

		return -EPERM;



	if (!dev)

		return -EINVAL;



	if (strict_strtoul(buf, 10, &val) < 0)

		return -EINVAL;



	/* do not allow writes outside of allowed bits */

	if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||

	    ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))

		return -EINVAL;



	val |= BIT(30);

	pci_write_config_dword(dev, 0x1BC + index * 4, val);

	/*

	 * We need to WBINVD on a core on the node containing the L3 cache which

	 * indices we disable therefore a simple wbinvd() is not sufficient.

	 */

	wbinvd_on_cpu(cpu);

	pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));

	return count;

}



#define STORE_CACHE_DISABLE(index)					\

static ssize_t								\

store_cache_disable_##index(struct _cpuid4_info *this_leaf,		\

			    const char *buf, size_t count)		\

{									\

	return store_cache_disable(this_leaf, buf, count, index);	\

}

STORE_CACHE_DISABLE(0)

STORE_CACHE_DISABLE(1)



static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,

		show_cache_disable_0, store_cache_disable_0);

static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,

		show_cache_disable_1, store_cache_disable_1);



#else	/* CONFIG_CPU_SUP_AMD */

static void __cpuinit

amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)

{

};

#endif /* CONFIG_CPU_SUP_AMD */



static int

__cpuinit cpuid4_cache_lookup_regs(int index,

				   struct _cpuid4_info_regs *this_leaf)
@@ -713,82 +837,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) 
#define to_object(k)	container_of(k, struct _index_kobject, kobj)

#define to_attr(a)	container_of(a, struct _cache_attr, attr)



static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,

				  unsigned int index)

{

	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));

	int node = cpu_to_node(cpu);

	struct pci_dev *dev = node_to_k8_nb_misc(node);

	unsigned int reg = 0;



	if (!this_leaf->can_disable)

		return -EINVAL;



	if (!dev)

		return -EINVAL;



	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);

	return sprintf(buf, "%x\n", reg);

}



#define SHOW_CACHE_DISABLE(index)					\

static ssize_t								\

show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)  	\

{									\

	return show_cache_disable(this_leaf, buf, index);		\

}

SHOW_CACHE_DISABLE(0)

SHOW_CACHE_DISABLE(1)



static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,

	const char *buf, size_t count, unsigned int index)

{

	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));

	int node = cpu_to_node(cpu);

	struct pci_dev *dev = node_to_k8_nb_misc(node);

	unsigned long val = 0;

	unsigned int scrubber = 0;



	if (!this_leaf->can_disable)

		return -EINVAL;



	if (!capable(CAP_SYS_ADMIN))

		return -EPERM;



	if (!dev)

		return -EINVAL;



	if (strict_strtoul(buf, 10, &val) < 0)

		return -EINVAL;



	val |= 0xc0000000;



	pci_read_config_dword(dev, 0x58, &scrubber);

	scrubber &= ~0x1f000000;

	pci_write_config_dword(dev, 0x58, scrubber);



	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);

	wbinvd();

	pci_write_config_dword(dev, 0x1BC + index * 4, val);

	return count;

}



#define STORE_CACHE_DISABLE(index)					\

static ssize_t								\

store_cache_disable_##index(struct _cpuid4_info *this_leaf,	     	\

			    const char *buf, size_t count)		\

{									\

	return store_cache_disable(this_leaf, buf, count, index);	\

}

STORE_CACHE_DISABLE(0)

STORE_CACHE_DISABLE(1)



struct _cache_attr {

	struct attribute attr;

	ssize_t (*show)(struct _cpuid4_info *, char *);

	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);

};



#define define_one_ro(_name) \

static struct _cache_attr _name = \

	__ATTR(_name, 0444, show_##_name, NULL)
@@ -803,23 +851,28 @@ define_one_ro(size); 
define_one_ro(shared_cpu_map);

define_one_ro(shared_cpu_list);



static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,

		show_cache_disable_0, store_cache_disable_0);

static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,

		show_cache_disable_1, store_cache_disable_1);

#define DEFAULT_SYSFS_CACHE_ATTRS	\

	&type.attr,			\

	&level.attr,			\

	&coherency_line_size.attr,	\

	&physical_line_partition.attr,	\

	&ways_of_associativity.attr,	\

	&number_of_sets.attr,		\

	&size.attr,			\

	&shared_cpu_map.attr,		\

	&shared_cpu_list.attr



static struct attribute *default_attrs[] = {

	&type.attr,

	&level.attr,

	&coherency_line_size.attr,

	&physical_line_partition.attr,

	&ways_of_associativity.attr,

	&number_of_sets.attr,

	&size.attr,

	&shared_cpu_map.attr,

	&shared_cpu_list.attr,

	DEFAULT_SYSFS_CACHE_ATTRS,

	NULL

};



static struct attribute *default_l3_attrs[] = {

	DEFAULT_SYSFS_CACHE_ATTRS,

#ifdef CONFIG_CPU_SUP_AMD

	&cache_disable_0.attr,

	&cache_disable_1.attr,

#endif

	NULL

};
@@ -910,6 +963,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) 
	unsigned int cpu = sys_dev->id;

	unsigned long i, j;

	struct _index_kobject *this_object;

	struct _cpuid4_info   *this_leaf;

	int retval;



	retval = cpuid4_cache_sysfs_init(cpu);
@@ -928,6 +982,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) 
		this_object = INDEX_KOBJECT_PTR(cpu, i);

		this_object->cpu = cpu;

		this_object->index = i;



		this_leaf = CPUID4_INFO_IDX(cpu, i);



		if (this_leaf->can_disable)

			ktype_cache.default_attrs = default_l3_attrs;

		else

			ktype_cache.default_attrs = default_attrs;



		retval = kobject_init_and_add(&(this_object->kobj),

					      &ktype_cache,

					      per_cpu(ici_cache_kobject, cpu),

arch/x86/lib/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c 


clean-files := inat-tables.c



obj-$(CONFIG_SMP) += msr-smp.o

obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o



lib-y := delay.o

lib-y += thunk_$(BITS).o