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Commit 58ce0d45 authored by Govind Singh's avatar Govind Singh Committed by Gerrit - the friendly Code Review server
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ath10k: Remove bus structures from ath10k struct 



ath10k struct is bus opaque structure.
Remove bus structures from ath10k struct to make it
bus independent.

Change-Id: Ifb82e1fc4525c535e8a19f95bd4da006294be203
Signed-off-by: default avatarGovind Singh <govinds@codeaurora.org>
parent 81eef00c

drivers/net/wireless/ath/ath10k/ce.c

+149 −79
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 


/*

 * Support for Copy Engine hardware, which is mainly used for

 * communication between Host and Target over a PCIe interconnect.

 * communication between Host and Target over a PCIe/SNOC/AHB interconnect.

 */



/*
@@ -32,7 +32,7 @@ 
 * Each ring consists of a number of descriptors which specify

 * an address, length, and meta-data.

 *

 * Typically, one side of the PCIe interconnect (Host or Target)

 * Typically, one side of the PCIe/AHB/SNOC interconnect (Host or Target)

 * controls one ring and the other side controls the other ring.

 * The source side chooses when to initiate a transfer and it

 * chooses what to send (buffer address, length). The destination
@@ -62,70 +62,95 @@ static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, 
						       u32 ce_ctrl_addr,

						       unsigned int n)

{

	ar->bus_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

}



static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,

						      u32 ce_ctrl_addr)

{

	return ar->bus_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  DST_WR_INDEX_ADDRESS);

}



static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,

						      u32 ce_ctrl_addr,

						      unsigned int n)

{

	ar->bus_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

}



static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ar->bus_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  SR_WR_INDEX_ADDRESS);

}



static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	return ar->bus_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  CURRENT_SRRI_ADDRESS);

}



static inline void ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar,

							     u32 ce_ctrl_addr,

							     unsigned int n)

{

	ar->bus_write32(ar, shadow_sr_wr_ind_addr(ar, ce_ctrl_addr), n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, shadow_sr_wr_ind_addr(ar,

							      ce_ctrl_addr), n);

}



static inline void ath10k_ce_shadow_dest_ring_write_index_set(struct ath10k *ar,

							      u32 ce_ctrl_addr,

							      unsigned int n)

{

	ar->bus_write32(ar, shadow_dst_wr_ind_addr(ar, ce_ctrl_addr), n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, shadow_dst_wr_ind_addr(ar,

							       ce_ctrl_addr),

							       n);

}



static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,

						    u32 ce_ctrl_addr,

						    unsigned int addr)

{

	ar->bus_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

}



static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	ar->bus_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

}



static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	u32 ctrl1_addr = ar->bus_read32((ar),

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 ctrl1_addr = ar_opaque->bus_ops->read32((ar),

					   (ce_ctrl_addr) + CE_CTRL1_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr &  ~CE_CTRL1_DMAX_LENGTH_MASK) |

			   CE_CTRL1_DMAX_LENGTH_SET(n));

}
@@ -134,9 +159,11 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, 
						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 ctrl1_addr = ar->bus_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

						    CE_CTRL1_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));

}
@@ -145,9 +172,11 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 
						     u32 ce_ctrl_addr,

						     unsigned int n)

{

	u32 ctrl1_addr = ar->bus_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

						    CE_CTRL1_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));

}
@@ -155,30 +184,40 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 
static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ar->bus_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  CURRENT_DRRI_ADDRESS);

}



static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,

						     u32 ce_ctrl_addr,

						     u32 addr)

{

	ar->bus_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

}



static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,

						u32 ce_ctrl_addr,

						unsigned int n)

{

	ar->bus_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

}



static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,

						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar->bus_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_HIGH_MASK) |

			   SRC_WATERMARK_HIGH_SET(n));

}
@@ -187,9 +226,11 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, 
						  u32 ce_ctrl_addr,

						  unsigned int n)

{

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_LOW_MASK) |

			   SRC_WATERMARK_LOW_SET(n));

}
@@ -198,9 +239,11 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, 
						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_HIGH_MASK) |

			   DST_WATERMARK_HIGH_SET(n));

}
@@ -209,9 +252,11 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_LOW_MASK) |

			   DST_WATERMARK_LOW_SET(n));

}
@@ -219,50 +264,55 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ar->bus_read32(ar,

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);

}



static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ar->bus_read32(ar,

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);

}



static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ar->bus_read32(ar,

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~CE_WATERMARK_MASK);

}



static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,

					       u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ar->bus_read32(ar,

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr | CE_ERROR_MASK);

}



static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,

						u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ar->bus_read32(ar,

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);



	ar->bus_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr & ~CE_ERROR_MASK);

}
@@ -270,7 +320,9 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, 
						     u32 ce_ctrl_addr,

						     unsigned int mask)

{

	ar->bus_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

}



u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
@@ -422,10 +474,11 @@ exit: 
void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_ring *src_ring = pipe->src_ring;

	u32 ctrl_addr = pipe->ctrl_addr;



	lockdep_assert_held(&ar->ce_lock);

	lockdep_assert_held(&ar_opaque->ce_lock);



	/*

	 * This function must be called only if there is an incomplete
@@ -453,12 +506,13 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 
		   unsigned int flags)

{

	struct ath10k *ar = ce_state->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int ret;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);

	ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,

				    buffer, nbytes, transfer_id, flags);

	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -466,13 +520,14 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 
int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int delta;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);

	delta = CE_RING_DELTA(pipe->src_ring->nentries_mask,

			      pipe->src_ring->write_index,

			      pipe->src_ring->sw_index - 1);

	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return delta;

}
@@ -480,12 +535,13 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) 
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_ring *dest_ring = pipe->dest_ring;

	unsigned int nentries_mask = dest_ring->nentries_mask;

	unsigned int write_index = dest_ring->write_index;

	unsigned int sw_index = dest_ring->sw_index;



	lockdep_assert_held(&ar->ce_lock);

	lockdep_assert_held(&ar_opaque->ce_lock);



	return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);

}
@@ -494,6 +550,7 @@ int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, 
			    dma_addr_t paddr)

{

	struct ath10k *ar = pipe->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_ring *dest_ring = pipe->dest_ring;

	unsigned int nentries_mask = dest_ring->nentries_mask;

	unsigned int write_index = dest_ring->write_index;
@@ -502,7 +559,7 @@ int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, 
	struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);

	u32 ctrl_addr = pipe->ctrl_addr;



	lockdep_assert_held(&ar->ce_lock);

	lockdep_assert_held(&ar_opaque->ce_lock);



	if ((pipe->id != 5) &&

	    CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0)
@@ -542,11 +599,12 @@ int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, 
			  dma_addr_t paddr)

{

	struct ath10k *ar = pipe->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int ret;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);

	ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr);

	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -609,13 +667,14 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 
				  unsigned int *nbytesp)

{

	struct ath10k *ar = ce_state->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int ret;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);

	ret = ath10k_ce_completed_recv_next_nolock(ce_state,

						   per_transfer_contextp,

						   nbytesp);

	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -630,6 +689,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
	unsigned int write_index;

	int ret;

	struct ath10k *ar;

	struct bus_opaque *ar_opaque;



	dest_ring = ce_state->dest_ring;
@@ -637,8 +697,9 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
		return -EIO;



	ar = ce_state->ar;

	ar_opaque = ath10k_bus_priv(ar);



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);



	nentries_mask = dest_ring->nentries_mask;

	sw_index = dest_ring->sw_index;
@@ -666,7 +727,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
		ret = -EIO;

	}



	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -734,6 +795,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
	unsigned int write_index;

	int ret;

	struct ath10k *ar;

	struct bus_opaque *ar_opaque;



	src_ring = ce_state->src_ring;
@@ -741,8 +803,9 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
		return -EIO;



	ar = ce_state->ar;

	ar_opaque = ath10k_bus_priv(ar);



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);



	nentries_mask = src_ring->nentries_mask;

	sw_index = src_ring->sw_index;
@@ -773,7 +836,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
		ret = -EIO;

	}



	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -782,12 +845,13 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 
				  void **per_transfer_contextp)

{

	struct ath10k *ar = ce_state->ar;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int ret;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);

	ret = ath10k_ce_completed_send_next_nolock(ce_state,

						   per_transfer_contextp);

	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	return ret;

}
@@ -800,17 +864,17 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 
 */

void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)

{

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	u32 ctrl_addr = ce_state->ctrl_addr;



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);



	/* Clear the copy-complete interrupts that will be handled here. */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,

					  HOST_IS_COPY_COMPLETE_MASK);



	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);



	if (ce_state->recv_cb)

		ce_state->recv_cb(ce_state);
@@ -818,7 +882,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	if (ce_state->send_cb)

		ce_state->send_cb(ce_state);



	spin_lock_bh(&ar->ce_lock);

	spin_lock_bh(&ar_opaque->ce_lock);



	/*

	 * Misc CE interrupts are not being handled, but still need
@@ -826,7 +890,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	 */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);



	spin_unlock_bh(&ar->ce_lock);

	spin_unlock_bh(&ar_opaque->ce_lock);

}



/*
@@ -840,11 +904,12 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar) 
	int ce_id;

	u32 intr_summary;

	struct ath10k_ce_pipe *ce_state;

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	if (ar->target_version == ATH10K_HW_WCN3990)

		intr_summary = 0xFFF;

	else

		intr_summary = CE_INTERRUPT_SUMMARY(ar);

		intr_summary = CE_INTERRUPT_SUMMARY(ar, ar_opaque);



	for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) {

		if (intr_summary & (1 << ce_id))
@@ -853,7 +918,7 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar) 
			/* no intr pending on this CE */

			continue;



		ce_state = ((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

		ce_state = &ar_opaque->ce_states[ce_id];

		if (ce_state->send_cb || ce_state->recv_cb)

			ath10k_ce_per_engine_service(ar, ce_id);

	}
@@ -899,42 +964,47 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar) 


void ath10k_ce_enable_interrupts(struct ath10k *ar)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	int ce_id;

	struct ath10k_ce_pipe *ce_state;



	/* Skip the last copy engine, CE7 the diagnostic window, as that

	 * uses polling and isn't initialized for interrupts.

	 */

	for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++)

		ath10k_ce_per_engine_handler_adjust(

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id));

	for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++) {

		ce_state  = &ar_opaque->ce_states[ce_id];

		ath10k_ce_per_engine_handler_adjust(ce_state);

	}

}



void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)

{

	u32 offset;

	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	offset = HOST_IE_ADDRESS + ctrl_addr;

	ar->bus_write32(ar, offset, 1);

	ar->bus_read32(ar, offset);

	ar_opaque->bus_ops->write32(ar, offset, 1);

	ar_opaque->bus_ops->read32(ar, offset);

}



void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)

{

	u32 offset;

	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	offset = HOST_IE_ADDRESS + ctrl_addr;

	ar->bus_write32(ar, offset, 0);

	ar->bus_read32(ar, offset);

	ar_opaque->bus_ops->write32(ar, offset, 0);

	ar_opaque->bus_ops->read32(ar, offset);

}



static int ath10k_ce_init_src_ring(struct ath10k *ar,

				   unsigned int ce_id,

				   const struct ce_attr *attr)

{

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	struct ath10k_ce_ring *src_ring = ce_state->src_ring;

	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
@@ -970,8 +1040,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar, 
				    unsigned int ce_id,

				    const struct ce_attr *attr)

{

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;

	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
@@ -1178,8 +1248,8 @@ void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id) 
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,

			 const struct ce_attr *attr)

{

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	int ret;



	/*
@@ -1235,8 +1305,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 


void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)

{

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];



	if (ce_state->src_ring) {

		kfree(ce_state->src_ring->shadow_base_unaligned);

drivers/net/wireless/ath/ath10k/ce.h

+20 −2
Original line number Diff line number Diff line
@@ -201,6 +201,24 @@ struct ce_attr; 
u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr);

u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr);



struct ath10k_bus_ops {

	u32 (*read32)(struct ath10k *ar, u32 offset);

	void (*write32)(struct ath10k *ar, u32 offset, u32 value);

	int (*get_num_banks)(struct ath10k *ar);

};



static inline struct bus_opaque *ath10k_bus_priv(struct ath10k *ar)

{

	return (struct bus_opaque *)ar->drv_priv;

}



struct bus_opaque {

	/* protects CE info */

	spinlock_t ce_lock;

	const struct ath10k_bus_ops *bus_ops;

	struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];

};



/*==================Send====================*/



/* ath10k_ce_send flags */
@@ -692,9 +710,9 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 
		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)

#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS			0x0000



#define CE_INTERRUPT_SUMMARY(ar) \

#define CE_INTERRUPT_SUMMARY(ar, ar_opaque) \

	CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \

		ar->bus_read32((ar), CE_WRAPPER_BASE_ADDRESS + \

		ar_opaque->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS + \

		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))



#endif /* _CE_H_ */

drivers/net/wireless/ath/ath10k/core.h

+0 −4
Original line number Diff line number Diff line
@@ -923,10 +923,6 @@ struct ath10k { 
	struct net_device napi_dev;

	struct napi_struct napi;



	void (*bus_write32)(void *ar, u32 offset, u32 value);

	u32 (*bus_read32)(void *ar, u32 offset);

	spinlock_t ce_lock; /* lock for CE access */

	void *ce_states;

	struct fw_flag *fw_flags;

	/* set for bmi chip sets */

	bool is_bmi;

drivers/net/wireless/ath/ath10k/hif.h

+2 −2
Original line number Diff line number Diff line
@@ -74,9 +74,9 @@ struct ath10k_hif_ops { 


	u16 (*get_free_queue_number)(struct ath10k *ar, u8 pipe_id);



	u32 (*read32)(void *ar, u32 address);

	u32 (*read32)(struct ath10k *ar, u32 address);



	void (*write32)(void *ar, u32 address, u32 value);

	void (*write32)(struct ath10k *ar, u32 address, u32 value);



	/* Power up the device and enter BMI transfer mode for FW download */

	int (*power_up)(struct ath10k *ar);

drivers/net/wireless/ath/ath10k/pci.c

+21 −27

File changed.

Preview size limit exceeded, changes collapsed.