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Commit 5832401c authored by Udaya Mallavarapu's avatar Udaya Mallavarapu
Browse files

ARM: dts: msm: add TSPP support for msmcobalt 



Add TSPP device tree node to support TSPP on msmcobalt,
together with the required pinctrl definitions.

CRs-Fixed: 1057562
Change-Id: Id4bf6b6221a18231d7f8e6e592402d826d98e3da
Signed-off-by: default avatarUdaya Mallavarapu <udaym@codeaurora.org>
parent 027c21bf

arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -1779,6 +1779,66 @@ 
			};

		};



		tsif0_signals_active: tsif0_signals_active {

			tsif1_clk {

				pins = "gpio89"; /* TSIF0 CLK */

				function = "tsif1_clk";

			};

			tsif1_en {

				pins = "gpio90"; /* TSIF0 Enable */

				function = "tsif1_en";

			};

			tsif1_data {

				pins = "gpio91"; /* TSIF0 DATA */

				function = "tsif1_data";

			};

			signals_cfg {

				pins = "gpio89", "gpio90", "gpio91";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		/* sync signal is only used if configured to mode-2 */

		tsif0_sync_active: tsif0_sync_active {

			tsif1_sync {

				pins = "gpio9";	/* TSIF0 SYNC */

				function = "tsif1_sync";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		tsif1_signals_active: tsif1_signals_active {

			tsif2_clk {

				pins = "gpio93"; /* TSIF1 CLK */

				function = "tsif2_clk";

			};

			tsif2_en {

				pins = "gpio94"; /* TSIF1 Enable */

				function = "tsif2_en";

			};

			tsif2_data {

				pins = "gpio95"; /* TSIF1 DATA */

				function = "tsif2_data";

			};

			signals_cfg {

				pins = "gpio93", "gpio94", "gpio95";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		/* sync signal is only used if configured to mode-2 */

		tsif1_sync_active: tsif1_sync_active {

			tsif2_sync {

				pins = "gpio96";	/* TSIF1 SYNC */

				function = "tsif2_sync";

				drive_strength = <2>;	/* 2 mA */

				bias-pull-down;		/* pull down */

			};

		};



		pri_aux_pcm_clk {

			pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {

				mux {

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -2886,6 +2886,57 @@ 
		qcom,icnss-adc_tm = <&pmcobalt_adc_tm>;

	};



	tspp: msm_tspp@0c1e7000 {

		compatible = "qcom,msm_tspp";

		reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */

		      <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */

		      <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS  */

		      <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */

		reg-names = "MSM_TSIF0_PHYS",

			"MSM_TSIF1_PHYS",

			"MSM_TSPP_PHYS",

			"MSM_TSPP_BAM_PHYS";

		interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */

			<0 119 0>, /* TSIF0_IRQ */

			<0 120 0>, /* TSIF1_IRQ */

			<0 122 0>; /* TSIF_BAM_IRQ */

		interrupt-names = "TSIF_TSPP_IRQ",

			"TSIF0_IRQ",

			"TSIF1_IRQ",

			"TSIF_BAM_IRQ";



		clock-names = "iface_clk", "ref_clk";

		clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>,

			<&clock_gcc clk_gcc_tsif_ref_clk>;



		qcom,msm-bus,name = "tsif";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<82 512 0 0>, /* No vote */

				<82 512 12288 24576>;

				/* Max. bandwidth, 2xTSIF, each max of 96Mbps */



		pinctrl-names = "disabled",

			"tsif0-mode1", "tsif0-mode2",

			"tsif1-mode1", "tsif1-mode2",

			"dual-tsif-mode1", "dual-tsif-mode2";



		pinctrl-0 = <>;				/* disabled */

		pinctrl-1 = <&tsif0_signals_active>;	/* tsif0-mode1 */

		pinctrl-2 = <&tsif0_signals_active

			&tsif0_sync_active>;		/* tsif0-mode2 */

		pinctrl-3 = <&tsif1_signals_active>;	/* tsif1-mode1 */

		pinctrl-4 = <&tsif1_signals_active

			&tsif1_sync_active>;		/* tsif1-mode2 */

		pinctrl-5 = <&tsif0_signals_active

			&tsif1_signals_active>;		/* dual-tsif-mode1 */

		pinctrl-6 = <&tsif0_signals_active

			&tsif0_sync_active

			&tsif1_signals_active

			&tsif1_sync_active>;		/* dual-tsif-mode2 */

	};



	wil6210: qcom,wil6210 {

		compatible = "qcom,wil6210";

		qcom,pcie-parent = <&pcie0>;