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Commit 57f5019a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add support for MMCC clock for MSMFalcon"

parents 0e7a3bb0 48638ac9
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@@ -10,6 +10,7 @@ Required properties :
			"qcom,mmcc-msm8960"
			"qcom,mmcc-msm8974"
			"qcom,mmcc-msm8996"
			"qcom,mmcc-msmfalcon"

- reg : shall contain base register location and length
- #clock-cells : shall contain 1
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@@ -173,6 +173,16 @@ config MSM_GPUCC_FALCON
	  Say Y if you want to support graphics controller devices which will
	  be required to enable those device.

config MSM_MMCC_FALCON
	tristate "MSMFALCON Multimedia Clock Controller"
	select MSM_GCC_FALCON
	depends on COMMON_CLK_QCOM
	help
	  Support for the multimedia clock controller on Qualcomm Technologies, Inc
	  MSMfalcon devices.
	  Say Y if you want to support multimedia devices such as display,
	  video encode/decode, camera, etc.

config QCOM_HFPLL
	tristate "High-Frequency PLL (HFPLL) Clock Controller"
	depends on COMMON_CLK_QCOM
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@@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o
obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
obj-$(CONFIG_KRAITCC) += krait-cc.o
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@@ -116,6 +116,21 @@
	},						\
	.num_rate_max = VDD_DIG_NUM

#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \
	.vdd_class = &vdd_mx,			\
	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
		[VDD_DIG_##l1] = (f1),		\
	},					\
	.num_rate_max = VDD_DIG_NUM

#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \
	.vdd_class = &vdd_mx,			\
	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
		[VDD_DIG_##l1] = (f1),		\
		[VDD_DIG_##l2] = (f2),		\
	},					\
	.num_rate_max = VDD_DIG_NUM

enum vdd_dig_levels {
	VDD_DIG_NONE,
	VDD_DIG_MIN,		/* MIN SVS */
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