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Commit 57db8863 authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati
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ASoC: wcd934x: Update codec master clock configuration 



Update wcd934x codec master clock configuration to
9.6MHz or 12.288MHz based on the device tree setting.
This is done during early codec initialization to prevent
artifacts when audio path is enabled.

CRs-fixed: 1061430
Change-Id: Ic983a524b6fa5bb079c6e61b8fe729974de78eea
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
parent ab26d098

sound/soc/codecs/wcd934x/wcd934x.c

+10 −8
Original line number Diff line number Diff line
@@ -6816,14 +6816,6 @@ static int tavil_soc_codec_probe(struct snd_soc_codec *codec) 
	for (i = 0; i < COMPANDER_MAX; i++)

		tavil->comp_enabled[i] = 0;



	dev_dbg(codec->dev, "%s: MCLK Rate = %x\n", __func__,

			control->mclk_rate);

	if (control->mclk_rate == WCD934X_MCLK_CLK_12P288MHZ)

		snd_soc_update_bits(codec, WCD934X_CODEC_RPM_CLK_MCLK_CFG,

				    0x03, 0x00);

	else if (control->mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)

		snd_soc_update_bits(codec, WCD934X_CODEC_RPM_CLK_MCLK_CFG,

				    0x03, 0x01);

	tavil_codec_init_reg(codec);

	tavil_enable_sido_buck(codec);
@@ -7480,6 +7472,16 @@ static int tavil_probe(struct platform_device *pdev) 
	tavil->wcd_ext_clk = wcd_ext_clk;

	set_bit(AUDIO_NOMINAL, &tavil->status_mask);

	/* Update codec register default values */

	dev_dbg(&pdev->dev, "%s: MCLK Rate = %x\n", __func__,

		tavil->wcd9xxx->mclk_rate);

	if (tavil->wcd9xxx->mclk_rate == WCD934X_MCLK_CLK_12P288MHZ)

		regmap_update_bits(tavil->wcd9xxx->regmap,

				   WCD934X_CODEC_RPM_CLK_MCLK_CFG,

				   0x03, 0x00);

	else if (tavil->wcd9xxx->mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)

		regmap_update_bits(tavil->wcd9xxx->regmap,

				   WCD934X_CODEC_RPM_CLK_MCLK_CFG,

				   0x03, 0x01);

	tavil_update_reg_defaults(tavil);

	__tavil_enable_efuse_sensing(tavil);