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Commit 57741a77 authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar
Browse files

x86_64: set cfg_size for AMD Family 10h in case MMCONFIG 



reuse pci_cfg_space_size but skip check pci express and pci-x CAP ID.

Signed-off-by: default avatarYinghai Lu <yinghai.lu@sun.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 05c58b8a

arch/x86/pci/fixup.c

+17 −0
Original line number Diff line number Diff line
@@ -493,3 +493,20 @@ static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev) 
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,

			  pci_siemens_interrupt_controller);



/*

 * Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config

 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can

 * access it.  Maybe we don't have a way to generate extended config space

 * accesses.   So check it

 */

static void fam10h_pci_cfg_space_size(struct pci_dev *dev)

{

	dev->cfg_size = pci_cfg_space_size_ext(dev, 0);

}



DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);

drivers/pci/probe.c

+10 −1
Original line number Diff line number Diff line
@@ -842,11 +842,14 @@ static void set_pcie_port_type(struct pci_dev *pdev) 
 * reading the dword at 0x100 which must either be 0 or a valid extended

 * capability header.

 */

int pci_cfg_space_size(struct pci_dev *dev)

int pci_cfg_space_size_ext(struct pci_dev *dev, unsigned check_exp_pcix)

{

	int pos;

	u32 status;



	if (!check_exp_pcix)

		goto skip;



	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);

	if (!pos) {

		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
@@ -858,6 +861,7 @@ int pci_cfg_space_size(struct pci_dev *dev) 
			goto fail;

	}



 skip:

	if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)

		goto fail;

	if (status == 0xffffffff)
@@ -869,6 +873,11 @@ int pci_cfg_space_size(struct pci_dev *dev) 
	return PCI_CFG_SPACE_SIZE;

}



int pci_cfg_space_size(struct pci_dev *dev)

{

	return pci_cfg_space_size_ext(dev, 1);

}



static void pci_release_bus_bridge_dev(struct device *dev)

{

	kfree(dev);

include/linux/pci.h

+1 −0
Original line number Diff line number Diff line
@@ -666,6 +666,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 


void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),

		  void *userdata);

int pci_cfg_space_size_ext(struct pci_dev *dev, unsigned check_exp_pcix);

int pci_cfg_space_size(struct pci_dev *dev);

unsigned char pci_bus_max_busnr(struct pci_bus *bus);