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Commit 55b19878 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: Fix clocks which are required to be always on 



Following are the changes made:
1. Add CLK_IGNORE_UNUSED flag for some clocks which are not
   supposed to be disabled at late_init_level.
2. Fix clock measure debug mux value for mmcc clocks.
3. Add mmss_mdss_byte1_intf_div_clk for mdp.
4. Fix usb ref clocks to branch voted.

Change-Id: I06396c73f7855acfac283abe576e0b4cc1a92bd5
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 79a1a55c

drivers/clk/qcom/gcc-sdm660.c

+188 −98
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1832,7 +1832,7 @@ static struct clk_branch gcc_hmss_ahb_clk = { 
				"hmss_ahb_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1847,6 +1847,7 @@ static struct clk_branch gcc_hmss_dvm_bus_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_hmss_dvm_bus_clk",

			.ops = &clk_branch2_ops,

			.flags = CLK_IGNORE_UNUSED,

		},

	},

};
@@ -2054,7 +2055,7 @@ static struct clk_branch gcc_qspi_ser_clk = { 


static struct clk_branch gcc_rx0_usb2_clkref_clk = {

	.halt_reg = 0x88018,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x88018,

		.enable_mask = BIT(0),
@@ -2067,7 +2068,7 @@ static struct clk_branch gcc_rx0_usb2_clkref_clk = { 


static struct clk_branch gcc_rx1_usb2_clkref_clk = {

	.halt_reg = 0x88014,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x88014,

		.enable_mask = BIT(0),
@@ -2080,7 +2081,7 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { 


static struct clk_branch gcc_rx2_qlink_clkref_clk = {

	.halt_reg = 0x88034,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x88034,

		.enable_mask = BIT(0),
@@ -2570,6 +2571,7 @@ static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { 
	.hw.init = &(struct clk_init_data){

		.name = "gcc_ce1_ahb_m_clk",

		.ops = &clk_dummy_ops,

		.flags = CLK_IGNORE_UNUSED,

	},

};
@@ -2577,6 +2579,7 @@ static struct clk_fixed_factor gcc_ce1_axi_m_clk = { 
	.hw.init = &(struct clk_init_data){

		.name = "gcc_ce1_axi_m_clk",

		.ops = &clk_dummy_ops,

		.flags = CLK_IGNORE_UNUSED,

	},

};
@@ -3107,93 +3110,180 @@ static struct clk_debug_mux gcc_debug_mux = { 
		{ "gcc_ufs_rx_symbol_1_clk",		0x162 },

		{ "gcc_ufs_tx_symbol_0_clk",		0x0EC },

		{ "gcc_usb3_phy_pipe_clk",		0x040 },

		{ "mmssnoc_axi_clk",                    0x22,   MMCC,   0x004 },

		{ "mmss_bimc_smmu_ahb_clk",		0x22,	MMCC,	0x00C },

		{ "mmss_bimc_smmu_axi_clk",		0x22,	MMCC,	0x00D },

		{ "mmss_camss_ahb_clk",			0x22,	MMCC,	0x037 },

		{ "mmss_camss_cci_ahb_clk",		0x22,	MMCC,	0x02E },

		{ "mmss_camss_cci_clk",			0x22,	MMCC,	0x02D },

		{ "mmss_camss_cphy_csid0_clk",		0x22,	MMCC,	0x08D },

		{ "mmss_camss_cphy_csid1_clk",		0x22,	MMCC,	0x08E },

		{ "mmss_camss_cphy_csid2_clk",		0x22,	MMCC,	0x08F },

		{ "mmss_camss_cphy_csid3_clk",		0x22,	MMCC,	0x090 },

		{ "mmss_camss_cpp_ahb_clk",		0x22,	MMCC,	0x03B },

		{ "mmss_camss_cpp_axi_clk",		0x22,	MMCC,	0x07A },

		{ "mmss_camss_cpp_clk",			0x22,	MMCC,	0x03A },

		{ "mmss_camss_cpp_vbif_ahb_clk",	0x22,	MMCC,	0x073 },

		{ "mmss_camss_csi0_ahb_clk",		0x22,	MMCC,	0x042 },

		{ "mmss_camss_csi0_clk",		0x22,	MMCC,	0x041 },

		{ "mmss_camss_csi0phytimer_clk",	0x22,	MMCC,	0x02F },

		{ "mmss_camss_csi0pix_clk",		0x22,	MMCC,	0x045 },

		{ "mmss_camss_csi0rdi_clk",		0x22,	MMCC,	0x044 },

		{ "mmss_camss_csi1_ahb_clk",		0x22,	MMCC,	0x047 },

		{ "mmss_camss_csi1_clk",		0x22,	MMCC,	0x046 },

		{ "mmss_camss_csi1phytimer_clk",	0x22,	MMCC,	0x030 },

		{ "mmss_camss_csi1pix_clk",		0x22,	MMCC,	0x04A },

		{ "mmss_camss_csi1rdi_clk",		0x22,	MMCC,	0x049 },

		{ "mmss_camss_csi2_ahb_clk",		0x22,	MMCC,	0x04C },

		{ "mmss_camss_csi2_clk",		0x22,	MMCC,	0x04B },

		{ "mmss_camss_csi2phytimer_clk",	0x22,	MMCC,	0x031 },

		{ "mmss_camss_csi2pix_clk",		0x22,	MMCC,	0x04F },

		{ "mmss_camss_csi2rdi_clk",		0x22,	MMCC,	0x04E },

		{ "mmss_camss_csi3_ahb_clk",		0x22,	MMCC,	0x051 },

		{ "mmss_camss_csi3_clk",		0x22,	MMCC,	0x050 },

		{ "mmss_camss_csi3pix_clk",		0x22,	MMCC,	0x054 },

		{ "mmss_camss_csi3rdi_clk",		0x22,	MMCC,	0x053 },

		{ "mmss_camss_csi_vfe0_clk",		0x22,	MMCC,	0x03F },

		{ "mmss_camss_csi_vfe1_clk",		0x22,	MMCC,	0x040 },

		{ "mmss_camss_csiphy0_clk",		0x22,	MMCC,	0x043 },

		{ "mmss_camss_csiphy1_clk",		0x22,	MMCC,	0x085 },

		{ "mmss_camss_csiphy2_clk",		0x22,	MMCC,	0x088 },

		{ "mmss_camss_gp0_clk",			0x22,	MMCC,	0x027 },

		{ "mmss_camss_gp1_clk",			0x22,	MMCC,	0x028 },

		{ "mmss_camss_ispif_ahb_clk",		0x22,	MMCC,	0x033 },

		{ "mmss_camss_jpeg0_clk",		0x22,	MMCC,	0x032 },

		{ "mmss_camss_jpeg_ahb_clk",		0x22,	MMCC,	0x035 },

		{ "mmss_camss_jpeg_axi_clk",		0x22,	MMCC,	0x036 },

		{ "mmss_camss_mclk0_clk",		0x22,	MMCC,	0x029 },

		{ "mmss_camss_mclk1_clk",		0x22,	MMCC,	0x02A },

		{ "mmss_camss_mclk2_clk",		0x22,	MMCC,	0x02B },

		{ "mmss_camss_mclk3_clk",		0x22,	MMCC,	0x02C },

		{ "mmss_camss_micro_ahb_clk",		0x22,	MMCC,	0x026 },

		{ "mmss_camss_top_ahb_clk",		0x22,	MMCC,	0x025 },

		{ "mmss_camss_vfe0_ahb_clk",		0x22,	MMCC,	0x086 },

		{ "mmss_camss_vfe0_clk",		0x22,	MMCC,	0x038 },

		{ "mmss_camss_vfe0_stream_clk",		0x22,	MMCC,	0x071 },

		{ "mmss_camss_vfe1_ahb_clk",		0x22,	MMCC,	0x087 },

		{ "mmss_camss_vfe1_clk",		0x22,	MMCC,	0x039 },

		{ "mmss_camss_vfe1_stream_clk",		0x22,	MMCC,	0x072 },

		{ "mmss_camss_vfe_vbif_ahb_clk",	0x22,	MMCC,	0x03C },

		{ "mmss_camss_vfe_vbif_axi_clk",	0x22,	MMCC,	0x03D },

		{ "mmss_csiphy_ahb2crif_clk",		0x22,	MMCC,	0x0B8 },

		{ "mmss_mdss_ahb_clk",			0x22,	MMCC,	0x022 },

		{ "mmss_mdss_axi_clk",			0x22,	MMCC,	0x024 },

		{ "mmss_mdss_byte0_clk",		0x22,	MMCC,	0x01E },

		{ "mmss_mdss_byte0_intf_clk",		0x22,	MMCC,	0x0AD },

		{ "mmss_mdss_byte1_clk",		0x22,	MMCC,	0x01F },

		{ "mmss_mdss_byte1_intf_clk",		0x22,	MMCC,	0x0B6 },

		{ "mmss_mdss_dp_aux_clk",		0x22,	MMCC,	0x09C },

		{ "mmss_mdss_dp_crypto_clk",		0x22,	MMCC,	0x09A },

		{ "mmss_mdss_dp_gtc_clk",		0x22,	MMCC,	0x09D },

		{ "mmss_mdss_dp_link_clk",		0x22,	MMCC,	0x098 },

		{ "mmss_mdss_dp_link_intf_clk",		0x22,	MMCC,	0x099 },

		{ "mmss_mdss_dp_pixel_clk",		0x22,	MMCC,	0x09B },

		{ "mmss_mdss_esc0_clk",			0x22,	MMCC,	0x020 },

		{ "mmss_mdss_esc1_clk",			0x22,	MMCC,	0x021 },

		{ "mmss_mdss_hdmi_dp_ahb_clk",		0x22,	MMCC,	0x023 },

		{ "mmss_mdss_mdp_clk",			0x22,	MMCC,	0x014 },

		{ "mmss_mdss_pclk0_clk",		0x22,	MMCC,	0x016 },

		{ "mmss_mdss_pclk1_clk",		0x22,	MMCC,	0x017 },

		{ "mmss_mdss_rot_clk",			0x22,	MMCC,	0x012 },

		{ "mmss_mdss_vsync_clk",		0x22,	MMCC,	0x01C },

		{ "mmss_misc_ahb_clk",			0x22,	MMCC,	0x003 },

		{ "mmss_misc_cxo_clk",			0x22,	MMCC,	0x077 },

		{ "mmss_mnoc_ahb_clk",			0x22,	MMCC,	0x001 },

		{ "mmss_snoc_dvm_axi_clk",		0x22,	MMCC,	0x013 },

		{ "mmss_video_ahb_clk",			0x22,	MMCC,	0x011 },

		{ "mmss_video_axi_clk",			0x22,	MMCC,	0x00F },

		{ "mmss_video_core_clk",		0x22,	MMCC,	0x00E },

		{ "mmss_video_subcore0_clk",		0x22,	MMCC,	0x01A },

		{ "mmssnoc_axi_clk",	0x22,   MMCC,

						0x004, 0, 0, 0x1000 },

		{ "mmss_bimc_smmu_ahb_clk", 0x22,	MMCC,

						0x00C, 0, 0, 0x1000 },

		{ "mmss_bimc_smmu_axi_clk",	0x22,	MMCC,

						0x00D, 0, 0, 0x1000 },

		{ "mmss_camss_ahb_clk",		0x22,	MMCC,

						0x037, 0, 0, 0x1000 },

		{ "mmss_camss_cci_ahb_clk",	0x22,	MMCC,

						0x02E, 0, 0, 0x1000 },

		{ "mmss_camss_cci_clk",		0x22,	MMCC,

						0x02D, 0, 0, 0x1000 },

		{ "mmss_camss_cphy_csid0_clk",	0x22,	MMCC,

						0x08D, 0, 0, 0x1000 },

		{ "mmss_camss_cphy_csid1_clk",	0x22,	MMCC,

						0x08E, 0, 0, 0x1000 },

		{ "mmss_camss_cphy_csid2_clk",	0x22,	MMCC,

						0x08F, 0, 0, 0x1000 },

		{ "mmss_camss_cphy_csid3_clk",	0x22,	MMCC,

						0x090, 0, 0, 0x1000 },

		{ "mmss_camss_cpp_ahb_clk",	0x22,	MMCC,

						0x03B, 0, 0, 0x1000 },

		{ "mmss_camss_cpp_axi_clk",	0x22,	MMCC,

						0x07A, 0, 0, 0x1000 },

		{ "mmss_camss_cpp_clk",		0x22,	MMCC,

						0x03A, 0, 0, 0x1000 },

		{ "mmss_camss_cpp_vbif_ahb_clk", 0x22,	MMCC,

						0x073, 0, 0, 0x1000 },

		{ "mmss_camss_csi0_ahb_clk",	0x22,	MMCC,

						0x042, 0, 0, 0x1000 },

		{ "mmss_camss_csi0_clk",	0x22,	MMCC,

						0x041, 0, 0, 0x1000 },

		{ "mmss_camss_csi0phytimer_clk", 0x22,	MMCC,

						0x02F, 0, 0, 0x1000 },

		{ "mmss_camss_csi0pix_clk",	0x22,	MMCC,

						0x045, 0, 0, 0x1000 },

		{ "mmss_camss_csi0rdi_clk",	0x22,	MMCC,

						0x044, 0, 0, 0x1000 },

		{ "mmss_camss_csi1_ahb_clk",	0x22,	MMCC,

						0x047, 0, 0, 0x1000 },

		{ "mmss_camss_csi1_clk",	0x22,	MMCC,

						0x046, 0, 0, 0x1000 },

		{ "mmss_camss_csi1phytimer_clk", 0x22,	MMCC,

						0x030, 0, 0, 0x1000 },

		{ "mmss_camss_csi1pix_clk",	0x22,	MMCC,

						0x04A, 0, 0, 0x1000 },

		{ "mmss_camss_csi1rdi_clk",	0x22,	MMCC,

						0x049, 0, 0, 0x1000 },

		{ "mmss_camss_csi2_ahb_clk",	0x22,	MMCC,

						0x04C, 0, 0, 0x1000 },

		{ "mmss_camss_csi2_clk",	0x22,	MMCC,

						0x04B, 0, 0, 0x1000 },

		{ "mmss_camss_csi2phytimer_clk", 0x22,	MMCC,

						0x031, 0, 0, 0x1000 },

		{ "mmss_camss_csi2pix_clk",	0x22,	MMCC,

						0x04F, 0, 0, 0x1000 },

		{ "mmss_camss_csi2rdi_clk",	0x22,	MMCC,

						0x04E, 0, 0, 0x1000 },

		{ "mmss_camss_csi3_ahb_clk",	0x22,	MMCC,

						0x051, 0, 0, 0x1000 },

		{ "mmss_camss_csi3_clk",	0x22,	MMCC,

						0x050, 0, 0, 0x1000 },

		{ "mmss_camss_csi3pix_clk",	0x22,   MMCC,

						0x054, 0, 0, 0x1000 },

		{ "mmss_camss_csi3rdi_clk",	0x22,	MMCC,

						0x053, 0, 0, 0x1000 },

		{ "mmss_camss_csi_vfe0_clk",	0x22,	MMCC,

						0x03F, 0, 0, 0x1000 },

		{ "mmss_camss_csi_vfe1_clk",	0x22,	MMCC,

						0x040, 0, 0, 0x1000 },

		{ "mmss_camss_csiphy0_clk",	0x22,	MMCC,

						0x043, 0, 0, 0x1000 },

		{ "mmss_camss_csiphy1_clk",	0x22,	MMCC,

						0x085, 0, 0, 0x1000 },

		{ "mmss_camss_csiphy2_clk",	0x22,	MMCC,

						0x088, 0, 0, 0x1000 },

		{ "mmss_camss_gp0_clk",		0x22,	MMCC,

						0x027, 0, 0, 0x1000 },

		{ "mmss_camss_gp1_clk",		0x22,	MMCC,

						0x028, 0, 0, 0x1000 },

		{ "mmss_camss_ispif_ahb_clk",	0x22,	MMCC,

						0x033, 0, 0, 0x1000 },

		{ "mmss_camss_jpeg0_clk",	0x22,	MMCC,

						0x032, 0, 0, 0x1000 },

		{ "mmss_camss_jpeg_ahb_clk",	0x22,	MMCC,

						0x035, 0, 0, 0x1000 },

		{ "mmss_camss_jpeg_axi_clk",	0x22,	MMCC,

						0x036, 0, 0, 0x1000 },

		{ "mmss_camss_mclk0_clk",	0x22,	MMCC,

						0x029, 0, 0, 0x1000 },

		{ "mmss_camss_mclk1_clk",	0x22,	MMCC,

						0x02A, 0, 0, 0x1000 },

		{ "mmss_camss_mclk2_clk",	0x22,	MMCC,

						0x02B, 0, 0, 0x1000 },

		{ "mmss_camss_mclk3_clk",	0x22,	MMCC,

						0x02C, 0, 0, 0x1000 },

		{ "mmss_camss_micro_ahb_clk",	0x22,	MMCC,

						0x026, 0, 0, 0x1000 },

		{ "mmss_camss_top_ahb_clk",	0x22,	MMCC,

						0x025, 0, 0, 0x1000 },

		{ "mmss_camss_vfe0_ahb_clk",	0x22,	MMCC,

						0x086, 0, 0, 0x1000 },

		{ "mmss_camss_vfe0_clk",	0x22,	MMCC,

						0x038, 0, 0, 0x1000 },

		{ "mmss_camss_vfe0_stream_clk",	0x22,	MMCC,

						0x071, 0, 0, 0x1000 },

		{ "mmss_camss_vfe1_ahb_clk",	0x22,	MMCC,

						0x087, 0, 0, 0x1000 },

		{ "mmss_camss_vfe1_clk",	0x22,	MMCC,

						0x039, 0, 0, 0x1000 },

		{ "mmss_camss_vfe1_stream_clk",	0x22,	MMCC,

						0x072, 0, 0, 0x1000 },

		{ "mmss_camss_vfe_vbif_ahb_clk", 0x22,	MMCC,

						0x03C, 0, 0, 0x1000 },

		{ "mmss_camss_vfe_vbif_axi_clk", 0x22,	MMCC,

						0x03D, 0, 0, 0x1000 },

		{ "mmss_csiphy_ahb2crif_clk",	0x22,	MMCC,

						0x0B8, 0, 0, 0x1000 },

		{ "mmss_mdss_ahb_clk",		0x22,	MMCC,

						0x022, 0, 0, 0x1000 },

		{ "mmss_mdss_axi_clk",		0x22,	MMCC,

						0x024, 0, 0, 0x1000 },

		{ "mmss_mdss_byte0_clk",	0x22,	MMCC,

						0x01E, 0, 0, 0x1000 },

		{ "mmss_mdss_byte0_intf_clk",	0x22,	MMCC,

						0x0AD, 0, 0, 0x1000 },

		{ "mmss_mdss_byte1_clk",	0x22,	MMCC,

						0x01F, 0, 0, 0x1000 },

		{ "mmss_mdss_byte1_intf_clk",	0x22,	MMCC,

						0x0B6, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_aux_clk",	0x22,	MMCC,

						0x09C, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_crypto_clk",	0x22,	MMCC,

						0x09A, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_gtc_clk",	0x22,	MMCC,

						0x09D, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_link_clk",	0x22,	MMCC,

						0x098, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_link_intf_clk",	0x22,	MMCC,

						0x099, 0, 0, 0x1000 },

		{ "mmss_mdss_dp_pixel_clk",	0x22,	MMCC,

						0x09B, 0, 0, 0x1000 },

		{ "mmss_mdss_esc0_clk",		0x22,	MMCC,

						0x020, 0, 0, 0x1000 },

		{ "mmss_mdss_esc1_clk",		0x22,	MMCC,

						0x021, 0, 0, 0x1000 },

		{ "mmss_mdss_hdmi_dp_ahb_clk",	0x22,	MMCC,

						0x023, 0, 0, 0x1000 },

		{ "mmss_mdss_mdp_clk",		0x22,	MMCC,

						0x014, 0, 0, 0x1000 },

		{ "mmss_mdss_pclk0_clk",	0x22,	MMCC,

						0x016, 0, 0, 0x1000 },

		{ "mmss_mdss_pclk1_clk",	0x22,	MMCC,

						0x017, 0, 0, 0x1000 },

		{ "mmss_mdss_rot_clk",		0x22,	MMCC,

						0x012, 0, 0, 0x1000 },

		{ "mmss_mdss_vsync_clk",	0x22,	MMCC,

						0x01C, 0, 0, 0x1000 },

		{ "mmss_misc_ahb_clk",		0x22,	MMCC,

						0x003, 0, 0, 0x1000 },

		{ "mmss_misc_cxo_clk",		0x22,	MMCC,

						0x077, 0, 0, 0x1000 },

		{ "mmss_mnoc_ahb_clk",		0x22,	MMCC,

						0x001, 0, 0, 0x1000 },

		{ "mmss_snoc_dvm_axi_clk",	0x22,	MMCC,

						0x013, 0, 0, 0x1000 },

		{ "mmss_video_ahb_clk",		0x22,	MMCC,

						0x011, 0, 0, 0x1000 },

		{ "mmss_video_axi_clk",		0x22,	MMCC,

						0x00F, 0, 0, 0x1000 },

		{ "mmss_video_core_clk",	0x22,	MMCC,

						0x00E, 0, 0, 0x1000 },

		{ "mmss_video_subcore0_clk",	0x22,	MMCC,

						0x01A, 0, 0, 0x1000 },

		{ "gpucc_gfx3d_clk",		0x13d,	GPU, 0x008 },

		{ "gpucc_rbbmtimer_clk",	0x13d,	GPU, 0x005 },

		{ "gpucc_rbcpr_clk",		0x13d,	GPU, 0x003 },
@@ -3280,7 +3370,7 @@ static int clk_debug_660_probe(struct platform_device *pdev) 


		/* Clear the DBG_CLK_DIV bits of the MMSS debug register */

		regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0,

						0x60000, 0x0);

						0x15400, 0x0);

	}



	if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) {

drivers/clk/qcom/mmcc-sdm660.c

+26 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -2372,7 +2372,7 @@ static struct clk_branch mmss_mdss_byte0_intf_clk = { 
				"mmss_mdss_byte0_intf_div_clk",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2426,14 +2426,36 @@ static struct clk_branch mmss_mdss_byte1_intf_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "mmss_mdss_byte1_intf_clk",

			.parent_names = (const char *[]){

				"byte1_clk_src",

				"mmss_mdss_byte1_intf_div_clk",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_regmap_div mmss_mdss_byte1_intf_div_clk = {

	.reg = 0x2380,

	.shift = 0,

	.width = 2,

	/*

	 * NOTE: Op does not work for div-3. Current assumption is that div-3

	 * is not a recommended setting for this divider.

	 */

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "mmss_mdss_byte1_intf_div_clk",

			.parent_names = (const char *[]){

					"byte1_clk_src",

			},

			.num_parents = 1,

			.ops = &clk_regmap_div_ops,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		},

	},

};



static struct clk_branch mmss_mdss_dp_aux_clk = {

	.halt_reg = 0x2364,

	.halt_check = BRANCH_HALT,
@@ -2952,6 +2974,7 @@ static struct clk_regmap *mmcc_660_clocks[] = { 
	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,

	[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,

	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,

	[MMSS_MDSS_BYTE1_INTF_DIV_CLK] = &mmss_mdss_byte1_intf_div_clk.clkr,

};



static const struct qcom_reset_map mmcc_660_resets[] = {

include/dt-bindings/clock/qcom,mmcc-sdm660.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -203,6 +203,7 @@ 
#define VFE1_CLK_SRC                             188

#define VIDEO_CORE_CLK_SRC                       189

#define VSYNC_CLK_SRC                            190

#define MMSS_MDSS_BYTE1_INTF_DIV_CLK             191



#define BIMC_SMMU_GDSC                           0

#define CAMSS_CPP_GDSC                           1