Merge tag 'phy-for-4.4' of... (53966977) · Commits · e / devices / android_kernel_sony_msm8998

Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt

0 → 100644

+47 −0

Original line number	Original line	Diff line number	Diff line
			Broadcom Cygnus PCIe PHY

			Required properties:
			- compatible: must be "brcm,cygnus-pcie-phy"
			- reg: base address and length of the PCIe PHY block
			- #address-cells: must be 1
			- #size-cells: must be 0

			Each PCIe PHY should be represented by a child node

			Required properties For the child node:
			- reg: the PHY ID
			0 - PCIe RC 0
			1 - PCIe RC 1
			- #phy-cells: must be 0

			Example:
			pcie_phy: phy@0301d0a0 {
			compatible = "brcm,cygnus-pcie-phy";
			reg = <0x0301d0a0 0x14>;

			pcie0_phy: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
			};

			pcie1_phy: phy@1 {
			reg = <1>;
			#phy-cells = <0>;
			};
			};

			/* users of the PCIe phy */

			pcie0: pcie@18012000 {
			...
			...
			phys = <&pcie0_phy>;
			phy-names = "pcie-phy";
			};

			pcie1: pcie@18013000 {
			...
			...
			phys = <pcie1_phy>;
			phy-names = "pcie-phy";
			};

Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt

0 → 100644

+68 −0

Original line number	Original line	Diff line number	Diff line
			mt65xx USB3.0 PHY binding
			--------------------------

			This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.

			Required properties (controller (parent) node):
			- compatible : should be "mediatek,mt8173-u3phy"
			- reg : offset and length of register for phy, exclude port's
			register.
			- clocks : a list of phandle + clock-specifier pairs, one for each
			entry in clock-names
			- clock-names : must contain
			"u3phya_ref": for reference clock of usb3.0 analog phy.

			Required nodes : a sub-node is required for each port the controller
			provides. Address range information including the usual
			'reg' property is used inside these nodes to describe
			the controller's topology.

			Required properties (port (child) node):
			- reg : address and length of the register set for the port.
			- #phy-cells : should be 1 (See second example)
			cell after port phandle is phy type from:
			- PHY_TYPE_USB2
			- PHY_TYPE_USB3

			Example:

			u3phy: usb-phy@11290000 {
			compatible = "mediatek,mt8173-u3phy";
			reg = <0 0x11290000 0 0x800>;
			clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
			clock-names = "u3phya_ref";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "okay";

			phy_port0: port@11290800 {
			reg = <0 0x11290800 0 0x800>;
			#phy-cells = <1>;
			status = "okay";
			};

			phy_port1: port@11291000 {
			reg = <0 0x11291000 0 0x800>;
			#phy-cells = <1>;
			status = "okay";
			};
			};

			Specifying phy control of devices
			---------------------------------

			Device nodes should specify the configuration required in their "phys"
			property, containing a phandle to the phy port node and a device type;
			phy-names for each port are optional.

			Example:

			#include <dt-bindings/phy/phy.h>

			usb30: usb@11270000 {
			...
			phys = <&phy_port0 PHY_TYPE_USB3>;
			phy-names = "usb3-0";
			...
			};

Documentation/devicetree/bindings/phy/samsung-phy.txt

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -44,6 +44,9 @@ Required properties:
	- the "ref" clock is used to get the rate of the clock provided to the		- the "ref" clock is used to get the rate of the clock provided to the
	PHY module		PHY module

			Optional properties:
			- vbus-supply: power-supply phandle for vbus power source

	The first phandle argument in the PHY specifier identifies the PHY, its		The first phandle argument in the PHY specifier identifies the PHY, its
	meaning is compatible dependent. For the currently supported SoCs (Exynos 4210		meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
	and Exynos 4212) it is as follows:		and Exynos 4212) it is as follows:

MAINTAINERS

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1297,6 +1297,13 @@ F: arch/arm/mach-mediatek/
	N: mtk		N: mtk
	K: mediatek		K: mediatek

			ARM/Mediatek USB3 PHY DRIVER
			M: Chunfeng Yun <chunfeng.yun@mediatek.com>
			L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
			L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
			S: Maintained
			F: drivers/phy/phy-mt65xx-usb3.c

	ARM/MICREL KS8695 ARCHITECTURE		ARM/MICREL KS8695 ARCHITECTURE
	M: Greg Ungerer <gerg@uclinux.org>		M: Greg Ungerer <gerg@uclinux.org>
	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)		L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

drivers/phy/Kconfig

+18 −0

Original line number	Original line	Diff line number	Diff line
	@@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA
	help		help
	Support for SATA PHY on Hisilicon hix5hd2 Soc.		Support for SATA PHY on Hisilicon hix5hd2 Soc.

			config PHY_MT65XX_USB3
			tristate "Mediatek USB3.0 PHY Driver"
			depends on ARCH_MEDIATEK && OF
			select GENERIC_PHY
			help
			Say 'Y' here to add support for Mediatek USB3.0 PHY driver
			for mt65xx SoCs. it supports two usb2.0 ports and
			one usb3.0 port.

	config PHY_SUN4I_USB		config PHY_SUN4I_USB
	tristate "Allwinner sunxi SoC USB PHY driver"		tristate "Allwinner sunxi SoC USB PHY driver"
	depends on ARCH_SUNXI && HAS_IOMEM && OF		depends on ARCH_SUNXI && HAS_IOMEM && OF
	@@ -371,4 +380,13 @@ config PHY_BRCMSTB_SATA
	Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.		Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
	Likely useful only with CONFIG_SATA_BRCMSTB enabled.		Likely useful only with CONFIG_SATA_BRCMSTB enabled.

			config PHY_CYGNUS_PCIE
			tristate "Broadcom Cygnus PCIe PHY driver"
			depends on OF && (ARCH_BCM_CYGNUS \|\| COMPILE_TEST)
			select GENERIC_PHY
			default ARCH_BCM_CYGNUS
			help
			Enable this to support the Broadcom Cygnus PCIe PHY.
			If unsure, say N.

	endmenu		endmenu