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Commit 52e3de81 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable CX Ipeak Mitigation for MSMFALCON"

parents 0d2f3573 0daf7767

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+4 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ Required properties: 
		      If "halt_base" is in same 4K pages this register then

		      this will be defined else "halt_q6", "halt_modem",

		      "halt_nc" is required.

		      "cxip_lm_vote_clear" needs to defined , in case PIL has to

		      clear the CX Ipeak bit if it was set by MSS.

- interrupts:         The modem watchdog interrupt

- vdd_cx-supply:      Reference to the regulator that supplies the vdd_cx domain.

- vdd_cx-voltage:     Voltage corner/level(max) for cx rail.
@@ -84,6 +86,8 @@ Optional properties: 
		    wordline clamp, and compiler memory clamp during MSS restart.

- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10

- qcom,override-acc-1: Override the default ACC settings with this value if present.

- qcom,cx-ipeak-vote: Boolean- Present if we need to set bit 5 of cxip_lm_vote_clear

			 during modem shutdown



Example:

	qcom,mss@fc880000 {

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -1319,9 +1319,11 @@ 
		      <0x1f65000 0x008>,

		      <0x1f64000 0x008>,

		      <0x4180000 0x040>,

		      <0x00179000 0x004>;

		      <0x00179000 0x004>,

		      <0x01fe5048 0x004>;

		reg-names = "qdsp6_base", "halt_q6", "halt_modem",

			    "halt_nc", "rmb_base", "restart_reg";

			    "halt_nc", "rmb_base", "restart_reg",

			    "cxip_lm_vote_clear";



		clocks = <&clock_rpmcc RPM_XO_CLK_SRC>,

			 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
@@ -1352,6 +1354,7 @@ 
		qcom,qdsp6v62-1-5;

		memory-region = <&modem_fw_mem>;

		qcom,mem-protect-id = <0xF>;

		qcom,cx-ipeak-vote;



		/* GPIO inputs from mss */

		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;

drivers/soc/qcom/pil-msa.c

+11 −0
Original line number Diff line number Diff line
@@ -75,6 +75,9 @@ 
#define MSS_RESTART_ID			0xA



#define MSS_MAGIC			0XAABADEAD

/* CX_IPEAK Parameters */

#define CX_IPEAK_MSS			BIT(5)



enum scm_cmd {

	PAS_MEM_SETUP_CMD = 2,

};
@@ -304,6 +307,14 @@ int pil_mss_shutdown(struct pil_desc *pil) 
									ret);

	}



	/*

	 *  If MSS was in turbo state before fatal error occurs, it would

	 *  have set the vote bit. Since MSS is restarting, So PIL need to

	 *  clear this bit. This may clear the throttle state.

	 */

	if (drv->cx_ipeak_vote)

		writel_relaxed(CX_IPEAK_MSS, drv->cxip_lm_vote_clear);



	ret = pil_mss_restart_reg(drv, 1);



	if (drv->is_booted) {

drivers/soc/qcom/pil-q6v5-mss.c

+11 −0
Original line number Diff line number Diff line
@@ -270,6 +270,17 @@ static int pil_mss_loadable_init(struct modem_data *drv, 
		q6_desc->ops = &pil_msa_mss_ops_selfauth;

	}



	q6->cx_ipeak_vote = of_property_read_bool(pdev->dev.of_node,

							"qcom,cx-ipeak-vote");

	if (q6->cx_ipeak_vote) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						    "cxip_lm_vote_clear");

		q6->cxip_lm_vote_clear = devm_ioremap_resource(&pdev->dev,

								res);

		if (!q6->cxip_lm_vote_clear)

			return -ENOMEM;

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg");

	if (!res) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

drivers/soc/qcom/pil-q6v5.h

+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ struct q6v5_data { 
	void __iomem *axi_halt_mss;

	void __iomem *axi_halt_nc;

	void __iomem *restart_reg;

	void __iomem *cxip_lm_vote_clear;

	struct regulator *vreg;

	struct regulator *vreg_cx;

	struct regulator *vreg_mx;
@@ -69,6 +70,7 @@ struct q6v5_data { 
	int override_acc_1;

	bool ahb_clk_vote;

	bool mx_spike_wa;

	bool cx_ipeak_vote;

};



int pil_q6v5_make_proxy_votes(struct pil_desc *pil);