ARM: tegra: remove legacy clock code (52dec4c9) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/mach-tegra/Makefile

+0 −5

Original line number	Diff line number	Diff line
		obj-y += common.o
		obj-y += io.o
		obj-y += irq.o
		obj-y += clock.o
		obj-y += fuse.o
		obj-y += pmc.o
		obj-y += flowctrl.o
		@@ -12,16 +11,12 @@ obj-y += reset.o
		obj-y += reset-handler.o
		obj-y += sleep.o
		obj-$(CONFIG_CPU_IDLE) += cpuidle.o
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
		ifeq ($(CONFIG_CPU_IDLE),y)
		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
		endif
		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
		ifeq ($(CONFIG_CPU_IDLE),y)

arch/arm/mach-tegra/clock.c

deleted100644 → 0

+0 −147

Original line number	Diff line number	Diff line
		/*
		*
		* Copyright (C) 2010 Google, Inc.
		* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
		*
		* Author:
		* Colin Cross <ccross@google.com>
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		* may be copied, distributed, and modified under those terms.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#include <linux/kernel.h>
		#include <linux/clk.h>
		#include <linux/clkdev.h>
		#include <linux/init.h>
		#include <linux/list.h>
		#include <linux/module.h>
		#include <linux/sched.h>
		#include <linux/seq_file.h>
		#include <linux/slab.h>
		#include <linux/clk/tegra.h>

		#include "board.h"
		#include "clock.h"

		/*
		* Locking:
		*
		* An additional mutex, clock_list_lock, is used to protect the list of all
		* clocks.
		*
		*/
		static DEFINE_MUTEX(clock_list_lock);
		static LIST_HEAD(clocks);

		void tegra_clk_add(struct clk *clk)
		{
		struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));

		mutex_lock(&clock_list_lock);
		list_add(&c->node, &clocks);
		mutex_unlock(&clock_list_lock);
		}

		struct clk tegra_get_clock_by_name(const char name)
		{
		struct clk_tegra *c;
		struct clk *ret = NULL;
		mutex_lock(&clock_list_lock);
		list_for_each_entry(c, &clocks, node) {
		if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
		ret = c->hw.clk;
		break;
		}
		}
		mutex_unlock(&clock_list_lock);
		return ret;
		}

		static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
		{
		struct clk *c;
		struct clk *p;
		struct clk *parent;

		int ret = 0;

		c = tegra_get_clock_by_name(table->name);

		if (!c) {
		pr_warn("Unable to initialize clock %s\n",
		table->name);
		return -ENODEV;
		}

		parent = clk_get_parent(c);

		if (table->parent) {
		p = tegra_get_clock_by_name(table->parent);
		if (!p) {
		pr_warn("Unable to find parent %s of clock %s\n",
		table->parent, table->name);
		return -ENODEV;
		}

		if (parent != p) {
		ret = clk_set_parent(c, p);
		if (ret) {
		pr_warn("Unable to set parent %s of clock %s: %d\n",
		table->parent, table->name, ret);
		return -EINVAL;
		}
		}
		}

		if (table->rate && table->rate != clk_get_rate(c)) {
		ret = clk_set_rate(c, table->rate);
		if (ret) {
		pr_warn("Unable to set clock %s to rate %lu: %d\n",
		table->name, table->rate, ret);
		return -EINVAL;
		}
		}

		if (table->enabled) {
		ret = clk_prepare_enable(c);
		if (ret) {
		pr_warn("Unable to enable clock %s: %d\n",
		table->name, ret);
		return -EINVAL;
		}
		}

		return 0;
		}

		void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
		{
		for (; table->name; table++)
		tegra_clk_init_one_from_table(table);
		}

		/* Several extended clock configuration bits (e.g., clock routing, clock
		* phase control) are included in PLL and peripheral clock source
		* registers. */
		int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
		{
		int ret = 0;
		struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));

		if (!clk->clk_cfg_ex) {
		ret = -ENOSYS;
		goto out;
		}
		ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);

		out:
		return ret;
		}

arch/arm/mach-tegra/clock.h

deleted100644 → 0

+0 −153

Original line number	Diff line number	Diff line
		/*
		* arch/arm/mach-tegra/include/mach/clock.h
		*
		* Copyright (C) 2010 Google, Inc.
		* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
		*
		* Author:
		* Colin Cross <ccross@google.com>
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		* may be copied, distributed, and modified under those terms.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#ifndef __MACH_TEGRA_CLOCK_H
		#define __MACH_TEGRA_CLOCK_H

		#include <linux/clk-provider.h>
		#include <linux/clkdev.h>
		#include <linux/list.h>

		#include <mach/clk.h>

		#define DIV_BUS (1 << 0)
		#define DIV_U71 (1 << 1)
		#define DIV_U71_FIXED (1 << 2)
		#define DIV_2 (1 << 3)
		#define DIV_U16 (1 << 4)
		#define PLL_FIXED (1 << 5)
		#define PLL_HAS_CPCON (1 << 6)
		#define MUX (1 << 7)
		#define PLLD (1 << 8)
		#define PERIPH_NO_RESET (1 << 9)
		#define PERIPH_NO_ENB (1 << 10)
		#define PERIPH_EMC_ENB (1 << 11)
		#define PERIPH_MANUAL_RESET (1 << 12)
		#define PLL_ALT_MISC_REG (1 << 13)
		#define PLLU (1 << 14)
		#define PLLX (1 << 15)
		#define MUX_PWM (1 << 16)
		#define MUX8 (1 << 17)
		#define DIV_U71_UART (1 << 18)
		#define MUX_CLK_OUT (1 << 19)
		#define PLLM (1 << 20)
		#define DIV_U71_INT (1 << 21)
		#define DIV_U71_IDLE (1 << 22)
		#define ENABLE_ON_INIT (1 << 28)
		#define PERIPH_ON_APB (1 << 29)

		struct clk_tegra;
		#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)

		struct clk_mux_sel {
		struct clk *input;
		u32 value;
		};

		struct clk_pll_freq_table {
		unsigned long input_rate;
		unsigned long output_rate;
		u16 n;
		u16 m;
		u8 p;
		u8 cpcon;
		};

		enum clk_state {
		UNINITIALIZED = 0,
		ON,
		OFF,
		};

		struct clk_tegra {
		/* node for master clocks list */
		struct list_head node; /* node for list of all clocks */
		struct clk_lookup lookup;
		struct clk_hw hw;

		bool set;
		unsigned long fixed_rate;
		unsigned long max_rate;
		unsigned long min_rate;
		u32 flags;
		const char *name;

		enum clk_state state;
		u32 div;
		u32 mul;

		u32 reg;
		u32 reg_shift;

		struct list_head shared_bus_list;

		union {
		struct {
		unsigned int clk_num;
		} periph;
		struct {
		unsigned long input_min;
		unsigned long input_max;
		unsigned long cf_min;
		unsigned long cf_max;
		unsigned long vco_min;
		unsigned long vco_max;
		const struct clk_pll_freq_table *freq_table;
		int lock_delay;
		unsigned long fixed_rate;
		} pll;
		struct {
		u32 sel;
		u32 reg_mask;
		} mux;
		struct {
		struct clk *main;
		struct clk *backup;
		} cpu;
		struct {
		struct list_head node;
		bool enabled;
		unsigned long rate;
		} shared_bus_user;
		} u;

		void (reset)(struct clk_hw , bool);
		int (clk_cfg_ex)(struct clk_hw , enum tegra_clk_ex_param, u32);
		};

		struct clk_duplicate {
		const char *name;
		struct clk_lookup lookup;
		};

		struct tegra_clk_init_table {
		const char *name;
		const char *parent;
		unsigned long rate;
		bool enabled;
		};

		void tegra_clk_add(struct clk *c);
		void tegra2_init_clocks(void);
		void tegra30_init_clocks(void);
		struct clk tegra_get_clock_by_name(const char name);
		void tegra_clk_init_from_table(struct tegra_clk_init_table *table);

		#endif

arch/arm/mach-tegra/include/mach/clk.h

deleted100644 → 0

+0 −41

Original line number	Diff line number	Diff line
		/*
		* arch/arm/mach-tegra/include/mach/clk.h
		*
		* Copyright (C) 2010 Google, Inc.
		*
		* Author:
		* Erik Gilling <konkers@google.com>
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		* may be copied, distributed, and modified under those terms.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#ifndef __MACH_CLK_H
		#define __MACH_CLK_H

		struct clk;

		enum tegra_clk_ex_param {
		TEGRA_CLK_VI_INP_SEL,
		TEGRA_CLK_DTV_INVERT,
		TEGRA_CLK_NAND_PAD_DIV2_ENB,
		TEGRA_CLK_PLLD_CSI_OUT_ENB,
		TEGRA_CLK_PLLD_DSI_OUT_ENB,
		TEGRA_CLK_PLLD_MIPI_MUX_SEL,
		};

		#ifndef CONFIG_COMMON_CLK
		unsigned long clk_get_rate_all_locked(struct clk *c);
		#endif

		void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
		int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);

		#endif

arch/arm/mach-tegra/tegra20_clocks.c

deleted100644 → 0

+0 −1623

File deleted.

Preview size limit exceeded, changes collapsed.