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Commit 52ab2538 authored by Brahmaji K's avatar Brahmaji K
Browse files

ARM: dts: msm: Add qseecom device node for msmfalcon 



Add qseecom device node with all the necessary parameters,
to enable qseecom driver on msmfalcon.

Change-Id: Ib29962ebc7427391d7c0e355fa46156d2a8d15e5
Signed-off-by: default avatarBrahmaji K <bkomma@codeaurora.org>
parent 04947ea3

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+28 −0
Original line number Original line Diff line number Diff line
@@ -1206,6 +1206,34 @@ 
		qcom,irq-is-percpu;

		qcom,irq-is-percpu;

		interrupts = <1 6 4>;

		interrupts = <1 6 4>;

	};

	};



	qcom_seecom: qseecom@86d00000 {

		compatible = "qcom,qseecom";

		reg = <0x86d00000 0x2200000>;

		reg-names = "secapp-region";

		qcom,hlos-num-ce-hw-instances = <1>;

		qcom,hlos-ce-hw-instance = <0>;

		qcom,qsee-ce-hw-instance = <0>;

		qcom,disk-encrypt-pipe-pair = <2>;

		qcom,support-fde;

		qcom,no-clock-support;

		qcom,msm-bus,name = "qseecom-noc";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<55 512 0 0>,

			<55 512 200000 400000>,

			<55 512 300000 800000>,

			<55 512 400000 1000000>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>;

		qcom,ce-opp-freq = <171430000>;

		qcom,qsee-reentrancy-support = <2>;

	};

};

};





#include "msmfalcon-ion.dtsi"

#include "msmfalcon-ion.dtsi"