Loading drivers/clk/msm/clock-gcc-cobalt.c +12 −0 Original line number Diff line number Diff line Loading @@ -1200,6 +1200,17 @@ static struct branch_clk gcc_aggre1_ufs_axi_clk = { }, }; static struct hw_ctl_clk gcc_aggre1_ufs_axi_hw_ctl_clk = { .cbcr_reg = GCC_AGGRE1_UFS_AXI_CBCR, .base = &virt_base, .c = { .dbg_name = "gcc_aggre1_ufs_axi_hw_ctl_clk", .parent = &gcc_aggre1_ufs_axi_clk.c, .ops = &clk_ops_branch_hw_ctl, CLK_INIT(gcc_aggre1_ufs_axi_hw_ctl_clk.c), }, }; static struct branch_clk gcc_aggre1_usb3_axi_clk = { .cbcr_reg = GCC_AGGRE1_USB3_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2597,6 +2608,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_qusb2phy_sec_reset), CLK_LIST(gpll0_out_msscc), CLK_LIST(gcc_aggre1_ufs_axi_clk), CLK_LIST(gcc_aggre1_ufs_axi_hw_ctl_clk), CLK_LIST(gcc_aggre1_usb3_axi_clk), CLK_LIST(gcc_bimc_mss_q6_axi_clk), CLK_LIST(gcc_blsp1_ahb_clk), Loading include/dt-bindings/clock/msm-clocks-cobalt.h +1 −0 Original line number Diff line number Diff line Loading @@ -157,6 +157,7 @@ #define clk_gcc_usb3_phy_reset 0x03d559f1 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 #define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 #define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 #define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f #define clk_gcc_blsp1_ahb_clk 0x8caa5b4f Loading Loading
drivers/clk/msm/clock-gcc-cobalt.c +12 −0 Original line number Diff line number Diff line Loading @@ -1200,6 +1200,17 @@ static struct branch_clk gcc_aggre1_ufs_axi_clk = { }, }; static struct hw_ctl_clk gcc_aggre1_ufs_axi_hw_ctl_clk = { .cbcr_reg = GCC_AGGRE1_UFS_AXI_CBCR, .base = &virt_base, .c = { .dbg_name = "gcc_aggre1_ufs_axi_hw_ctl_clk", .parent = &gcc_aggre1_ufs_axi_clk.c, .ops = &clk_ops_branch_hw_ctl, CLK_INIT(gcc_aggre1_ufs_axi_hw_ctl_clk.c), }, }; static struct branch_clk gcc_aggre1_usb3_axi_clk = { .cbcr_reg = GCC_AGGRE1_USB3_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2597,6 +2608,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_qusb2phy_sec_reset), CLK_LIST(gpll0_out_msscc), CLK_LIST(gcc_aggre1_ufs_axi_clk), CLK_LIST(gcc_aggre1_ufs_axi_hw_ctl_clk), CLK_LIST(gcc_aggre1_usb3_axi_clk), CLK_LIST(gcc_bimc_mss_q6_axi_clk), CLK_LIST(gcc_blsp1_ahb_clk), Loading
include/dt-bindings/clock/msm-clocks-cobalt.h +1 −0 Original line number Diff line number Diff line Loading @@ -157,6 +157,7 @@ #define clk_gcc_usb3_phy_reset 0x03d559f1 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 #define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 #define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 #define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f #define clk_gcc_blsp1_ahb_clk 0x8caa5b4f Loading