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Commit 4e3c6202 authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: camera: isp: Fix overflow recovery 



On vfe48 the write masters need to be reenabled after vfe h/w reset.

CRs-Fixed: 1067996
Change-Id: I3ca87ec06e6204e3cecb137d8d8b4f1cedfc3fe1
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent b5cf50d8

drivers/media/platform/msm/camera_v2/isp/msm_isp47.c

+65 −35
Original line number Diff line number Diff line
@@ -399,8 +399,8 @@ void msm_vfe47_init_hardware_reg(struct vfe_device *vfe_dev) 
	/* BUS_CFG */

	msm_camera_io_w(0x00000101, vfe_dev->vfe_base + 0x84);

	/* IRQ_MASK/CLEAR */

	msm_vfe47_config_irq(vfe_dev, 0x810000E0, 0xFFFFFF7E,

				MSM_ISP_IRQ_ENABLE);

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

			0x810000E0, 0xFFFFFF7E, MSM_ISP_IRQ_ENABLE);

	msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x64);

	msm_camera_io_w_mb(0xFFFFFFFF, vfe_dev->vfe_base + 0x68);

	msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x58);
@@ -408,8 +408,8 @@ void msm_vfe47_init_hardware_reg(struct vfe_device *vfe_dev) 


void msm_vfe47_clear_status_reg(struct vfe_device *vfe_dev)

{

	msm_vfe47_config_irq(vfe_dev, 0x80000000, 0x0,

				MSM_ISP_IRQ_SET);

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

			0x80000000, 0x0, MSM_ISP_IRQ_SET);

	msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x64);

	msm_camera_io_w_mb(0xFFFFFFFF, vfe_dev->vfe_base + 0x68);

	msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x58);
@@ -557,7 +557,8 @@ void msm_vfe47_read_irq_status(struct vfe_device *vfe_dev, 
		vfe_dev->error_info.camif_status =

		msm_camera_io_r(vfe_dev->vfe_base + 0x4A4);

		/* mask off camif error after first occurrance */

		msm_vfe47_config_irq(vfe_dev, 0, (1 << 0), MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev, 0,

					(1 << 0), MSM_ISP_IRQ_DISABLE);

	}



	if (*irq_status1 & (1 << 7))
@@ -796,7 +797,8 @@ void msm_vfe47_axi_cfg_comp_mask(struct vfe_device *vfe_dev, 
		stream_composite_mask << (comp_mask_index * 8));

	msm_camera_io_w(comp_mask, vfe_dev->vfe_base + 0x74);



	msm_vfe47_config_irq(vfe_dev, 1 << (comp_mask_index + 25), 0,

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << (comp_mask_index + 25), 0,

				MSM_ISP_IRQ_ENABLE);

}
@@ -811,7 +813,8 @@ void msm_vfe47_axi_clear_comp_mask(struct vfe_device *vfe_dev, 
	comp_mask &= ~(0x7F << (comp_mask_index * 8));

	msm_camera_io_w(comp_mask, vfe_dev->vfe_base + 0x74);



	msm_vfe47_config_irq(vfe_dev, (1 << (comp_mask_index + 25)), 0,

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				(1 << (comp_mask_index + 25)), 0,

				MSM_ISP_IRQ_DISABLE);

}
@@ -820,7 +823,8 @@ void msm_vfe47_axi_cfg_wm_irq_mask(struct vfe_device *vfe_dev, 
{

	int vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev, stream_info);



	msm_vfe47_config_irq(vfe_dev, 1 << (stream_info->wm[vfe_idx][0] + 8), 0,

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << (stream_info->wm[vfe_idx][0] + 8), 0,

				MSM_ISP_IRQ_ENABLE);

}
@@ -829,7 +833,8 @@ void msm_vfe47_axi_clear_wm_irq_mask(struct vfe_device *vfe_dev, 
{

	int vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev, stream_info);



	msm_vfe47_config_irq(vfe_dev, (1 << (stream_info->wm[vfe_idx][0] + 8)),

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				(1 << (stream_info->wm[vfe_idx][0] + 8)),

				0, MSM_ISP_IRQ_DISABLE);

}
@@ -1081,7 +1086,8 @@ void msm_vfe47_cfg_fetch_engine(struct vfe_device *vfe_dev, 
		temp |= (1 << 1);

		msm_camera_io_w(temp, vfe_dev->vfe_base + 0x84);



		msm_vfe47_config_irq(vfe_dev, (1 << 24), 0,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				(1 << 24), 0,

				MSM_ISP_IRQ_ENABLE);



		temp = fe_cfg->fetch_height - 1;
@@ -1411,7 +1417,8 @@ void msm_vfe47_update_camif_state(struct vfe_device *vfe_dev, 
		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x64);

		msm_camera_io_w(0x81, vfe_dev->vfe_base + 0x68);

		msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x58);

		msm_vfe47_config_irq(vfe_dev, 0x15, 0x81,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

					0x15, 0x81,

					MSM_ISP_IRQ_ENABLE);



		if ((vfe_dev->hvx_cmd > HVX_DISABLE) &&
@@ -1443,7 +1450,7 @@ void msm_vfe47_update_camif_state(struct vfe_device *vfe_dev, 
		if (vfe_dev->axi_data.src_info[VFE_PIX_0].input_mux == TESTGEN)

			update_state = DISABLE_CAMIF;

		/* turn off camif violation and error irqs */

		msm_vfe47_config_irq(vfe_dev, 0, 0x81,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev, 0, 0x81,

					MSM_ISP_IRQ_DISABLE);

		val = msm_camera_io_r(vfe_dev->vfe_base + 0x464);

		/* disable danger signal */
@@ -1468,7 +1475,8 @@ void msm_vfe47_update_camif_state(struct vfe_device *vfe_dev, 
		msm_camera_io_w(0, vfe_dev->vfe_base + 0x64);

		msm_camera_io_w(1 << 0, vfe_dev->vfe_base + 0x68);

		msm_camera_io_w_mb(1, vfe_dev->vfe_base + 0x58);

		msm_vfe47_config_irq(vfe_dev, vfe_dev->irq0_mask,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

					vfe_dev->irq0_mask,

					vfe_dev->irq1_mask, MSM_ISP_IRQ_SET);



	}
@@ -1749,7 +1757,8 @@ int msm_vfe47_axi_halt(struct vfe_device *vfe_dev, 
	msm_camera_io_w(val, vfe_dev->vfe_vbif_base + VFE47_VBIF_CLK_OFFSET);



	/* Keep only halt and reset mask */

	msm_vfe47_config_irq(vfe_dev, (1 << 31), (1 << 8),

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				(1 << 31), (1 << 8),

				MSM_ISP_IRQ_SET);



	/*Clear IRQ Status0, only leave reset irq mask*/
@@ -1798,7 +1807,8 @@ int msm_vfe47_axi_halt(struct vfe_device *vfe_dev, 
void msm_vfe47_axi_restart(struct vfe_device *vfe_dev,

	uint32_t blocking, uint32_t enable_camif)

{

	msm_vfe47_config_irq(vfe_dev, vfe_dev->irq0_mask, vfe_dev->irq1_mask,

	vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				vfe_dev->irq0_mask, vfe_dev->irq1_mask,

				MSM_ISP_IRQ_SET);

	msm_camera_io_w(0x7FFFFFFF, vfe_dev->vfe_base + 0x64);

	msm_camera_io_w(0xFFFFFEFF, vfe_dev->vfe_base + 0x68);
@@ -1905,7 +1915,8 @@ void msm_vfe47_stats_cfg_comp_mask( 
		comp_mask_reg |= stats_mask << (request_comp_index * 16);

		atomic_set(stats_comp_mask, stats_mask |

				atomic_read(stats_comp_mask));

		msm_vfe47_config_irq(vfe_dev, 1 << (29 + request_comp_index),

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << (29 + request_comp_index),

				0, MSM_ISP_IRQ_ENABLE);

	} else {

		if (!(atomic_read(stats_comp_mask) & stats_mask))
@@ -1914,7 +1925,8 @@ void msm_vfe47_stats_cfg_comp_mask( 
		atomic_set(stats_comp_mask,

				~stats_mask & atomic_read(stats_comp_mask));

		comp_mask_reg &= ~(stats_mask << (request_comp_index * 16));

		msm_vfe47_config_irq(vfe_dev, 1 << (29 + request_comp_index),

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << (29 + request_comp_index),

				0, MSM_ISP_IRQ_DISABLE);

	}
@@ -1937,32 +1949,41 @@ void msm_vfe47_stats_cfg_wm_irq_mask( 


	switch (STATS_IDX(stream_info->stream_handle[vfe_idx])) {

	case STATS_COMP_IDX_AEC_BG:

		msm_vfe47_config_irq(vfe_dev, 1 << 15, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 15, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_HDR_BE:

		msm_vfe47_config_irq(vfe_dev, 1 << 16, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 16, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_BG:

		msm_vfe47_config_irq(vfe_dev, 1 << 17, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 17, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_BF:

		msm_vfe47_config_irq(vfe_dev, 1 << 18, 1 << 26,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 18, 1 << 26,

				MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_HDR_BHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 19, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 19, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_RS:

		msm_vfe47_config_irq(vfe_dev, 1 << 20, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 20, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_CS:

		msm_vfe47_config_irq(vfe_dev, 1 << 21, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 21, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_IHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 22, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 22, 0, MSM_ISP_IRQ_ENABLE);

		break;

	case STATS_COMP_IDX_BHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 23, 0, MSM_ISP_IRQ_ENABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 23, 0, MSM_ISP_IRQ_ENABLE);

		break;

	default:

		pr_err("%s: Invalid stats idx %d\n", __func__,
@@ -1979,32 +2000,41 @@ void msm_vfe47_stats_clear_wm_irq_mask( 


	switch (STATS_IDX(stream_info->stream_handle[vfe_idx])) {

	case STATS_COMP_IDX_AEC_BG:

		msm_vfe47_config_irq(vfe_dev, 1 << 15, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 15, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_HDR_BE:

		msm_vfe47_config_irq(vfe_dev, 1 << 16, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 16, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_BG:

		msm_vfe47_config_irq(vfe_dev, 1 << 17, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 17, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_BF:

		msm_vfe47_config_irq(vfe_dev, 1 << 18, 1 << 26,

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 18, 1 << 26,

				MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_HDR_BHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 19, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 19, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_RS:

		msm_vfe47_config_irq(vfe_dev, 1 << 20, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 20, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_CS:

		msm_vfe47_config_irq(vfe_dev, 1 << 21, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 21, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_IHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 22, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 22, 0, MSM_ISP_IRQ_DISABLE);

		break;

	case STATS_COMP_IDX_BHIST:

		msm_vfe47_config_irq(vfe_dev, 1 << 23, 0, MSM_ISP_IRQ_DISABLE);

		vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev,

				1 << 23, 0, MSM_ISP_IRQ_DISABLE);

		break;

	default:

		pr_err("%s: Invalid stats idx %d\n", __func__,

drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c

+16 −1
Original line number Diff line number Diff line
@@ -2270,13 +2270,14 @@ int msm_isp_axi_halt(struct vfe_device *vfe_dev, 
int msm_isp_axi_reset(struct vfe_device *vfe_dev,

	struct msm_vfe_axi_reset_cmd *reset_cmd)

{

	int rc = 0, i, k;

	int rc = 0, i, k, j;

	struct msm_vfe_axi_stream *stream_info;

	struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;

	uint32_t bufq_handle = 0, bufq_id = 0;

	struct msm_isp_timestamp timestamp;

	unsigned long flags;

	struct vfe_device *update_vfes[MAX_VFE] = {0, 0};

	int vfe_idx;



	if (!reset_cmd) {

		pr_err("%s: NULL pointer reset cmd %pK\n", __func__, reset_cmd);
@@ -2347,6 +2348,20 @@ int msm_isp_axi_reset(struct vfe_device *vfe_dev, 
						ISP_EVENT_BUF_FATAL_ERROR);

					return rc;

				}

				if (stream_info->num_planes > 1) {

					vfe_dev->hw_info->vfe_ops.axi_ops.

					cfg_comp_mask(vfe_dev, stream_info);

				} else {

					vfe_dev->hw_info->vfe_ops.axi_ops.

					cfg_wm_irq_mask(vfe_dev, stream_info);

				}

				vfe_idx = msm_isp_get_vfe_idx_for_stream(

							vfe_dev, stream_info);

				for (j = 0; j < stream_info->num_planes; j++)

					vfe_dev->hw_info->vfe_ops.axi_ops.

						enable_wm(

						vfe_dev->vfe_base,

						stream_info->wm[vfe_idx][j], 1);



				axi_data->src_info[SRC_TO_INTF(stream_info->

					stream_src)].frame_id =

drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c

+4 −0
Original line number Diff line number Diff line
@@ -904,6 +904,10 @@ int msm_isp_stats_reset(struct vfe_device *vfe_dev) 
					ISP_EVENT_BUF_FATAL_ERROR);

				return rc;

			}

			vfe_dev->hw_info->vfe_ops.stats_ops.cfg_wm_irq_mask(

					vfe_dev, stream_info);

			vfe_dev->hw_info->vfe_ops.stats_ops.enable_module(

				vfe_dev, BIT(i), 1);

		}

	}