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Commit 4e38e151 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: specify SPI configuration for msmfalcon."

parents 46f563dc e9f5e981

arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi

0 → 100644
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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include "msmfalcon-pinctrl.dtsi"



/ {

	aliases {

		spi1 = &spi_1;

		spi2 = &spi_2;

		spi3 = &spi_3;

		spi4 = &spi_4;

		spi5 = &spi_5;

		spi6 = &spi_6;

		spi7 = &spi_7;

		spi8 = &spi_8;

	};

};





&soc {

	spi_1: spi@c175000 { /* BLSP1 QUP1 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc175000 0x600>,

		      <0xc144000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 95 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <4>;

		qcom,bam-producer-pipe-index = <5>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_1_active>;

		pinctrl-1 = <&spi_1_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,

			 <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_2: spi@c176000 { /* BLSP1 QUP2 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc176000 0x600>,

		      <0xc144000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 96 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <6>;

		qcom,bam-producer-pipe-index = <7>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_2_active>;

		pinctrl-1 = <&spi_2_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,

			 <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_3: spi@c177000 { /* BLSP1 QUP3 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc177000 0x600>,

		      <0xc144000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 97 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <8>;

		qcom,bam-producer-pipe-index = <9>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_3_active>;

		pinctrl-1 = <&spi_3_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,

			 <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_4: spi@c178000 { /* BLSP1 QUP4 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc178000 0x600>,

		      <0xc144000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 98 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <10>;

		qcom,bam-producer-pipe-index = <11>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_4_active>;

		pinctrl-1 = <&spi_4_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,

			 <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_5: spi@c1b5000 { /* BLSP2 QUP1 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc1b5000 0x600>,

		      <0xc184000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 101 0>, <0 239 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <4>;

		qcom,bam-producer-pipe-index = <5>;

		qcom,master-id = <84>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_5_active>;

		pinctrl-1 = <&spi_5_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,

			 <&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_6: spi@c1b6000 { /* BLSP2 QUP2 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc1b6000 0x600>,

		      <0xc184000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 102 0>, <0 239 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <6>;

		qcom,bam-producer-pipe-index = <7>;

		qcom,master-id = <84>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_6_active>;

		pinctrl-1 = <&spi_6_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,

			 <&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_7: spi@c1b7000 { /* BLSP2 QUP3 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc1b7000 0x600>,

		      <0xc184000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 103 0>, <0 239 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <8>;

		qcom,bam-producer-pipe-index = <9>;

		qcom,master-id = <84>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_7_active>;

		pinctrl-1 = <&spi_7_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,

			 <&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>;

		status = "disabled";

	};



	spi_8: spi@c1b8000 { /* BLSP2 QUP4 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0xc1b8000 0x600>,

		      <0xc184000 0x1f000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 104 0>, <0 239 0>;

		spi-max-frequency = <50000000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <10>;

		qcom,bam-producer-pipe-index = <11>;

		qcom,master-id = <84>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_8_active>;

		pinctrl-1 = <&spi_8_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,

			 <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>;

		status = "disabled";

	};

};

arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi

+257 −0
Original line number Diff line number Diff line
@@ -112,5 +112,262 @@ 
				bias-pull-down; /* pull down */

			};

		};



		/* SPI CONFIGURATION */

		spi_1 {

			spi_1_active: spi_1_active {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "blsp_spi1";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_1_sleep: spi_1_sleep {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "blsp_spi1";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_2 {

			spi_2_active: spi_2_active {

				mux {

					pins = "gpio4", "gpio5",

							"gpio6", "gpio7";

					function = "blsp_spi2";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio6", "gpio7";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_2_sleep: spi_2_sleep {

				mux {

					pins = "gpio4", "gpio5",

							"gpio6", "gpio7";

					function = "blsp_spi2";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio6", "gpio7";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_3 {

			spi_3_active: spi_3_active {

				mux {

					pins = "gpio8", "gpio9",

							"gpio10", "gpio11";

					function = "blsp_spi3";

				};



				config {

					pins = "gpio8", "gpio9",

							"gpio10", "gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_3_sleep: spi_3_sleep {

				mux {

					pins = "gpio8", "gpio9",

							"gpio10", "gpio11";

					function = "blsp_spi3";

				};



				config {

					pins = "gpio8", "gpio9",

							"gpio10", "gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_4 {

			spi_4_active: spi_4_active {

				mux {

					pins = "gpio12", "gpio13",

							"gpio14", "gpio15";

					function = "blsp_spi4";

				};



				config {

					pins = "gpio12", "gpio13",

							"gpio14", "gpio15";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_4_sleep: spi_4_sleep {

				mux {

					pins = "gpio12", "gpio13",

							"gpio14", "gpio15";

					function = "blsp_spi4";

				};



				config {

					pins = "gpio12", "gpio13",

							"gpio14", "gpio15";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_5 {

			spi_5_active: spi_5_active {

				mux {

					pins = "gpio16", "gpio17",

							"gpio18", "gpio19";

					function = "blsp_spi5";

				};



				config {

					pins = "gpio16", "gpio17",

							"gpio18", "gpio19";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_5_sleep: spi_5_sleep {

				mux {

					pins = "gpio16", "gpio17",

							"gpio18", "gpio19";

					function = "blsp_spi5";

				};



				config {

					pins = "gpio16", "gpio17",

							"gpio18", "gpio19";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_6 {

			spi_6_active: spi_6_active {

				mux {

					pins = "gpio49", "gpio52",

							"gpio22", "gpio23";

					function = "blsp_spi6";

				};



				config {

					pins = "gpio49", "gpio52",

							"gpio22", "gpio23";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_6_sleep: spi_6_sleep {

				mux {

					pins = "gpio49", "gpio52",

							"gpio22", "gpio23";

					function = "blsp_spi6";

				};



				config {

					pins = "gpio49", "gpio52",

							"gpio22", "gpio23";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_7 {

			spi_7_active: spi_7_active {

				mux {

					pins = "gpio24", "gpio25",

							"gpio26", "gpio27";

					function = "blsp_spi7";

				};



				config {

					pins = "gpio24", "gpio25",

							"gpio26", "gpio27";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_7_sleep: spi_7_sleep {

				mux {

					pins = "gpio24", "gpio25",

							"gpio26", "gpio27";

					function = "blsp_spi7";

				};



				config {

					pins = "gpio24", "gpio25",

							"gpio26", "gpio27";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_8 {

			spi_8_active: spi_8_active {

				mux {

					pins = "gpio28", "gpio29",

							"gpio30", "gpio31";

					function = "blsp_spi8";

				};



				config {

					pins = "gpio28", "gpio29",

							"gpio30", "gpio31";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_8_sleep: spi_8_sleep {

				mux {

					pins = "gpio28", "gpio29",

							"gpio30", "gpio31";

					function = "blsp_spi8";

				};



				config {

					pins = "gpio28", "gpio29",

							"gpio30", "gpio31";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};

	};

};

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -899,3 +899,4 @@ 
#include "msm-pm2falcon.dtsi"

#include "msm-arm-smmu-falcon.dtsi"

#include "msm-arm-smmu-impl-defs-falcon.dtsi"

#include "msmfalcon-blsp.dtsi"