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Commit 4e258da2 authored by Pavankumar Kondeti's avatar Pavankumar Kondeti
Browse files

ARM: dts: msm: update CPU efficiency values for sdm660 



Update the CPU efficiency values as per the post silicon
data.

Change-Id: I69321cf5b4cf80d91f27744dd3da617354f3474d
Signed-off-by: default avatarPavankumar Kondeti <pkondeti@codeaurora.org>
parent 88fee0f3

arch/arm/boot/dts/qcom/sdm660.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ 
			qcom,limits-info = <&mitigation_profile1>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea4>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";
@@ -179,7 +179,7 @@ 
			qcom,limits-info = <&mitigation_profile2>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea5>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";
@@ -202,7 +202,7 @@ 
			qcom,limits-info = <&mitigation_profile3>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea6>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";
@@ -225,7 +225,7 @@ 
			qcom,limits-info = <&mitigation_profile4>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea7>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";