Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4c551536 authored by Vijayavardhan Vennapusa's avatar Vijayavardhan Vennapusa Committed by Gerrit - the friendly Code Review server
Browse files

USB: dwc3: msm: Fail probe if core-clk-rate is not passed from dts



Currently USB driver is not failing probe if USB core-clk-rate property
is not exist. This leads to USB enumeration failures across connect/
disconnect. Hence make core-clk-rate property mandatory and if in case
not defined, fail the probe. Also Fail probe if extcon property not
defined in case of OTG mode.

Also return error if dwc3_core_pre_init() fails during dwc3-msm_resume()
due to phy init fails and don't go ahead with setting up event buffers
as event buffers allocation is done.

Change-Id: I3927ad2f670e45acd10f8568857cf9f3434df657
Signed-off-by: default avatarVijayavardhan Vennapusa <vvreddy@codeaurora.org>
parent a80e267a
Loading
Loading
Loading
Loading
+18 −6
Original line number Diff line number Diff line
@@ -1748,6 +1748,7 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)
{
	struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3);
	u32 val;
	int ret;

	/* Configure AHB2PHY for one wait state read/write */
	if (mdwc->ahb2phy_base) {
@@ -1766,7 +1767,11 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)
	if (!mdwc->init) {
		dbg_event(0xFF, "dwc3 init",
				atomic_read(&mdwc->dev->power.usage_count));
		dwc3_core_pre_init(dwc);
		ret = dwc3_core_pre_init(dwc);
		if (ret) {
			dev_err(mdwc->dev, "dwc3_core_pre_init failed\n");
			return;
		}
		mdwc->init = true;
	}

@@ -2381,11 +2386,14 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc)
		return ret;
	}

	if (!of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate",
	if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate",
				(u32 *)&mdwc->core_clk_rate)) {
		dev_err(mdwc->dev, "USB core-clk-rate is not present\n");
		return -EINVAL;
	}

	mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk,
							mdwc->core_clk_rate);
	}

	dev_dbg(mdwc->dev, "USB core frequency = %ld\n",
						mdwc->core_clk_rate);
@@ -2529,8 +2537,12 @@ static int dwc3_msm_extcon_register(struct dwc3_msm *mdwc)
	struct extcon_dev *edev;
	int ret = 0;

	if (!of_property_read_bool(node, "extcon"))
	if (!of_property_read_bool(node, "extcon")) {
		if (usb_get_dr_mode(&mdwc->dwc3->dev) == USB_DR_MODE_HOST)
			return 0;
		dev_err(mdwc->dev, "extcon property doesn't exist\n");
		return -EINVAL;
	}

	edev = extcon_get_edev_by_phandle(mdwc->dev, 0);
	if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV)