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Commit 4b8fc9f2 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.4.82 into android-4.4 



Changes in 4.4.82
	tcp: avoid setting cwnd to invalid ssthresh after cwnd reduction states
	net: fix keepalive code vs TCP_FASTOPEN_CONNECT
	bpf, s390: fix jit branch offset related to ldimm64
	net: sched: set xt_tgchk_param par.nft_compat as 0 in ipt_init_target
	tcp: fastopen: tcp_connect() must refresh the route
	net: avoid skb_warn_bad_offload false positives on UFO
	packet: fix tp_reserve race in packet_set_ring
	revert "net: account for current skb length when deciding about UFO"
	revert "ipv4: Should use consistent conditional judgement for ip fragment in __ip_append_data and ip_finish_output"
	udp: consistently apply ufo or fragmentation
	sparc64: Prevent perf from running during super critical sections
	KVM: arm/arm64: Handle hva aging while destroying the vm
	mm/mempool: avoid KASAN marking mempool poison checks as use-after-free
	ipv4: Should use consistent conditional judgement for ip fragment in __ip_append_data and ip_finish_output
	net: account for current skb length when deciding about UFO
	Linux 4.4.82

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 286f536c 4e2e415f

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 81

SUBLEVEL = 82

EXTRAVERSION =

NAME = Blurry Fish Butt

arch/arm/kvm/mmu.c

+4 −0
Original line number Diff line number Diff line
@@ -1629,12 +1629,16 @@ static int kvm_test_age_hva_handler(struct kvm *kvm, gpa_t gpa, void *data) 


int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)

{

	if (!kvm->arch.pgd)

		return 0;

	trace_kvm_age_hva(start, end);

	return handle_hva_to_gpa(kvm, start, end, kvm_age_hva_handler, NULL);

}



int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)

{

	if (!kvm->arch.pgd)

		return 0;

	trace_kvm_test_age_hva(hva);

	return handle_hva_to_gpa(kvm, hva, hva, kvm_test_age_hva_handler, NULL);

}

arch/s390/net/bpf_jit_comp.c

+2 −1
Original line number Diff line number Diff line
@@ -1250,7 +1250,8 @@ static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 
		insn_count = bpf_jit_insn(jit, fp, i);

		if (insn_count < 0)

			return -1;

		jit->addrs[i + 1] = jit->prg; /* Next instruction address */

		/* Next instruction address */

		jit->addrs[i + insn_count] = jit->prg;

	}

	bpf_jit_epilogue(jit);

arch/sparc/include/asm/mmu_context_64.h

+9 −5
Original line number Diff line number Diff line
@@ -25,9 +25,11 @@ void destroy_context(struct mm_struct *mm); 
void __tsb_context_switch(unsigned long pgd_pa,

			  struct tsb_config *tsb_base,

			  struct tsb_config *tsb_huge,

			  unsigned long tsb_descr_pa);

			  unsigned long tsb_descr_pa,

			  unsigned long secondary_ctx);



static inline void tsb_context_switch(struct mm_struct *mm)

static inline void tsb_context_switch_ctx(struct mm_struct *mm,

					  unsigned long ctx)

{

	__tsb_context_switch(__pa(mm->pgd),

			     &mm->context.tsb_block[0],
@@ -38,9 +40,12 @@ static inline void tsb_context_switch(struct mm_struct *mm) 
#else

			     NULL

#endif

			     , __pa(&mm->context.tsb_descr[0]));

			     , __pa(&mm->context.tsb_descr[0]),

			     ctx);

}



#define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)



void tsb_grow(struct mm_struct *mm,

	      unsigned long tsb_index,

	      unsigned long mm_rss);
@@ -110,8 +115,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str 
	 * cpu0 to update it's TSB because at that point the cpu_vm_mask

	 * only had cpu1 set in it.

	 */

	load_secondary_context(mm);

	tsb_context_switch(mm);

	tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));



	/* Any time a processor runs a context on an address space

	 * for the first time, we must flush that context out of the

arch/sparc/kernel/tsb.S

+12 −0
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ tsb_flush: 
	 * %o1:	TSB base config pointer

	 * %o2:	TSB huge config pointer, or NULL if none

	 * %o3:	Hypervisor TSB descriptor physical address

	 * %o4: Secondary context to load, if non-zero

	 *

	 * We have to run this whole thing with interrupts

	 * disabled so that the current cpu doesn't change
@@ -387,6 +388,17 @@ __tsb_context_switch: 
	rdpr	%pstate, %g1

	wrpr	%g1, PSTATE_IE, %pstate



	brz,pn	%o4, 1f

	 mov	SECONDARY_CONTEXT, %o5



661:	stxa	%o4, [%o5] ASI_DMMU

	.section .sun4v_1insn_patch, "ax"

	.word	661b

	stxa	%o4, [%o5] ASI_MMU

	.previous

	flush	%g6



1:

	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)



	stx	%o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]