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Commit 4b30b870 authored by Dave Airlie's avatar Dave Airlie
Browse files

drm/radeon/kms: fix divide by 0 in clocks code 



If the chip isn't initialised properly this can happen.
also fix return value in combios clocks function.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7dde8a19

drivers/gpu/drm/radeon/radeon_clocks.c

+8 −0
Original line number Diff line number Diff line
@@ -44,6 +44,10 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) 


	ref_div =

	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;



	if (ref_div == 0)

		return 0;



	sclk = fb_div / ref_div;



	post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
@@ -70,6 +74,10 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 


	ref_div =

	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;



	if (ref_div == 0)

		return 0;



	mclk = fb_div / ref_div;



	post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;

drivers/gpu/drm/radeon/radeon_combios.c

+1 −1
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ bool radeon_combios_get_clock_info(struct drm_device *dev) 
	uint16_t sclk, mclk;



	if (rdev->bios == NULL)

		return NULL;

		return false;



	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);

	if (pll_info) {