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Commit 48c0c902 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add support for CP setup on SI 



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 8b074dd6

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \

	radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \

	radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o

	radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o si_blit_shaders.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/si.c

+267 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "radeon_drm.h"

#include "sid.h"

#include "atom.h"

#include "si_blit_shaders.h"



#define SI_PFP_UCODE_SIZE 2144

#define SI_PM4_UCODE_SIZE 2144
@@ -1861,6 +1862,272 @@ static void si_gpu_init(struct radeon_device *rdev) 
	udelay(50);

}



/*

 * CP.

 */

static void si_cp_enable(struct radeon_device *rdev, bool enable)

{

	if (enable)

		WREG32(CP_ME_CNTL, 0);

	else {

		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

		WREG32(SCRATCH_UMSK, 0);

	}

	udelay(50);

}



static int si_cp_load_microcode(struct radeon_device *rdev)

{

	const __be32 *fw_data;

	int i;



	if (!rdev->me_fw || !rdev->pfp_fw)

		return -EINVAL;



	si_cp_enable(rdev, false);



	/* PFP */

	fw_data = (const __be32 *)rdev->pfp_fw->data;

	WREG32(CP_PFP_UCODE_ADDR, 0);

	for (i = 0; i < SI_PFP_UCODE_SIZE; i++)

		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

	WREG32(CP_PFP_UCODE_ADDR, 0);



	/* CE */

	fw_data = (const __be32 *)rdev->ce_fw->data;

	WREG32(CP_CE_UCODE_ADDR, 0);

	for (i = 0; i < SI_CE_UCODE_SIZE; i++)

		WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));

	WREG32(CP_CE_UCODE_ADDR, 0);



	/* ME */

	fw_data = (const __be32 *)rdev->me_fw->data;

	WREG32(CP_ME_RAM_WADDR, 0);

	for (i = 0; i < SI_PM4_UCODE_SIZE; i++)

		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

	WREG32(CP_ME_RAM_WADDR, 0);



	WREG32(CP_PFP_UCODE_ADDR, 0);

	WREG32(CP_CE_UCODE_ADDR, 0);

	WREG32(CP_ME_RAM_WADDR, 0);

	WREG32(CP_ME_RAM_RADDR, 0);

	return 0;

}



static int si_cp_start(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	int r, i;



	r = radeon_ring_lock(rdev, ring, 7 + 4);

	if (r) {

		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);

		return r;

	}

	/* init the CP */

	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

	radeon_ring_write(ring, 0x1);

	radeon_ring_write(ring, 0x0);

	radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);

	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);



	/* init the CE partitions */

	radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

	radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));

	radeon_ring_write(ring, 0xc000);

	radeon_ring_write(ring, 0xe000);

	radeon_ring_unlock_commit(rdev, ring);



	si_cp_enable(rdev, true);



	r = radeon_ring_lock(rdev, ring, si_default_size + 10);

	if (r) {

		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);

		return r;

	}



	/* setup clear context state */

	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);



	for (i = 0; i < si_default_size; i++)

		radeon_ring_write(ring, si_default_state[i]);



	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);



	/* set clear context state */

	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

	radeon_ring_write(ring, 0);



	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

	radeon_ring_write(ring, 0x00000316);

	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */



	radeon_ring_unlock_commit(rdev, ring);



	for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {

		ring = &rdev->ring[i];

		r = radeon_ring_lock(rdev, ring, 2);



		/* clear the compute context state */

		radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));

		radeon_ring_write(ring, 0);



		radeon_ring_unlock_commit(rdev, ring);

	}



	return 0;

}



static void si_cp_fini(struct radeon_device *rdev)

{

	si_cp_enable(rdev, false);

	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);

	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);

	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);

}



static int si_cp_resume(struct radeon_device *rdev)

{

	struct radeon_ring *ring;

	u32 tmp;

	u32 rb_bufsz;

	int r;



	/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */

	WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |

				 SOFT_RESET_PA |

				 SOFT_RESET_VGT |

				 SOFT_RESET_SPI |

				 SOFT_RESET_SX));

	RREG32(GRBM_SOFT_RESET);

	mdelay(15);

	WREG32(GRBM_SOFT_RESET, 0);

	RREG32(GRBM_SOFT_RESET);



	WREG32(CP_SEM_WAIT_TIMER, 0x0);

	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);



	/* Set the write pointer delay */

	WREG32(CP_RB_WPTR_DELAY, 0);



	WREG32(CP_DEBUG, 0);

	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);



	/* ring 0 - compute and gfx */

	/* Set ring buffer size */

	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB0_CNTL, tmp);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB0_WPTR, ring->wptr);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);



	if (rdev->wb.enabled)

		WREG32(SCRATCH_UMSK, 0xff);

	else {

		tmp |= RB_NO_UPDATE;

		WREG32(SCRATCH_UMSK, 0);

	}



	mdelay(1);

	WREG32(CP_RB0_CNTL, tmp);



	WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB0_RPTR);



	/* ring1  - compute only */

	/* Set ring buffer size */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB1_CNTL, tmp);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB1_WPTR, ring->wptr);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);



	mdelay(1);

	WREG32(CP_RB1_CNTL, tmp);



	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB1_RPTR);



	/* ring2 - compute only */

	/* Set ring buffer size */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB2_CNTL, tmp);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB2_WPTR, ring->wptr);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);



	mdelay(1);

	WREG32(CP_RB2_CNTL, tmp);



	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB2_RPTR);



	/* start the rings */

	si_cp_start(rdev);

	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;

	rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;

	rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;

	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);

	if (r) {

		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

		rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;

		rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;

		return r;

	}

	r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);

	if (r) {

		rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;

	}

	r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);

	if (r) {

		rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;

	}



	return 0;

}



bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)

{

	u32 srbm_status;

drivers/gpu/drm/radeon/si_blit_shaders.c

0 → 100644
+252 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * Authors:

 *     Alex Deucher <alexander.deucher@amd.com>

 */



#include <linux/types.h>

#include <linux/kernel.h>



const u32 si_default_state[] =

{

	0xc0066900,

	0x00000000,

	0x00000060, /* DB_RENDER_CONTROL */

	0x00000000, /* DB_COUNT_CONTROL */

	0x00000000, /* DB_DEPTH_VIEW */

	0x0000002a, /* DB_RENDER_OVERRIDE */

	0x00000000, /* DB_RENDER_OVERRIDE2 */

	0x00000000, /* DB_HTILE_DATA_BASE */



	0xc0046900,

	0x00000008,

	0x00000000, /* DB_DEPTH_BOUNDS_MIN */

	0x00000000, /* DB_DEPTH_BOUNDS_MAX */

	0x00000000, /* DB_STENCIL_CLEAR */

	0x00000000, /* DB_DEPTH_CLEAR */



	0xc0036900,

	0x0000000f,

	0x00000000, /* DB_DEPTH_INFO */

	0x00000000, /* DB_Z_INFO */

	0x00000000, /* DB_STENCIL_INFO */



	0xc0016900,

	0x00000080,

	0x00000000, /* PA_SC_WINDOW_OFFSET */



	0xc00d6900,

	0x00000083,

	0x0000ffff, /* PA_SC_CLIPRECT_RULE */

	0x00000000, /* PA_SC_CLIPRECT_0_TL */

	0x20002000, /* PA_SC_CLIPRECT_0_BR */

	0x00000000,

	0x20002000,

	0x00000000,

	0x20002000,

	0x00000000,

	0x20002000,

	0xaaaaaaaa, /* PA_SC_EDGERULE */

	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */

	0x0000000f, /* CB_TARGET_MASK */

	0x0000000f, /* CB_SHADER_MASK */



	0xc0226900,

	0x00000094,

	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */

	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x00000000, /* PA_SC_VPORT_ZMIN_0 */

	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */



	0xc0026900,

	0x000000d9,

	0x00000000, /* CP_RINGID */

	0x00000000, /* CP_VMID */



	0xc0046900,

	0x00000100,

	0xffffffff, /* VGT_MAX_VTX_INDX */

	0x00000000, /* VGT_MIN_VTX_INDX */

	0x00000000, /* VGT_INDX_OFFSET */

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */



	0xc0046900,

	0x00000105,

	0x00000000, /* CB_BLEND_RED */

	0x00000000, /* CB_BLEND_GREEN */

	0x00000000, /* CB_BLEND_BLUE */

	0x00000000, /* CB_BLEND_ALPHA */



	0xc0016900,

	0x000001e0,

	0x00000000, /* CB_BLEND0_CONTROL */



	0xc00e6900,

	0x00000200,

	0x00000000, /* DB_DEPTH_CONTROL */

	0x00000000, /* DB_EQAA */

	0x00cc0010, /* CB_COLOR_CONTROL */

	0x00000210, /* DB_SHADER_CONTROL */

	0x00010000, /* PA_CL_CLIP_CNTL */

	0x00000004, /* PA_SU_SC_MODE_CNTL */

	0x00000100, /* PA_CL_VTE_CNTL */

	0x00000000, /* PA_CL_VS_OUT_CNTL */

	0x00000000, /* PA_CL_NANINF_CNTL */

	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */

	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */

	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */

	0x00000000, /*  */

	0x00000000, /*  */



	0xc0116900,

	0x00000280,

	0x00000000, /* PA_SU_POINT_SIZE */

	0x00000000, /* PA_SU_POINT_MINMAX */

	0x00000008, /* PA_SU_LINE_CNTL */

	0x00000000, /* PA_SC_LINE_STIPPLE */

	0x00000000, /* VGT_OUTPUT_PATH_CNTL */

	0x00000000, /* VGT_HOS_CNTL */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000, /* VGT_GS_MODE */



	0xc0026900,

	0x00000292,

	0x00000000, /* PA_SC_MODE_CNTL_0 */

	0x00000000, /* PA_SC_MODE_CNTL_1 */



	0xc0016900,

	0x000002a1,

	0x00000000, /* VGT_PRIMITIVEID_EN */



	0xc0016900,

	0x000002a5,

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */



	0xc0026900,

	0x000002a8,

	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */

	0x00000000,



	0xc0026900,

	0x000002ad,

	0x00000000, /* VGT_REUSE_OFF */

	0x00000000,



	0xc0016900,

	0x000002d5,

	0x00000000, /* VGT_SHADER_STAGES_EN */



	0xc0016900,

	0x000002dc,

	0x0000aa00, /* DB_ALPHA_TO_MASK */



	0xc0066900,

	0x000002de,

	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0026900,

	0x000002e5,

	0x00000000, /* VGT_STRMOUT_CONFIG */

	0x00000000,



	0xc01b6900,

	0x000002f5,

	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */

	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */

	0x00000000, /* PA_SC_LINE_CNTL */

	0x00000000, /* PA_SC_AA_CONFIG */

	0x00000005, /* PA_SU_VTX_CNTL */

	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */

	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */

	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */

	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */

	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */

	0xffffffff,



	0xc0026900,

	0x00000316,

	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	0x00000010, /*  */

};



const u32 si_default_size = ARRAY_SIZE(si_default_state);

drivers/gpu/drm/radeon/si_blit_shaders.h

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef SI_BLIT_SHADERS_H

#define SI_BLIT_SHADERS_H



extern const u32 si_default_state[];



extern const u32 si_default_size;



#endif

drivers/gpu/drm/radeon/sid.h

+55 −0
Original line number Diff line number Diff line
@@ -273,12 +273,31 @@ 


#define GRBM_GFX_INDEX          			0x802C



#define	SCRATCH_REG0					0x8500

#define	SCRATCH_REG1					0x8504

#define	SCRATCH_REG2					0x8508

#define	SCRATCH_REG3					0x850C

#define	SCRATCH_REG4					0x8510

#define	SCRATCH_REG5					0x8514

#define	SCRATCH_REG6					0x8518

#define	SCRATCH_REG7					0x851C



#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_ADDR					0x8544



#define	CP_SEM_WAIT_TIMER				0x85BC



#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8



#define CP_ME_CNTL					0x86D8

#define		CP_CE_HALT					(1 << 24)

#define		CP_PFP_HALT					(1 << 26)

#define		CP_ME_HALT					(1 << 28)



#define	CP_RB2_RPTR					0x86f8

#define	CP_RB1_RPTR					0x86fc

#define	CP_RB0_RPTR					0x8700

#define	CP_RB_WPTR_DELAY				0x8704



#define	CP_QUEUE_THRESHOLDS				0x8760

#define		ROQ_IB1_START(x)				((x) << 0)
@@ -458,6 +477,40 @@ 
#define	TCP_CHAN_STEER_LO				0xac0c

#define	TCP_CHAN_STEER_HI				0xac10



#define	CP_RB0_BASE					0xC100

#define	CP_RB0_CNTL					0xC104

#define		RB_BUFSZ(x)					((x) << 0)

#define		RB_BLKSZ(x)					((x) << 8)

#define		BUF_SWAP_32BIT					(2 << 16)

#define		RB_NO_UPDATE					(1 << 27)

#define		RB_RPTR_WR_ENA					(1 << 31)



#define	CP_RB0_RPTR_ADDR				0xC10C

#define	CP_RB0_RPTR_ADDR_HI				0xC110

#define	CP_RB0_WPTR					0xC114



#define	CP_PFP_UCODE_ADDR				0xC150

#define	CP_PFP_UCODE_DATA				0xC154

#define	CP_ME_RAM_RADDR					0xC158

#define	CP_ME_RAM_WADDR					0xC15C

#define	CP_ME_RAM_DATA					0xC160



#define	CP_CE_UCODE_ADDR				0xC168

#define	CP_CE_UCODE_DATA				0xC16C



#define	CP_RB1_BASE					0xC180

#define	CP_RB1_CNTL					0xC184

#define	CP_RB1_RPTR_ADDR				0xC188

#define	CP_RB1_RPTR_ADDR_HI				0xC18C

#define	CP_RB1_WPTR					0xC190

#define	CP_RB2_BASE					0xC194

#define	CP_RB2_CNTL					0xC198

#define	CP_RB2_RPTR_ADDR				0xC19C

#define	CP_RB2_RPTR_ADDR_HI				0xC1A0

#define	CP_RB2_WPTR					0xC1A4



#define	CP_DEBUG					0xC1FC



/*

 * PM4

 */
@@ -483,6 +536,8 @@ 
			 (((op) & 0xFF) << 8) |				\

			 ((n) & 0x3FFF) << 16)



#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)



/* Packet 3 types */

#define	PACKET3_NOP					0x10

#define	PACKET3_SET_BASE				0x11