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Commit 47d8417f authored by Eran Ben Elisha's avatar Eran Ben Elisha Committed by David S. Miller
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net/mlx4_core: Add sink counter



Reserve the last valid counter index for "sink" counter, when a
new counter cannot be allocated, the driver will use this counter.

In order to avoid allocating this counter on any other flow, fix the
indices bitmap allocation range, and reserve the sink counter index.

Add macro for the sink counter index and replace all appearences of the
index with the macro.

Signed-off-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarHadar Hen Zion <hadarh@mellanox.com>
Signed-off-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b72ca7e9
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+2 −1
Original line number Original line Diff line number Diff line
@@ -1544,7 +1544,8 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
						dev->counters[qp->port - 1];
						dev->counters[qp->port - 1];
			optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
			optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
		} else
		} else
			context->pri_path.counter_index = 0xff;
			context->pri_path.counter_index =
				MLX4_SINK_COUNTER_INDEX(dev->dev);


		if (qp->flags & MLX4_IB_QP_NETIF) {
		if (qp->flags & MLX4_IB_QP_NETIF) {
			mlx4_ib_steer_qp_reg(dev, qp, 1);
			mlx4_ib_steer_qp_reg(dev, qp, 1);
+1 −1
Original line number Original line Diff line number Diff line
@@ -66,7 +66,7 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
		context->pri_path.sched_queue |= user_prio << 3;
		context->pri_path.sched_queue |= user_prio << 3;
		context->pri_path.feup = MLX4_FEUP_FORCE_ETH_UP;
		context->pri_path.feup = MLX4_FEUP_FORCE_ETH_UP;
	}
	}
	context->pri_path.counter_index = 0xff;
	context->pri_path.counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
	context->cqn_send = cpu_to_be32(cqn);
	context->cqn_send = cpu_to_be32(cqn);
	context->cqn_recv = cpu_to_be32(cqn);
	context->cqn_recv = cpu_to_be32(cqn);
	context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2);
	context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2);
+7 −4
Original line number Original line Diff line number Diff line
@@ -479,7 +479,7 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
		}
		}
	}
	}


	dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
	dev->caps.max_counters = dev_cap->max_counters;


	dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
	dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
	dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
	dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
@@ -2193,13 +2193,16 @@ err_free_icm:
static int mlx4_init_counters_table(struct mlx4_dev *dev)
static int mlx4_init_counters_table(struct mlx4_dev *dev)
{
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_priv *priv = mlx4_priv(dev);
	int nent;
	int nent_pow2;


	if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
	if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
		return -ENOENT;
		return -ENOENT;


	nent = dev->caps.max_counters;
	nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
	return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
	/* reserve last counter index for sink counter */
	return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
				nent_pow2 - 1, 0,
				nent_pow2 - dev->caps.max_counters + 1);
}
}


static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
+1 −0
Original line number Original line Diff line number Diff line
@@ -957,6 +957,7 @@ struct mlx4_mad_ifc {
			((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
			((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))


#define MLX4_INVALID_SLAVE_ID	0xFF
#define MLX4_INVALID_SLAVE_ID	0xFF
#define MLX4_SINK_COUNTER_INDEX(dev)	(dev->caps.max_counters - 1)


void handle_port_mgmt_change_event(struct work_struct *work);
void handle_port_mgmt_change_event(struct work_struct *work);