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Commit 406019ef authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Update clock gfx node for MSMfalcon/Triton 



Modify the clock_gfx dummy clock to use the real clock controller for all
gpu clock controller clients.

Change-Id: If3c707877f2a0da04065b57a1c2fd44d256a5303
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 98e734e0

arch/arm/boot/dts/qcom/msmfalcon-rumi.dts

+5 −0
Original line number Diff line number Diff line
@@ -102,3 +102,8 @@ 
&pmfalcon_fg {

	status = "disabled";

};



&clock_gfx {

	compatible = "qcom,dummycc";

	clock-output-names = "gfx_clocks";

};

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+17 −6
Original line number Diff line number Diff line
@@ -467,8 +467,21 @@ 
	};



	clock_gfx: clock-controller@5065000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gfx_clocks";

		compatible = "qcom,gpucc-msmfalcon";

		reg = <0x5065000 0x10000>;

		vdd_dig_gfx-supply = <&pm2falcon_s3_level>;

		vdd_mx_gfx-supply = <&pm2falcon_s5_level>;

		vdd_gfx-supply = <&gfx_vreg_corner>;

		qcom,gfxfreq-corner =

			< 0         0>,

			< 160000000 1>,  /* MinSVS */

			< 266000000 2>,  /* LowSVS */

			< 370000000 3>,  /* SVS    */

			< 465000000 4>,  /* SVS_L1 */

			< 588000000 5>,  /* NOM    */

			< 647000000 6>,  /* NOM_L1 */

			< 700000000 7>,  /* TURBO */

			< 750000000 7>;  /* TURBO  */

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -985,10 +998,8 @@ 
};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,

		 <&clock_gfx GPUCC_GFX3D_CLK>,

		 <&clock_gfx GFX3D_CLK_SRC>;

	clock-names = "core_root_clk";

	clocks = <&clock_gfx GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	parent-supply = <&gfx_vreg_corner>;

	status = "ok";

arch/arm/boot/dts/qcom/msmtriton-rumi.dts

+5 −0
Original line number Diff line number Diff line
@@ -63,3 +63,8 @@ 
	compatible = "qcom,dummycc";

	clock-output-names = "gcc_clocks";

};



&clock_gfx {

	compatible = "qcom,dummycc";

	clock-output-names = "gfx_clocks";

};

arch/arm/boot/dts/qcom/msmtriton.dtsi

+17 −6
Original line number Diff line number Diff line
@@ -382,8 +382,21 @@ 
	};



	clock_gfx: clock-controller@5065000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gfx_clocks";

		compatible = "qcom,gpucc-msmfalcon";

		reg = <0x5065000 0x10000>;

		vdd_dig_gfx-supply = <&pm2falcon_s3_level>;

		vdd_mx_gfx-supply = <&pm2falcon_s5_level>;

		vdd_gfx-supply = <&gfx_vreg_corner>;

		qcom,gfxfreq-corner =

			< 0         0>,

			< 160000000 1>,  /* MinSVS */

			< 266000000 2>,  /* LowSVS */

			< 370000000 3>,  /* SVS    */

			< 465000000 4>,  /* SVS_L1 */

			< 588000000 5>,  /* NOM    */

			< 647000000 6>,  /* NOM_L1 */

			< 700000000 7>,  /* TURBO  */

			< 750000000 7>;  /* TURBO  */

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -794,10 +807,8 @@ 
};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,

		 <&clock_gfx GPUCC_GFX3D_CLK>,

		 <&clock_gfx GFX3D_CLK_SRC>;

	clock-names = "core_root_clk";

	clocks = <&clock_gfx GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	parent-supply = <&gfx_vreg_corner>;

	status = "ok";