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Commit 3f5515f1 authored by Brahmaji K's avatar Brahmaji K
Browse files

ARM: dts: msm: Add crypto device node for msmfalcon 



Add qcrypto and qcedev device nodes with all the necessary
parameters, to enable crypto drivers on msmfalcon.

Change-Id: I9d9d4eeeb5ee41ff8a61676b19bb01b9280ae7ca
Signed-off-by: default avatarBrahmaji K <bkomma@codeaurora.org>
parent b832093b

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+63 −4
Original line number Diff line number Diff line
@@ -1274,13 +1274,72 @@ 
			<55 512 400000 1000000>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>,

			<&clock_gcc QSEECOM_CE1_CLK>;

		clocks = <&clock_rpmcc QSEECOM_CE1_CLK>,

			<&clock_rpmcc QSEECOM_CE1_CLK>,

			<&clock_rpmcc QSEECOM_CE1_CLK>,

			<&clock_rpmcc QSEECOM_CE1_CLK>;

		qcom,ce-opp-freq = <171430000>;

		qcom,qsee-reentrancy-support = <2>;

	};



	qcom_cedev: qcedev@1de0000{

		compatible = "qcom,qcedev";

		reg = <0x1de0000 0x20000>,

			<0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,bam-ee = <0>;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_rpmcc QCEDEV_CE1_CLK>,

			 <&clock_rpmcc QCEDEV_CE1_CLK>,

			 <&clock_rpmcc QCEDEV_CE1_CLK>,

			 <&clock_rpmcc QCEDEV_CE1_CLK>;

		qcom,ce-opp-freq = <171430000>;

	};



	qcom_crypto: qcrypto@1de0000 {

		compatible = "qcom,qcrypto";

		reg = <0x1de0000 0x20000>,

			 <0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,bam-ee = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<55 512 0 0>,

			<55 512 393600 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>,

			 <&clock_rpmcc QCRYPTO_CE1_CLK>,

			 <&clock_rpmcc QCRYPTO_CE1_CLK>,

			 <&clock_rpmcc QCRYPTO_CE1_CLK>;

		qcom,ce-opp-freq = <171430000>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-aead-algo;

		qcom,use-sw-hmac-algo;

	};

};



#include "msmfalcon-ion.dtsi"