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Commit 3c5a62b5 authored by Yuanhan Liu's avatar Yuanhan Liu Committed by Chris Wilson
Browse files

drm/i915: fix calculation of eDP signal levels on Sandybridge 



Some voltage swing/pre-emphasis level use the same value on eDP
Sandybridge, like 400mv_0db and 600mv_0db are with the same value
of (0x0 << 22). So, fix them, and point out the value if it isn't
a supported voltage swing/pre-emphasis level.

Signed-off-by: default avatarYuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
parent f5afcd3d

drivers/gpu/drm/i915/i915_reg.h

+5 −4
Original line number Diff line number Diff line
@@ -3174,10 +3174,11 @@ 
#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)

#define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)

/* SNB B-stepping */

#define  EDP_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)

#define  EDP_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)

#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)

#define  EDP_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)

#define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)

#define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)

#define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)

#define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)

#define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)

#define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)



#define  FORCEWAKE				0xA18C

drivers/gpu/drm/i915/intel_dp.c

+16 −7
Original line number Diff line number Diff line
@@ -1153,18 +1153,27 @@ intel_dp_signal_levels(uint8_t train_set, int lane_count) 
static uint32_t

intel_gen6_edp_signal_levels(uint8_t train_set)

{

	switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {

	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |

					 DP_TRAIN_PRE_EMPHASIS_MASK);

	switch (signal_levels) {

	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:

		return EDP_LINK_TRAIN_400MV_0DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:

		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:

		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:

		return EDP_LINK_TRAIN_400MV_6DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:

		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:

		return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:

		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:

		return EDP_LINK_TRAIN_800MV_0DB_SNB_B;

	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:

		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;

	default:

		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");

		return EDP_LINK_TRAIN_400MV_0DB_SNB_B;

		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"

			      "0x%x\n", signal_levels);

		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;

	}

}