Merge "qpnp-fg-gen3: use IMA single mode for pm660 fuel gauge" (3b758d49) · Commits · e / devices / android_kernel_sony_msm8998

drivers/iio/adc/qcom-rradc.c

+4 −9

Original line number	Diff line number	Diff line
		@@ -164,11 +164,6 @@
		#define FG_ADC_RR_DIE_TEMP_SLOPE 2
		#define FG_ADC_RR_DIE_TEMP_OFFSET_MILLI_DEGC 25000

		#define FAB_ID_GF 0x30
		#define FAB_ID_SMIC 0x11
		#define FAB_ID_660_GF 0x0
		#define FAB_ID_660_TSMC 0x2
		#define FAB_ID_660_MX 0x3
		#define FG_ADC_RR_CHG_TEMP_GF_OFFSET_UV 1303168
		#define FG_ADC_RR_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
		#define FG_ADC_RR_CHG_TEMP_SMIC_OFFSET_UV 1338433
		@@ -402,11 +397,11 @@ static int rradc_get_660_fab_coeff(struct rradc_chip *chip,
		int64_t offset, int64_t slope)
		{
		switch (chip->pmic_fab_id->fab_id) {
		case FAB_ID_660_GF:
		case PM660_FAB_ID_GF:
		*offset = FG_ADC_RR_CHG_TEMP_660_GF_OFFSET_UV;
		*slope = FG_RR_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
		break;
		case FAB_ID_660_TSMC:
		case PM660_FAB_ID_TSMC:
		*offset = FG_ADC_RR_CHG_TEMP_660_SMIC_OFFSET_UV;
		*slope = FG_RR_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
		break;
		@@ -422,11 +417,11 @@ static int rradc_get_8998_fab_coeff(struct rradc_chip *chip,
		int64_t offset, int64_t slope)
		{
		switch (chip->pmic_fab_id->fab_id) {
		case FAB_ID_GF:
		case PMI8998_FAB_ID_GF:
		*offset = FG_ADC_RR_CHG_TEMP_GF_OFFSET_UV;
		*slope = FG_ADC_RR_CHG_TEMP_GF_SLOPE_UV_PER_C;
		break;
		case FAB_ID_SMIC:
		case PMI8998_FAB_ID_SMIC:
		*offset = FG_ADC_RR_CHG_TEMP_SMIC_OFFSET_UV;
		*slope = FG_ADC_RR_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
		break;

drivers/power/supply/qcom/fg-core.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -372,6 +372,7 @@ struct fg_chip {
		bool esr_flt_cold_temp_en;
		bool bsoc_delta_irq_en;
		bool slope_limit_en;
		bool use_ima_single_mode;
		struct completion soc_update;
		struct completion soc_ready;
		struct delayed_work profile_load_work;

drivers/power/supply/qcom/fg-memif.c

+59 −19

Original line number	Diff line number	Diff line
		@@ -48,6 +48,10 @@ static int fg_config_access_mode(struct fg_chip *chip, bool access, bool burst)
		int rc;
		u8 intf_ctl = 0;

		fg_dbg(chip, FG_SRAM_READ \| FG_SRAM_WRITE, "access: %d burst: %d\n",
		access, burst);

		WARN_ON(burst && chip->use_ima_single_mode);
		intf_ctl = ((access == FG_WRITE) ? IMA_WR_EN_BIT : 0) \|
		(burst ? MEM_ACS_BURST_BIT : 0);

		@@ -293,7 +297,9 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
		/* check for error condition */
		rc = fg_clear_ima_errors_if_any(chip, false);
		if (rc < 0) {
		pr_err("Failed to check for ima errors rc=%d\n", rc);
		if (rc != -EAGAIN)
		pr_err("Failed to check for ima errors rc=%d\n",
		rc);
		return rc;
		}

		@@ -357,7 +363,12 @@ static int __fg_interleaved_mem_write(struct fg_chip *chip, u16 address,
		/* check for error condition */
		rc = fg_clear_ima_errors_if_any(chip, false);
		if (rc < 0) {
		pr_err("Failed to check for ima errors rc=%d\n", rc);
		if (rc == -EAGAIN)
		pr_err("IMA error cleared, address [%d %d] len %d\n",
		address, offset, len);
		else
		pr_err("Failed to check for ima errors rc=%d\n",
		rc);
		return rc;
		}

		@@ -365,6 +376,15 @@ static int __fg_interleaved_mem_write(struct fg_chip *chip, u16 address,
		len -= num_bytes;
		offset = byte_enable = 0;

		if (chip->use_ima_single_mode && len) {
		address++;
		rc = fg_set_address(chip, address);
		if (rc < 0) {
		pr_err("failed to set address rc = %d\n", rc);
		return rc;
		}
		}

		rc = fg_check_iacs_ready(chip);
		if (rc < 0) {
		pr_debug("IACS_RDY failed rc=%d\n", rc);
		@@ -403,24 +423,42 @@ static int __fg_interleaved_mem_read(struct fg_chip *chip, u16 address,
		/* check for error condition */
		rc = fg_clear_ima_errors_if_any(chip, false);
		if (rc < 0) {
		pr_err("Failed to check for ima errors rc=%d\n", rc);
		if (rc == -EAGAIN)
		pr_err("IMA error cleared, address [%d %d] len %d\n",
		address, offset, len);
		else
		pr_err("Failed to check for ima errors rc=%d\n",
		rc);
		return rc;
		}

		if (chip->use_ima_single_mode) {
		if (len) {
		address++;
		rc = fg_set_address(chip, address);
		if (rc < 0) {
		pr_err("failed to set address rc = %d\n",
		rc);
		return rc;
		}
		}
		} else {
		if (len && len < BYTES_PER_SRAM_WORD) {
		/*
		* Move to single mode. Changing address is not
		* required here as it must be in burst mode. Address
		* will get incremented internally by FG HW once the MSB
		* of RD_DATA is read.
		* required here as it must be in burst mode.
		* Address will get incremented internally by FG
		* HW once the MSB of RD_DATA is read.
		*/
		rc = fg_config_access_mode(chip, FG_READ, 0);
		rc = fg_config_access_mode(chip, FG_READ,
		false);
		if (rc < 0) {
		pr_err("failed to move to single mode rc=%d\n",
		rc);
		return -EIO;
		}
		}
		}

		rc = fg_check_iacs_ready(chip);
		if (rc < 0) {
		@@ -489,6 +527,7 @@ static int fg_interleaved_mem_config(struct fg_chip chip, u8 val,
		u16 address, int offset, int len, bool access)
		{
		int rc = 0;
		bool burst_mode = false;

		if (!is_mem_access_available(chip, access))
		return -EBUSY;
		@@ -503,7 +542,8 @@ static int fg_interleaved_mem_config(struct fg_chip chip, u8 val,
		}

		/* configure for the read/write, single/burst mode */
		rc = fg_config_access_mode(chip, access, (offset + len) > 4);
		burst_mode = chip->use_ima_single_mode ? false : ((offset + len) > 4);
		rc = fg_config_access_mode(chip, access, burst_mode);
		if (rc < 0) {
		pr_err("failed to set memory access rc = %d\n", rc);
		return rc;
		@@ -583,7 +623,7 @@ retry:
		if (rc < 0) {
		count++;
		if (rc == -EAGAIN) {
		pr_err("IMA access failed retry_count = %d\n", count);
		pr_err("IMA read failed retry_count = %d\n", count);
		goto retry;
		}
		pr_err("failed to read SRAM address rc = %d\n", rc);
		@@ -667,8 +707,8 @@ retry:
		rc = __fg_interleaved_mem_write(chip, address, offset, val, len);
		if (rc < 0) {
		count++;
		if ((rc == -EAGAIN) && (count < RETRY_COUNT)) {
		pr_err("IMA access failed retry_count = %d\n", count);
		if (rc == -EAGAIN) {
		pr_err("IMA write failed retry_count = %d\n", count);
		goto retry;
		}
		pr_err("failed to write SRAM address rc = %d\n", rc);

drivers/power/supply/qcom/qpnp-fg-gen3.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -3744,6 +3744,7 @@ static int fg_parse_dt(struct fg_chip *chip)
		case PM660_SUBTYPE:
		chip->sp = pmi8998_v2_sram_params;
		chip->alg_flags = pmi8998_v2_alg_flags;
		chip->use_ima_single_mode = true;
		break;
		default:
		return -EINVAL;

include/linux/qpnp/qpnp-revid.h

+22 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -181,6 +181,7 @@
		#define PM660L_SUBTYPE 0x1A
		#define PM660_SUBTYPE 0x1B

		/* PMI8998 REV_ID */
		#define PMI8998_V1P0_REV1 0x00
		#define PMI8998_V1P0_REV2 0x00
		#define PMI8998_V1P0_REV3 0x00
		@@ -196,6 +197,26 @@
		#define PMI8998_V2P0_REV3 0x00
		#define PMI8998_V2P0_REV4 0x02

		/* PM660 REV_ID */
		#define PM660_V1P0_REV1 0x00
		#define PM660_V1P0_REV2 0x00
		#define PM660_V1P0_REV3 0x00
		#define PM660_V1P0_REV4 0x01

		#define PM660_V1P1_REV1 0x00
		#define PM660_V1P1_REV2 0x00
		#define PM660_V1P1_REV3 0x01
		#define PM660_V1P1_REV4 0x01

		/* PMI8998 FAB_ID */
		#define PMI8998_FAB_ID_SMIC 0x11
		#define PMI8998_FAB_ID_GF 0x30

		/* PM660 FAB_ID */
		#define PM660_FAB_ID_GF 0x0
		#define PM660_FAB_ID_TSMC 0x2
		#define PM660_FAB_ID_MX 0x3

		/* PM8005 */
		#define PM8005_SUBTYPE 0x18