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Commit 3b1d4ed5 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Don't drag a platform specific header into generic arch code. 



For some platforms it's definitions may conflict.  So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 7c8545e9

arch/mips/kernel/smtc.c

+3 −3
Original line number Diff line number Diff line
@@ -13,9 +13,9 @@ 
#include <asm/system.h>

#include <asm/hardirq.h>

#include <asm/hazards.h>

#include <asm/irq.h>

#include <asm/mmu_context.h>

#include <asm/smp.h>

#include <asm/mips-boards/maltaint.h>

#include <asm/mipsregs.h>

#include <asm/cacheflush.h>

#include <asm/time.h>
@@ -614,7 +614,7 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new, 
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG

	unsigned int vpe = current_cpu_data.vpe_id;



	vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1;

	vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;

#endif

	irq_hwmask[irq] = hwmask;
@@ -822,7 +822,7 @@ void ipi_decode(struct smtc_ipi *pipi) 
	switch (type_copy) {

	case SMTC_CLOCK_TICK:

		irq_enter();

		kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++;

		kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_perfcount_irq]++;

		/* Invoke Clock "Interrupt" */

		ipi_timer_latch[dest_copy] = 0;

#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG

arch/mips/kernel/time.c

+9 −4
Original line number Diff line number Diff line
@@ -199,11 +199,16 @@ int (*perf_irq)(void) = null_perf_irq; 
EXPORT_SYMBOL(null_perf_irq);

EXPORT_SYMBOL(perf_irq);



/*

 * Timer interrupt

 */

int cp0_compare_irq;



/*

 * Performance counter IRQ or -1 if shared with timer

 */

int mipsxx_perfcount_irq;

EXPORT_SYMBOL(mipsxx_perfcount_irq);

int cp0_perfcount_irq;

EXPORT_SYMBOL_GPL(cp0_perfcount_irq);



/*

 * Possibly handle a performance counter interrupt.
@@ -213,12 +218,12 @@ static inline int handle_perf_irq (int r2) 
{

	/*

	 * The performance counter overflow interrupt may be shared with the

	 * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a

	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a

	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)

	 * and we can't reliably determine if a counter interrupt has also

	 * happened (!r2) then don't check for a timer interrupt.

	 */

	return (mipsxx_perfcount_irq < 0) &&

	return (cp0_perfcount_irq < 0) &&

		perf_irq() == IRQ_HANDLED &&

		!r2;

}

arch/mips/kernel/traps.c

+17 −3
Original line number Diff line number Diff line
@@ -1350,9 +1350,6 @@ void __init per_cpu_trap_init(void) 
	if (!secondaryTC) {

#endif /* CONFIG_MIPS_MT_SMTC */



	/*

	 * Interrupt handling.

	 */

	if (cpu_has_veic || cpu_has_vint) {

		write_c0_ebase (ebase);

		/* Setting vector spacing enables EI/VI mode  */
@@ -1366,6 +1363,23 @@ void __init per_cpu_trap_init(void) 
		} else

			set_c0_cause(CAUSEF_IV);

	}



	/*

	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:

	 *

	 *  o read IntCtl.IPTI to determine the timer interrupt

	 *  o read IntCtl.IPPCI to determine the performance counter interrupt

	 */

	if (cpu_has_mips_r2) {

		cp0_compare_irq = (read_c0_intctl () >> 29) & 7;

		cp0_perfcount_irq = -1;

	} else {

		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;

		cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;

		if (cp0_perfcount_irq != cp0_compare_irq)

			cp0_perfcount_irq = -1;

	}



#ifdef CONFIG_MIPS_MT_SMTC

	}

#endif /* CONFIG_MIPS_MT_SMTC */

arch/mips/mips-boards/atlas/atlas_int.c

+4 −4
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ asmlinkage void plat_irq_dispatch(void) 
	if (irq == MIPSCPU_INT_ATLAS)

		atlas_hw0_irqdispatch();

	else if (irq >= 0)

		do_IRQ(MIPSCPU_INT_BASE + irq);

		do_IRQ(MIPS_CPU_IRQ_BASE + irq);

	else

		spurious_interrupt();

}
@@ -261,11 +261,11 @@ void __init arch_init_irq(void) 
	} else if (cpu_has_vint) {

		set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);

#ifdef CONFIG_MIPS_MT_SMTC

		setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,

		setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,

				&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));

#else /* Not SMTC */

		setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);

		setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);

#endif /* CONFIG_MIPS_MT_SMTC */

	} else

		setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);

		setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);

}

arch/mips/mips-boards/generic/time.c

+16 −34
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 
unsigned long cpu_khz;



static int mips_cpu_timer_irq;

extern int mipsxx_perfcount_irq;

extern int cp0_perfcount_irq;

extern void smtc_timer_broadcast(int);



static void mips_timer_dispatch(void)
@@ -64,7 +64,7 @@ static void mips_timer_dispatch(void) 


static void mips_perf_dispatch(void)

{

	do_IRQ(mipsxx_perfcount_irq);

	do_IRQ(cp0_perfcount_irq);

}



/*
@@ -82,12 +82,12 @@ static inline int handle_perf_irq (int r2) 
{

	/*

	 * The performance counter overflow interrupt may be shared with the

	 * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a

	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a

	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)

	 * and we can't reliably determine if a counter interrupt has also

	 * happened (!r2) then don't check for a timer interrupt.

	 */

	return (mipsxx_perfcount_irq < 0) &&

	return (cp0_perfcount_irq < 0) &&

		perf_irq() == IRQ_HANDLED &&

		!r2;

}
@@ -259,42 +259,31 @@ static struct irqaction perf_irqaction = { 


void __init plat_perf_setup(struct irqaction *irq)

{

	int hwint = 0;

	mipsxx_perfcount_irq = -1;

	cp0_perfcount_irq = -1;



#ifdef MSC01E_INT_BASE

	if (cpu_has_veic) {

		set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);

		mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;

		cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;

	} else

#endif

	if (cpu_has_mips_r2) {

		/*

		 * Read IntCtl.IPPCI to determine the performance

		 * counter interrupt

		 */

		hwint = (read_c0_intctl () >> 26) & 7;

		if (hwint != MIPSCPU_INT_CPUCTR) {

	if (cp0_perfcount_irq >= 0) {

		if (cpu_has_vint)

				set_vi_handler (hwint, mips_perf_dispatch);

			mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint;

		}

	}

	if (mipsxx_perfcount_irq >= 0) {

			set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);

#ifdef CONFIG_MIPS_MT_SMTC

		setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint);

		setup_irq_smtc(cp0_perfcount_irq, irq,

		               0x100 << cp0_perfcount_irq);

#else

		setup_irq(mipsxx_perfcount_irq, irq);

		setup_irq(cp0_perfcount_irq, irq);

#endif /* CONFIG_MIPS_MT_SMTC */

#ifdef CONFIG_SMP

		set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq);

		set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);

#endif

	}

}



void __init plat_timer_setup(struct irqaction *irq)

{

	int hwint = 0;

#ifdef MSC01E_INT_BASE

	if (cpu_has_veic) {

		set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
@@ -303,22 +292,15 @@ void __init plat_timer_setup(struct irqaction *irq) 
	else

#endif

	{

		if (cpu_has_mips_r2)

			/*

			 * Read IntCtl.IPTI to determine the timer interrupt

			 */

			hwint = (read_c0_intctl () >> 29) & 7;

		else

			hwint = MIPSCPU_INT_CPUCTR;

		if (cpu_has_vint)

			set_vi_handler (hwint, mips_timer_dispatch);

		mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint;

			set_vi_handler(cp0_compare_irq, mips_timer_dispatch);

		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

	}



	/* we are using the cpu counter for timer interrupts */

	irq->handler = mips_timer_interrupt;	/* we use our own handler */

#ifdef CONFIG_MIPS_MT_SMTC

	setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint);

	setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);

#else

	setup_irq(mips_cpu_timer_irq, irq);

#endif /* CONFIG_MIPS_MT_SMTC */