Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a757d03 authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Gerrit - the friendly Code Review server
Browse files

clk: mdss: adjust PLL disable sequence to avoid glitch 



Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.

Change-Id: I6df35bbe18b0c42b43f38b9dd85c3502b2038928
Signed-off-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
parent b2e93442

drivers/clk/msm/mdss/mdss-dsi-pll-8998.c

+11 −3
Original line number Diff line number Diff line
@@ -634,7 +634,6 @@ error: 


static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc)

{

	dsi_pll_disable_global_clk(rsc);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0);

	dsi_pll_disable_pll_bias(rsc);

}
@@ -653,11 +652,20 @@ static void dsi_pll_disable(struct dsi_pll_vco_clk *vco) 


	pr_debug("stop PLL (%d)\n", rsc->index);



	/*

	 * To avoid any stray glitches while

	 * abruptly powering down the PLL

	 * make sure to gate the clock using

	 * the clock enable bit before powering

	 * down the PLL

	 **/

	dsi_pll_disable_global_clk(rsc);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0);

	dsi_pll_disable_sub(rsc);

	if (rsc->slave)

	if (rsc->slave) {

		dsi_pll_disable_global_clk(rsc->slave);

		dsi_pll_disable_sub(rsc->slave);



	}

	/* flush, ensure all register writes are done*/

	wmb();

	rsc->pll_on = false;