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Commit 39df01cd authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

Alex writes:
"This is the first -fixes pull for 3.7.  I would have preferred
to have gotten it out a bit sooner, but I was on holiday last week.
- Cleanup of the new 2 level page table code it get it in
  better shape and using less memory.
- Fix some display issues related to the PLL rework.
- Fix some cmpiler warnings and errors with certain config
  options.
- Other misc bug fixes."

* 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix spelling typos in debugging output
  drm/radeon: Don't destroy I2C Bus Rec in radeon_ext_tmds_enc_destroy().
  drm/radeon: check if pcie gen 2 is already enabled (v2)
  drm/radeon/cayman: set VM max pfn at MC init
  drm/radeon: separate pt alloc from lru add
  drm/radeon: don't add the IB pool to all VMs v2
  drm/radeon: allocate page tables on demand v4
  drm/radeon: update comments to clarify VM setup (v2)
  drm/radeon: allocate PPLLs from low to high
  drm/radeon: fix compilation with backlight disabled
  drm/radeon: use %zu for formatting size_t
parents 3459f620 8ad33cdf

drivers/gpu/drm/radeon/atombios_crtc.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -1690,10 +1690,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		}

		}

		/* all other cases */

		/* all other cases */

		pll_in_use = radeon_get_pll_use_mask(crtc);

		pll_in_use = radeon_get_pll_use_mask(crtc);

		if (!(pll_in_use & (1 << ATOM_PPLL2)))

			return ATOM_PPLL2;

		if (!(pll_in_use & (1 << ATOM_PPLL1)))

		if (!(pll_in_use & (1 << ATOM_PPLL1)))

			return ATOM_PPLL1;

			return ATOM_PPLL1;

		if (!(pll_in_use & (1 << ATOM_PPLL2)))

			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

		return ATOM_PPLL_INVALID;

	} else {

	} else {
@@ -1715,10 +1715,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			}

			}

			/* all other cases */

			/* all other cases */

			pll_in_use = radeon_get_pll_use_mask(crtc);

			pll_in_use = radeon_get_pll_use_mask(crtc);

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			DRM_ERROR("unable to allocate a PPLL\n");

			DRM_ERROR("unable to allocate a PPLL\n");

			return ATOM_PPLL_INVALID;

			return ATOM_PPLL_INVALID;

		} else {

		} else {

drivers/gpu/drm/radeon/evergreen.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 
	if (!(mask & DRM_PCIE_SPEED_50))

	if (!(mask & DRM_PCIE_SPEED_50))

		return;

		return;





	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if (speed_cntl & LC_CURRENT_DATA_RATE) {

		DRM_INFO("PCIE gen 2 link speeds already enabled\n");

		return;

	}



	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");





	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||

	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||

	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {

	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {

drivers/gpu/drm/radeon/ni.c

+5 −7
Original line number Original line Diff line number Diff line
@@ -770,9 +770,13 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32(0x15DC, 0);

	WREG32(0x15DC, 0);





	/* empty context1-7 */

	/* empty context1-7 */

	/* Assign the pt base to something valid for now; the pts used for

	 * the VMs are determined by the application and setup and assigned

	 * on the fly in the vm part of radeon_gart.c

	 */

	for (i = 1; i < 8; i++) {

	for (i = 1; i < 8; i++) {

		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);

		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);

		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);

		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);

		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

			rdev->gart.table_addr >> 12);

			rdev->gart.table_addr >> 12);

	}

	}
@@ -1572,12 +1576,6 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 
	if (vm == NULL)

	if (vm == NULL)

		return;

		return;





	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0));

	radeon_ring_write(ring, 0);



	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0));

	radeon_ring_write(ring, vm->last_pfn);



	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));

	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));

	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);

	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);

drivers/gpu/drm/radeon/r600.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -3703,6 +3703,12 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
	if (!(mask & DRM_PCIE_SPEED_50))

	if (!(mask & DRM_PCIE_SPEED_50))

		return;

		return;





	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if (speed_cntl & LC_CURRENT_DATA_RATE) {

		DRM_INFO("PCIE gen 2 link speeds already enabled\n");

		return;

	}



	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");





	/* 55 nm r6xx asics */

	/* 55 nm r6xx asics */

drivers/gpu/drm/radeon/radeon.h

+10 −4
Original line number Original line Diff line number Diff line
@@ -663,9 +663,14 @@ struct radeon_vm { 
	struct list_head		list;

	struct list_head		list;

	struct list_head		va;

	struct list_head		va;

	unsigned			id;

	unsigned			id;

	unsigned			last_pfn;



	u64				pd_gpu_addr;

	/* contains the page directory */

	struct radeon_sa_bo		*sa_bo;

	struct radeon_sa_bo		*page_directory;

	uint64_t			pd_gpu_addr;



	/* array of page tables, one for each page directory entry */

	struct radeon_sa_bo		**page_tables;



	struct mutex			mutex;

	struct mutex			mutex;

	/* last fence for cs using this vm */

	/* last fence for cs using this vm */

	struct radeon_fence		*fence;

	struct radeon_fence		*fence;
@@ -1843,9 +1848,10 @@ extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size 
 */

 */

int radeon_vm_manager_init(struct radeon_device *rdev);

int radeon_vm_manager_init(struct radeon_device *rdev);

void radeon_vm_manager_fini(struct radeon_device *rdev);

void radeon_vm_manager_fini(struct radeon_device *rdev);

int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);

void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);

void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);

void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);

int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);

int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);

void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);

struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,

struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,

				       struct radeon_vm *vm, int ring);

				       struct radeon_vm *vm, int ring);

void radeon_vm_fence(struct radeon_device *rdev,

void radeon_vm_fence(struct radeon_device *rdev,