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Commit 374db4f7 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm: Add save/restore functions for perfcounters"

parents bf0fbeea eeec2726
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+0 −2
Original line number Diff line number Diff line
@@ -406,11 +406,9 @@ static const unsigned int a3xx_registers[] = {
#ifdef CONFIG_DEBUG_FS
static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
{
	gpu->funcs->pm_resume(gpu);
	seq_printf(m, "status:   %08x\n",
			gpu_read(gpu, REG_A3XX_RBBM_STATUS));
	adreno_show(gpu, m);
	gpu->funcs->pm_suspend(gpu);
}
#endif

+0 −4
Original line number Diff line number Diff line
@@ -443,13 +443,9 @@ static const unsigned int a4xx_registers[] = {
#ifdef CONFIG_DEBUG_FS
static void a4xx_show(struct msm_gpu *gpu, struct seq_file *m)
{
	gpu->funcs->pm_resume(gpu);

	seq_printf(m, "status:   %08x\n",
			gpu_read(gpu, REG_A4XX_RBBM_STATUS));

	adreno_show(gpu, m);
	gpu->funcs->pm_suspend(gpu);

}
#endif
+271 −135

File changed.

Preview size limit exceeded, changes collapsed.

+18 −56
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@
#include "msm_iommu.h"
#include "msm_trace.h"
#include "a5xx_gpu.h"
#include <linux/clk/msm-clk.h>

#define SECURE_VA_START 0xc0000000
#define SECURE_VA_SIZE  SZ_256M
@@ -1170,25 +1169,14 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
{
	int ret;

	/*
	 * Between suspend/resumes the GPU clocks need to be turned off
	 * but not a complete power down, typically between frames. Set the
	 * memory retention flags on the GPU core clock to retain memory
	 * across clock toggles.
	 */
	if (gpu->core_clk) {
		clk_set_flags(gpu->core_clk, CLKFLAG_RETAIN_PERIPH);
		clk_set_flags(gpu->core_clk, CLKFLAG_RETAIN_MEM);
	}

	/* Turn on the core power */
	ret = msm_gpu_pm_resume(gpu);
	if (ret)
		return ret;

	/* If we are already up, don't mess with what works */
	if (gpu->active_cnt > 1)
		return 0;

	/* Restore all the counters before turning on the GPMU */
	a5xx_counters_restore(gpu);

	/* Turn the RBCCU domain first to limit the chances of voltage droop */
	gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000);
@@ -1220,22 +1208,16 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	/* Turn off the memory retention flag when not necessary */
	if (gpu->core_clk) {
		clk_set_flags(gpu->core_clk, CLKFLAG_NORETAIN_PERIPH);
		clk_set_flags(gpu->core_clk, CLKFLAG_NORETAIN_MEM);
	}

	/* Only do this next bit if we are about to go down */
	if (gpu->active_cnt == 1) {
	/* Clear the VBIF pipe before shutting down */

	gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF);
	spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF)
			== 0xF);

	gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0);

	/* Save the counters before going down */
	a5xx_counters_save(gpu);

	/*
	 * Reset the VBIF before power collapse to avoid issue with FIFO
	 * entries
@@ -1247,7 +1229,6 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
		gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD,
				0x00000000);
	}
	}

	return msm_gpu_pm_suspend(gpu);
}
@@ -1266,29 +1247,10 @@ static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
#ifdef CONFIG_DEBUG_FS
static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
	bool enabled = test_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);

	gpu->funcs->pm_resume(gpu);

	seq_printf(m, "status:   %08x\n",
			gpu_read(gpu, REG_A5XX_RBBM_STATUS));

	/*
	 * Temporarily disable hardware clock gating before going into
	 * adreno_show to avoid issues while reading the registers
	 */

	if (enabled)
		a5xx_set_hwcg(gpu, false);

	adreno_show(gpu, m);

	if (enabled)
		a5xx_set_hwcg(gpu, true);

	gpu->funcs->pm_suspend(gpu);
}
#endif

+2 −0
Original line number Diff line number Diff line
@@ -194,5 +194,7 @@ static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu)
}

int a5xx_counters_init(struct adreno_gpu *adreno_gpu);
void a5xx_counters_save(struct msm_gpu *gpu);
void a5xx_counters_restore(struct msm_gpu *gpu);

#endif /* __A5XX_GPU_H__ */
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