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Commit 34a1c994 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: change early camera on msm8996 agave"

parents 6aaef912 b5e11120

arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi

+23 −12
Original line number Diff line number Diff line
@@ -828,15 +828,14 @@ 
			<&clock_mmss clk_camss_vfe0_ahb_clk>,

			<&clock_mmss clk_camss_vfe1_ahb_clk>,

			<&clock_mmss clk_camss_vfe_axi_clk>,

			<&clock_mmss clk_camss_vfe0_stream_clk>,

			<&clock_mmss clk_camss_vfe1_stream_clk>,

			<&clock_mmss clk_smmu_vfe_axi_clk>,

			<&clock_mmss clk_smmu_vfe_ahb_clk>,

			<&clock_mmss clk_camss_csi_vfe0_clk>,

			<&clock_mmss clk_camss_csi_vfe1_clk>,

			<&clock_mmss clk_vfe0_clk_src>,

			<&clock_mmss clk_vfe1_clk_src>,

			<&clock_mmss clk_camss_vfe0_stream_clk>,

			<&clock_mmss clk_camss_vfe1_stream_clk>,

			<&clock_mmss clk_camss_csi_vfe0_clk>,

			<&clock_mmss clk_camss_csi_vfe1_clk>,

			<&clock_mmss clk_camss_csi2_ahb_clk>,

			<&clock_mmss clk_camss_csi2_clk>,

			<&clock_mmss clk_camss_csi2phy_clk>,
@@ -858,15 +857,14 @@ 
			"camss_vfe0_ahb_clk",

			"camss_vfe1_ahb_clk",

			"camss_vfe_axi_clk",

			"camss_vfe0_stream_clk",

			"camss_vfe1_stream_clk",

			"smmu_vfe_axi_clk",

			"smmu_vfe_ahb_clk",

			"camss_csi_vfe0_clk",

			"camss_csi_vfe1_clk",

			"vfe0_clk_src",

			"vfe1_clk_src",

			"camss_vfe0_stream_clk",

			"camss_vfe1_stream_clk",

			"camss_csi_vfe0_clk",

			"camss_csi_vfe1_clk",

			"camss_csi2_ahb_clk",

			"camss_csi2_clk",

			"camss_csi2phy_clk",
@@ -876,7 +874,6 @@ 
			"camss_ispif_ahb_clk",

			"clk_camss_vfe0_clk",

			"clk_camss_vfe1_clk";



		qcom,clock-rates = <19200000

					19200000

					19200000
@@ -890,13 +887,12 @@ 
					320000000

					0

					0

					320000000

					320000000

					0

					0

					0

					0

					320000000

					320000000

					0

					0

					200000000

					200000000
@@ -906,6 +902,21 @@ 
					0

					100000000

					100000000>;

		qcom,clock-cntl-support;

		qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE",

			"INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE","NO_SET_RATE",

			"INIT_RATE","NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE","NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE";

	};



	qcom,ntn_avb {

arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi

+23 −12
Original line number Diff line number Diff line
@@ -593,15 +593,14 @@ 
			<&clock_mmss clk_camss_vfe0_ahb_clk>,

			<&clock_mmss clk_camss_vfe1_ahb_clk>,

			<&clock_mmss clk_camss_vfe_axi_clk>,

			<&clock_mmss clk_camss_vfe0_stream_clk>,

			<&clock_mmss clk_camss_vfe1_stream_clk>,

			<&clock_mmss clk_smmu_vfe_axi_clk>,

			<&clock_mmss clk_smmu_vfe_ahb_clk>,

			<&clock_mmss clk_camss_csi_vfe0_clk>,

			<&clock_mmss clk_camss_csi_vfe1_clk>,

			<&clock_mmss clk_vfe0_clk_src>,

			<&clock_mmss clk_vfe1_clk_src>,

			<&clock_mmss clk_camss_vfe0_stream_clk>,

			<&clock_mmss clk_camss_vfe1_stream_clk>,

			<&clock_mmss clk_camss_csi_vfe0_clk>,

			<&clock_mmss clk_camss_csi_vfe1_clk>,

			<&clock_mmss clk_camss_csi2_ahb_clk>,

			<&clock_mmss clk_camss_csi2_clk>,

			<&clock_mmss clk_camss_csi2phy_clk>,
@@ -623,15 +622,14 @@ 
			"camss_vfe0_ahb_clk",

			"camss_vfe1_ahb_clk",

			"camss_vfe_axi_clk",

			"camss_vfe0_stream_clk",

			"camss_vfe1_stream_clk",

			"smmu_vfe_axi_clk",

			"smmu_vfe_ahb_clk",

			"camss_csi_vfe0_clk",

			"camss_csi_vfe1_clk",

			"vfe0_clk_src",

			"vfe1_clk_src",

			"camss_vfe0_stream_clk",

			"camss_vfe1_stream_clk",

			"camss_csi_vfe0_clk",

			"camss_csi_vfe1_clk",

			"camss_csi2_ahb_clk",

			"camss_csi2_clk",

			"camss_csi2phy_clk",
@@ -641,7 +639,6 @@ 
			"camss_ispif_ahb_clk",

			"clk_camss_vfe0_clk",

			"clk_camss_vfe1_clk";



		qcom,clock-rates = <19200000

					19200000

					19200000
@@ -655,13 +652,12 @@ 
					320000000

					0

					0

					320000000

					320000000

					0

					0

					0

					0

					320000000

					320000000

					0

					0

					200000000

					200000000
@@ -671,6 +667,21 @@ 
					0

					100000000

					100000000>;

		qcom,clock-cntl-support;

		qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "INIT_RATE",

			"INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE",

			"NO_SET_RATE","NO_SET_RATE",

			"INIT_RATE","NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE",

			"NO_SET_RATE","NO_SET_RATE",

			"NO_SET_RATE", "NO_SET_RATE";

	};



	ntn1: ntn_avb@1 { /* Neutrno device on RC1*/