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Commit 347e7592 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: Add support for RLC init on SI



RLC handles the interrupt controller and other tasks
on the GPU.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 2ece2e8b
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+13 −0
Original line number Diff line number Diff line
@@ -772,6 +772,18 @@ struct r600_blit {

void r600_blit_suspend(struct radeon_device *rdev);

/*
 * SI RLC stuff
 */
struct si_rlc {
	/* for power gating */
	struct radeon_bo	*save_restore_obj;
	uint64_t		save_restore_gpu_addr;
	/* for clear state */
	struct radeon_bo	*clear_state_obj;
	uint64_t		clear_state_gpu_addr;
};

int radeon_ib_get(struct radeon_device *rdev, int ring,
		  struct radeon_ib **ib, unsigned size);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
@@ -1532,6 +1544,7 @@ struct radeon_device {
	struct r600_vram_scratch vram_scratch;
	int msi_enabled; /* msi enabled */
	struct r600_ih ih; /* r6/700 interrupt ring */
	struct si_rlc rlc;
	struct work_struct hotplug_work;
	int num_crtc; /* number of crtcs */
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
+132 −0
Original line number Diff line number Diff line
@@ -2940,3 +2940,135 @@ void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
	WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
}

/*
 * RLC
 */
static void si_rlc_fini(struct radeon_device *rdev)
{
	int r;

	/* save restore block */
	if (rdev->rlc.save_restore_obj) {
		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
		if (unlikely(r != 0))
			dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
		radeon_bo_unpin(rdev->rlc.save_restore_obj);
		radeon_bo_unreserve(rdev->rlc.save_restore_obj);

		radeon_bo_unref(&rdev->rlc.save_restore_obj);
		rdev->rlc.save_restore_obj = NULL;
	}

	/* clear state block */
	if (rdev->rlc.clear_state_obj) {
		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
		if (unlikely(r != 0))
			dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
		radeon_bo_unpin(rdev->rlc.clear_state_obj);
		radeon_bo_unreserve(rdev->rlc.clear_state_obj);

		radeon_bo_unref(&rdev->rlc.clear_state_obj);
		rdev->rlc.clear_state_obj = NULL;
	}
}

static int si_rlc_init(struct radeon_device *rdev)
{
	int r;

	/* save restore block */
	if (rdev->rlc.save_restore_obj == NULL) {
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
				RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.save_restore_obj);
		if (r) {
			dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
			return r;
		}
	}

	r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
	if (unlikely(r != 0)) {
		si_rlc_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->rlc.save_restore_gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->rlc.save_restore_obj);
		dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
		si_rlc_fini(rdev);
		return r;
	}

	/* clear state block */
	if (rdev->rlc.clear_state_obj == NULL) {
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
				RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_obj);
		if (r) {
			dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
			si_rlc_fini(rdev);
			return r;
		}
	}
	r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
	if (unlikely(r != 0)) {
		si_rlc_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->rlc.clear_state_gpu_addr);
	if (r) {

		radeon_bo_unreserve(rdev->rlc.clear_state_obj);
		dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
		si_rlc_fini(rdev);
		return r;
	}

	return 0;
}

static void si_rlc_stop(struct radeon_device *rdev)
{
	WREG32(RLC_CNTL, 0);
}

static void si_rlc_start(struct radeon_device *rdev)
{
	WREG32(RLC_CNTL, RLC_ENABLE);
}

static int si_rlc_resume(struct radeon_device *rdev)
{
	u32 i;
	const __be32 *fw_data;

	if (!rdev->rlc_fw)
		return -EINVAL;

	si_rlc_stop(rdev);

	WREG32(RLC_RL_BASE, 0);
	WREG32(RLC_RL_SIZE, 0);
	WREG32(RLC_LB_CNTL, 0);
	WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
	WREG32(RLC_LB_CNTR_INIT, 0);

	WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
	WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);

	WREG32(RLC_MC_CNTL, 0);
	WREG32(RLC_UCODE_CNTL, 0);

	fw_data = (const __be32 *)rdev->rlc_fw->data;
	for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
		WREG32(RLC_UCODE_ADDR, i);
		WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
	}
	WREG32(RLC_UCODE_ADDR, 0);

	si_rlc_start(rdev);

	return 0;
}
+17 −0
Original line number Diff line number Diff line
@@ -513,6 +513,23 @@

#define	CP_DEBUG					0xC1FC

#define RLC_CNTL                                          0xC300
#       define RLC_ENABLE                                 (1 << 0)
#define RLC_RL_BASE                                       0xC304
#define RLC_RL_SIZE                                       0xC308
#define RLC_LB_CNTL                                       0xC30C
#define RLC_SAVE_AND_RESTORE_BASE                         0xC310
#define RLC_LB_CNTR_MAX                                   0xC314
#define RLC_LB_CNTR_INIT                                  0xC318

#define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320

#define RLC_UCODE_ADDR                                    0xC32C
#define RLC_UCODE_DATA                                    0xC330

#define RLC_MC_CNTL                                       0xC344
#define RLC_UCODE_CNTL                                    0xC348

#define VGT_EVENT_INITIATOR                             0x28a90
#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)