Merge "ARM: dts: msm: Add msm-core device for msmfalcon" (33fe35c7) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+47 −0

Original line number	Diff line number	Diff line
		@@ -48,6 +48,7 @@
		reg = <0x0 0x0>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea0>;
		};

		CPU1: cpu@1 {
		@@ -56,6 +57,7 @@
		reg = <0x0 0x1>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea1>;
		};

		CPU2: cpu@2 {
		@@ -64,6 +66,7 @@
		reg = <0x0 0x2>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea2>;
		};

		CPU3: cpu@3 {
		@@ -72,6 +75,7 @@
		reg = <0x0 0x3>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea3>;
		};

		CPU4: cpu@100 {
		@@ -80,6 +84,7 @@
		reg = <0x0 0x100>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile1>;
		qcom,ea = <&ea4>;
		};

		CPU5: cpu@101 {
		@@ -88,6 +93,7 @@
		reg = <0x0 0x101>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile2>;
		qcom,ea = <&ea5>;
		};

		CPU6: cpu@102 {
		@@ -96,6 +102,7 @@
		reg = <0x0 0x102>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile3>;
		qcom,ea = <&ea6>;
		};

		CPU7: cpu@103 {
		@@ -104,6 +111,7 @@
		reg = <0x0 0x103>;
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile4>;
		qcom,ea = <&ea7>;
		};

		cpu-map {
		@@ -540,6 +548,45 @@
		};
		};

		qcom,msm-core@780000 {
		compatible = "qcom,apss-core-ea";
		reg = <0x780000 0x1000>;
		qcom,low-hyst-temp = <10>;
		qcom,high-hyst-temp = <5>;

		ea0: ea0 {
		sensor = <&sensor_information1>;
		};

		ea1: ea1 {
		sensor = <&sensor_information1>;
		};

		ea2: ea2 {
		sensor = <&sensor_information1>;
		};

		ea3: ea3 {
		sensor = <&sensor_information1>;
		};

		ea4: ea4 {
		sensor = <&sensor_information3>;
		};

		ea5: ea5 {
		sensor = <&sensor_information4>;
		};

		ea6: ea6 {
		sensor = <&sensor_information5>;
		};

		ea7: ea7 {
		sensor = <&sensor_information6>;
		};
		};

		uartblsp2dm1: serial@0c1b0000 {
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0xc1b0000 0x1000>;