Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 31bcecd1 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Kyle Yan
Browse files

clk: msm: clock: Add support for programming the GCC_GPU_IREF_EN register 



Add a new gcc_gpu_iref_clk that the graphics driver can control
as needed. The default state of the clock is ON; so having this
control will mean saving current.

CRs-Fixed: 1024948
Change-Id: I562bb546f49b1605f20fb7d705f40584d190230b
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 1cdd0691

drivers/clk/msm/clock-gcc-cobalt.c

+12 −0
Original line number Diff line number Diff line
@@ -1683,6 +1683,17 @@ static struct branch_clk gcc_gpu_snoc_dvm_gfx_clk = { 
	},

};



static struct branch_clk gcc_gpu_iref_clk = {

	.cbcr_reg = GCC_GPU_IREF_EN,

	.has_sibling = 1,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_gpu_iref_clk",

		.ops = &clk_ops_branch,

		CLK_INIT(gcc_gpu_iref_clk.c),

	},

};



static struct local_vote_clk gcc_bimc_hmss_axi_clk = {

	.cbcr_reg = GCC_BIMC_HMSS_AXI_CBCR,

	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE,
@@ -2645,6 +2656,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { 
	CLK_LIST(gcc_gpu_bimc_gfx_src_clk),

	CLK_LIST(gcc_gpu_cfg_ahb_clk),

	CLK_LIST(gcc_gpu_snoc_dvm_gfx_clk),

	CLK_LIST(gcc_gpu_iref_clk),

	CLK_LIST(gcc_bimc_hmss_axi_clk),

	CLK_LIST(gcc_hmss_ahb_clk),

	CLK_LIST(gcc_hmss_dvm_bus_clk),

include/dt-bindings/clock/msm-clocks-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -199,6 +199,7 @@ 
#define clk_gcc_gpu_bimc_gfx_src_clk		0x377cb748

#define clk_gcc_bimc_hmss_axi_clk		0x84653931

#define clk_gcc_gpu_cfg_ahb_clk			0x72f20a57

#define clk_gcc_gpu_iref_clk			0xfd82abad

#define clk_gcc_hmss_ahb_clk			0x62818713

#define clk_gcc_hmss_dvm_bus_clk		0x17cc8b53

#define clk_gcc_hmss_rbcpr_clk			0x699183be

include/dt-bindings/clock/msm-clocks-hwio-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ 
#define GCC_GPU_BIMC_GFX_SRC_CBCR				0x7100C

#define GCC_GPU_CFG_AHB_CBCR					0x71004

#define GCC_GPU_SNOC_DVM_GFX_CBCR				0x71018

#define GCC_GPU_IREF_EN						0x88010

#define GCC_BIMC_HMSS_AXI_CBCR					0x48004

#define GCC_HMSS_AHB_CBCR					0x48000

#define GCC_HMSS_DVM_BUS_CBCR					0x4808C