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Commit 3091a5c5 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Kyle Yan
Browse files

clk: msm: clock: Add support for programming MDP_LUT_CBCR register 



Add support for the mdss_mdp_lut_clk clock on MSMCOBALT.
In addition, remove toggling the memory retention bits for the
mdp core clock during gdsc_enable/disable. The display driver
will use the set_flags API to set the core clock memory retention.

CRs-Fixed: 1025605
Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent d7a02e72

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+1 −2
Original line number Diff line number Diff line
@@ -2813,9 +2813,8 @@ 
};



&gdsc_mdss {

	clock-names = "bus_clk", "core_clk", "root_clk";

	clock-names = "bus_clk", "rot_clk";

	clocks = <&clock_mmss clk_mmss_mdss_axi_clk>,

		 <&clock_mmss clk_mmss_mdss_mdp_clk>,

		 <&clock_mmss clk_mmss_mdss_rot_clk>;

	status = "ok";

};

drivers/clk/msm/clock-mmss-cobalt.c

+16 −0
Original line number Diff line number Diff line
@@ -2019,6 +2019,20 @@ static struct branch_clk mmss_mdss_mdp_clk = { 
	},

};



static struct branch_clk mmss_mdss_mdp_lut_clk = {

	.cbcr_reg = MMSS_MDSS_MDP_LUT_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.halt_check = DELAY,

	.base = &virt_base,

	.c = {

		.dbg_name = "mmss_mdss_mdp_lut_clk",

		.parent = &mdp_clk_src.c,

		.ops = &clk_ops_branch,

		CLK_INIT(mmss_mdss_mdp_lut_clk.c),

	},

};



static struct branch_clk mmss_mdss_pclk0_clk = {

	.cbcr_reg = MMSS_MDSS_PCLK0_CBCR,

	.has_sibling = 0,
@@ -2230,6 +2244,7 @@ static struct mux_clk mmss_debug_mux = { 
		{ &mmss_mdss_rot_clk.c, 0x0012 },

		{ &mmss_snoc_dvm_axi_clk.c, 0x0013 },

		{ &mmss_mdss_mdp_clk.c, 0x0014 },

		{ &mmss_mdss_mdp_lut_clk.c, 0x0015 },

		{ &mmss_mdss_pclk0_clk.c, 0x0016 },

		{ &mmss_mdss_pclk1_clk.c, 0x0017 },

		{ &mmss_mdss_extpclk_clk.c, 0x0018 },
@@ -2455,6 +2470,7 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = { 
	CLK_LIST(mmss_mdss_hdmi_clk),

	CLK_LIST(mmss_mdss_hdmi_dp_ahb_clk),

	CLK_LIST(mmss_mdss_mdp_clk),

	CLK_LIST(mmss_mdss_mdp_lut_clk),

	CLK_LIST(mmss_mdss_pclk0_clk),

	CLK_LIST(mmss_mdss_pclk1_clk),

	CLK_LIST(mmss_mdss_rot_clk),

include/dt-bindings/clock/msm-clocks-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -412,6 +412,7 @@ 
#define clk_mmss_mdss_hdmi_clk			0x28460a6d

#define clk_mmss_mdss_hdmi_dp_ahb_clk		0x5448519f

#define clk_mmss_mdss_mdp_clk			0x43539b0e

#define clk_mmss_mdss_mdp_lut_clk		0x00627b2b

#define clk_mmss_mdss_pclk0_clk			0xcc0e909d

#define clk_mmss_mdss_pclk1_clk			0x850d9146

#define clk_mmss_mdss_rot_clk			0xbb7e71c4

include/dt-bindings/clock/msm-clocks-hwio-cobalt.h

+1 −0
Original line number Diff line number Diff line
@@ -380,6 +380,7 @@ 
#define MMSS_MDSS_HDMI_CBCR					0x02338

#define MMSS_MDSS_HDMI_DP_AHB_CBCR				0x0230C

#define MMSS_MDSS_MDP_CBCR					0x0231C

#define MMSS_MDSS_MDP_LUT_CBCR					0x02320

#define MMSS_MDSS_PCLK0_CBCR					0x02314

#define MMSS_MDSS_PCLK1_CBCR					0x02318

#define MMSS_MDSS_ROT_CBCR					0x02350