Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 28c9770b authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Arnd Bergmann
Browse files

ARM: dts: fix L2 address in Hi3620 



Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: default avatarWei Xu <xuwei5@hisilicon.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent bf1d9879

arch/arm/boot/dts/hi3620.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 


		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0xfc10000 0x100000>;

			reg = <0x100000 0x100000>;

			interrupts = <0 15 4>;

			cache-unified;

			cache-level = <2>;