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Commit 28994bb5 authored Jan 02, 2018 by Marc Zyngier Committed by Srinivas Ramana Feb 08, 2018

arm64: Move post_ttbr_update_workaround to C code



We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Change-Id: Ie58057014bc0c8610ce2f00f09c9f52d28ac49a7
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: 95e3de3590e3f2358bb13f013911bc1bfa5d3f53
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[sramana@codeaurora.org: Resolve trivial merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>

parent a6486b73

arch/arm64/include/asm/assembler.h

+0 −13

Original line number	Diff line number	Diff line
		@@ -399,17 +399,4 @@ alternative_endif
		mrs \rd, sp_el0
		.endm

		/*
		* Errata workaround post TTBR0_EL1 update.
		*/
		.macro post_ttbr0_update_workaround
		#ifdef CONFIG_CAVIUM_ERRATUM_27456
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu
		dsb nsh
		isb
		alternative_else_nop_endif
		#endif
		.endm

		#endif /* __ASM_ASSEMBLER_H */

arch/arm64/kernel/entry.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -200,7 +200,7 @@ alternative_else_nop_endif
		* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
		* corruption).
		*/
		post_ttbr0_update_workaround
		bl post_ttbr_update_workaround
		.endif
		1:
		.if \el != 0

arch/arm64/mm/context.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -190,6 +190,15 @@ switch_mm_fastpath:
		cpu_switch_mm(mm->pgd, mm);
		}

		/* Errata workaround post TTBRx_EL1 update. */
		asmlinkage void post_ttbr_update_workaround(void)
		{
		asm(ALTERNATIVE("nop; nop; nop",
		"ic iallu; dsb nsh; isb",
		ARM64_WORKAROUND_CAVIUM_27456,
		CONFIG_CAVIUM_ERRATUM_27456));
		}

		static int asids_init(void)
		{
		int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 4);

arch/arm64/mm/proc.S

+1 −2

Original line number	Diff line number	Diff line
		@@ -171,8 +171,7 @@ ENTRY(cpu_do_switch_mm)
		bfi x0, x1, #48, #16 // set the ASID
		msr ttbr0_el1, x0 // set TTBR0
		isb
		post_ttbr0_update_workaround
		ret
		b post_ttbr_update_workaround // Back to C code...
		ENDPROC(cpu_do_switch_mm)

		.pushsection ".idmap.text", "ax"