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Commit 28113a99 authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Removal of trivial pci_controller_info uses. 



Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6c108f12

arch/sparc64/kernel/pci.c

+0 −2
Original line number Diff line number Diff line
@@ -921,10 +921,8 @@ static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struc 
				      enum pci_mmap_state mmap_state)

{

	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;

	struct pci_controller_info *p;

	unsigned long space_size, user_offset, user_size;



	p = pbm->parent;

	if (mmap_state == pci_mmap_io) {

		space_size = (pbm->io_space.end -

			      pbm->io_space.start) + 1;

arch/sparc64/kernel/pci_psycho.c

+30 −36
Original line number Diff line number Diff line
@@ -98,13 +98,8 @@ static int psycho_out_of_range(struct pci_pbm_info *pbm, 
			       unsigned char bus,

			       unsigned char devfn)

{

	return ((pbm->parent == 0) ||

		((pbm == &pbm->parent->pbm_B) &&

		 (bus == pbm->pci_first_busno) &&

		 PCI_SLOT(devfn) > 8) ||

		((pbm == &pbm->parent->pbm_A) &&

		 (bus == pbm->pci_first_busno) &&

		 PCI_SLOT(devfn) > 8));

	return ((bus == pbm->pci_first_busno) &&

		PCI_SLOT(devfn) > 8);

}



/* PSYCHO PCI configuration space accessors. */
@@ -918,33 +913,33 @@ static void psycho_scan_bus(struct pci_pbm_info *pbm) 
	psycho_register_error_handlers(pbm);

}



static void psycho_iommu_init(struct pci_controller_info *p)

static void psycho_iommu_init(struct pci_pbm_info *pbm)

{

	struct iommu *iommu = p->pbm_A.iommu;

	struct iommu *iommu = pbm->iommu;

	unsigned long i;

	u64 control;



	/* Register addresses. */

	iommu->iommu_control  = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;

	iommu->iommu_tsbbase  = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;

	iommu->iommu_flush    = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;

	iommu->iommu_control  = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;

	iommu->iommu_tsbbase  = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;

	iommu->iommu_flush    = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;

	/* PSYCHO's IOMMU lacks ctx flushing. */

	iommu->iommu_ctxflush = 0;



	/* We use the main control register of PSYCHO as the write

	 * completion register.

	 */

	iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;

	iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;



	/*

	 * Invalidate TLB Entries.

	 */

	control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);

	control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);

	control |= PSYCHO_IOMMU_CTRL_DENAB;

	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);

	psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);

	for(i = 0; i < 16; i++) {

		psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);

		psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);

		psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);

		psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);

	}



	/* Leave diag mode enabled for full-flushing done
@@ -952,17 +947,17 @@ static void psycho_iommu_init(struct pci_controller_info *p) 
	 */

	pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);



	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,

	psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,

		     __pa(iommu->page_table));



	control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);

	control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);

	control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);

	control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);

	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);

	psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);



	/* If necessary, hook us up for starfire IRQ translations. */

	if (this_is_starfire)

		starfire_hookup(p->pbm_A.portid);

		starfire_hookup(pbm->portid);

}



#define PSYCHO_IRQ_RETRY	0x1a00UL
@@ -977,36 +972,35 @@ static void psycho_iommu_init(struct pci_controller_info *p) 
#define  PSYCHO_PCIDIAG_IPAPAR	 0x0000000000000002UL /* Invert PIO address parity    */

#define  PSYCHO_PCIDIAG_LPBACK	 0x0000000000000001UL /* Enable loopback mode         */



static void psycho_controller_hwinit(struct pci_controller_info *p)

static void psycho_controller_hwinit(struct pci_pbm_info *pbm)

{

	u64 tmp;



	psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);

	psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);



	/* Enable arbiter for all PCI slots. */

	tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);

	tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);

	tmp |= PSYCHO_PCICTRL_AEN;

	psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);

	psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);



	tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);

	tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);

	tmp |= PSYCHO_PCICTRL_AEN;

	psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);

	psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);



	/* Disable DMA write / PIO read synchronization on

	 * both PCI bus segments.

	 * [ U2P Erratum 1243770, STP2223BGA data sheet ]

	 */

	tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);

	tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);

	tmp |= PSYCHO_PCIDIAG_DDWSYNC;

	psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);

	psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);



	tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);

	tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);

	tmp |= PSYCHO_PCIDIAG_DDWSYNC;

	psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);

	psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);

}



static void psycho_pbm_strbuf_init(struct pci_controller_info *p,

				   struct pci_pbm_info *pbm,

static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,

				   int is_pbm_a)

{

	unsigned long base = pbm->controller_regs;
@@ -1105,7 +1099,7 @@ static void psycho_pbm_init(struct pci_controller_info *p, 


	pci_get_pbm_props(pbm);



	psycho_pbm_strbuf_init(p, pbm, is_pbm_a);

	psycho_pbm_strbuf_init(pbm, is_pbm_a);

}



#define PSYCHO_CONFIGSPACE	0x001000000UL
@@ -1165,9 +1159,9 @@ void psycho_init(struct device_node *dp, char *model_name) 
	 */

	pci_memspace_mask = 0x7fffffffUL;



	psycho_controller_hwinit(p);

	psycho_controller_hwinit(&p->pbm_A);



	psycho_iommu_init(p);

	psycho_iommu_init(&p->pbm_A);



	is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);

	psycho_pbm_init(p, dp, is_pbm_a);

arch/sparc64/kernel/pci_sabre.c

+28 −29
Original line number Diff line number Diff line
@@ -942,30 +942,30 @@ static void sabre_scan_bus(struct pci_pbm_info *pbm) 
	sabre_register_error_handlers(pbm);

}



static void sabre_iommu_init(struct pci_controller_info *p,

static void sabre_iommu_init(struct pci_pbm_info *pbm,

			     int tsbsize, unsigned long dvma_offset,

			     u32 dma_mask)

{

	struct iommu *iommu = p->pbm_A.iommu;

	struct iommu *iommu = pbm->iommu;

	unsigned long i;

	u64 control;



	/* Register addresses. */

	iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;

	iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;

	iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;

	iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;

	iommu->iommu_control  = pbm->controller_regs + SABRE_IOMMU_CONTROL;

	iommu->iommu_tsbbase  = pbm->controller_regs + SABRE_IOMMU_TSBBASE;

	iommu->iommu_flush    = pbm->controller_regs + SABRE_IOMMU_FLUSH;

	iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;

	/* Sabre's IOMMU lacks ctx flushing. */

	iommu->iommu_ctxflush = 0;

                                        

	/* Invalidate TLB Entries. */

	control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);

	control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);

	control |= SABRE_IOMMUCTRL_DENAB;

	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);

	sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);



	for(i = 0; i < 16; i++) {

		sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);

		sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);

		sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);

		sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);

	}



	/* Leave diag mode enabled for full-flushing done
@@ -973,10 +973,10 @@ static void sabre_iommu_init(struct pci_controller_info *p, 
	 */

	pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);



	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,

	sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,

		    __pa(iommu->page_table));



	control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);

	control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);

	control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);

	control |= SABRE_IOMMUCTRL_ENAB;

	switch(tsbsize) {
@@ -991,14 +991,11 @@ static void sabre_iommu_init(struct pci_controller_info *p, 
		prom_halt();

		break;

	}

	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);

	sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);

}



static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)

static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp)

{

	struct pci_pbm_info *pbm;



	pbm = &p->pbm_A;

	pbm->name = dp->full_name;

	printk("%s: SABRE PCI Bus Module\n", pbm->name);
@@ -1019,6 +1016,7 @@ void sabre_init(struct device_node *dp, char *model_name) 
{

	const struct linux_prom64_registers *pr_regs;

	struct pci_controller_info *p;

	struct pci_pbm_info *pbm;

	struct iommu *iommu;

	int tsbsize;

	const u32 *vdma;
@@ -1055,14 +1053,15 @@ void sabre_init(struct device_node *dp, char *model_name) 
		prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");

		prom_halt();

	}

	p->pbm_A.iommu = iommu;

	pbm = &p->pbm_A;

	pbm->iommu = iommu;



	upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);



	p->pbm_A.next = pci_pbm_root;

	pci_pbm_root = &p->pbm_A;

	pbm->next = pci_pbm_root;

	pci_pbm_root = pbm;



	p->pbm_A.portid = upa_portid;

	pbm->portid = upa_portid;



	/*

	 * Map in SABRE register set and report the presence of this SABRE.
@@ -1073,26 +1072,26 @@ void sabre_init(struct device_node *dp, char *model_name) 
	/*

	 * First REG in property is base of entire SABRE register space.

	 */

	p->pbm_A.controller_regs = pr_regs[0].phys_addr;

	pbm->controller_regs = pr_regs[0].phys_addr;



	/* Clear interrupts */



	/* PCI first */

	for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)

		sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);

		sabre_write(pbm->controller_regs + clear_irq, 0x0UL);



	/* Then OBIO */

	for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)

		sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);

		sabre_write(pbm->controller_regs + clear_irq, 0x0UL);



	/* Error interrupts are enabled later after the bus scan. */

	sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,

	sabre_write(pbm->controller_regs + SABRE_PCICTRL,

		    (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |

		     SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));



	/* Now map in PCI config space for entire SABRE. */

	p->pbm_A.config_space =

		(p->pbm_A.controller_regs + SABRE_CONFIGSPACE);

	pbm->config_space =

		(pbm->controller_regs + SABRE_CONFIGSPACE);



	vdma = of_get_property(dp, "virtual-dma", NULL);
@@ -1116,10 +1115,10 @@ void sabre_init(struct device_node *dp, char *model_name) 
			prom_halt();

	}



	sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);

	sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask);



	/*

	 * Look for APB underneath.

	 */

	sabre_pbm_init(p, dp);

	sabre_pbm_init(p, pbm, dp);

}