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Commit 26cdd44d authored by Viswanadha Raju Thotakura's avatar Viswanadha Raju Thotakura
Browse files

msm: camera: Add support for camera on version 2 of msmcobalt 



EQ bias is enabled in of msmcobalt version 2 csiphy.
Differentiate this setting with new version 2 camera dt file.

CRs-Fixed: 1050172
Change-Id: I5781453f2b2a81b9cf5f7fb643e021b53879583e
Signed-off-by: default avatarViswanadha Raju Thotakura <viswanad@codeaurora.org>
parent 9c8924db

Documentation/devicetree/bindings/media/video/msm-csi-phy.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required properties: 
    - "qcom,csiphy-v3.4.2"

    - "qcom,csiphy-v3.5"

    - "qcom,csiphy-v5.0"

    - "qcom,csiphy-v5.01"

- reg : offset and length of the register set for the device

    for the csiphy operating in compatible mode.

- reg-names : should specify relevant names to each reg property defined.

arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi

0 → 100644
+111 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	qcom,csiphy@ca34000 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";

		reg = <0xca34000 0x1000>;

		reg-names = "csiphy";

		interrupts = <0 78 0>;

		interrupt-names = "csiphy";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,

			<&clock_mmss clk_mmss_camss_ahb_clk>,

			<&clock_mmss clk_mmss_camss_top_ahb_clk>,

			<&clock_mmss clk_csi0_clk_src>,

			<&clock_mmss clk_mmss_camss_csi0_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid0_clk>,

			<&clock_mmss clk_csi0phytimer_clk_src>,

			<&clock_mmss clk_mmss_camss_csi0phytimer_clk>,

			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csiphy_clk_src>,

			<&clock_mmss clk_mmss_camss_csiphy0_clk>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

		status = "ok";

	};



	qcom,csiphy@ca35000 {

		cell-index = <1>;

		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";

		reg = <0xca35000 0x1000>;

		reg-names = "csiphy";

		interrupts = <0 79 0>;

		interrupt-names = "csiphy";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,

			<&clock_mmss clk_mmss_camss_ahb_clk>,

			<&clock_mmss clk_mmss_camss_top_ahb_clk>,

			<&clock_mmss clk_csi1_clk_src>,

			<&clock_mmss clk_mmss_camss_csi1_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,

			<&clock_mmss clk_csi1phytimer_clk_src>,

			<&clock_mmss clk_mmss_camss_csi1phytimer_clk>,

			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csiphy_clk_src>,

			<&clock_mmss clk_mmss_camss_csiphy1_clk>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

		status = "ok";

	};



	qcom,csiphy@ca36000 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";

		reg = <0xca36000 0x1000>;

		reg-names = "csiphy";

		interrupts = <0 80 0>;

		interrupt-names = "csiphy";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,

			<&clock_mmss clk_mmss_camss_ahb_clk>,

			<&clock_mmss clk_mmss_camss_top_ahb_clk>,

			<&clock_mmss clk_csi2_clk_src>,

			<&clock_mmss clk_mmss_camss_csi2_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid2_clk>,

			<&clock_mmss clk_csi2phytimer_clk_src>,

			<&clock_mmss clk_mmss_camss_csi2phytimer_clk>,

			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csiphy_clk_src>,

			<&clock_mmss clk_mmss_camss_csiphy2_clk>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

		status = "ok";

	};

};

arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
 */



#include "msmcobalt.dtsi"

#include "msmcobalt-v2-camera.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSMCOBALT v2";

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h

0 → 100644
+160 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef MSM_CSIPHY_5_0_1_HWREG_H

#define MSM_CSIPHY_5_0_1_HWREG_H



#define ULPM_WAKE_UP_TIMER_MODE                   2



#include <sensor/csiphy/msm_csiphy.h>



struct csiphy_reg_parms_t csiphy_v5_0_1 = {

	.mipi_csiphy_interrupt_status0_addr = 0x8B0,

	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.combo_clk_mask = 0x10,

};



struct csiphy_reg_3ph_parms_t csiphy_v5_0_1_3ph = {

	/*MIPI CSI PHY registers*/

	{0x814, 0xD5},

	{0x818, 0x1},

	{0x188, 0x7F},

	{0x18C, 0x7F},

	{0x190, 0x0},

	{0x104, 0x6},

	{0x108, 0x1},

	{0x10c, 0x12},

	{0x114, 0x20},

	{0x118, 0x3E},

	{0x11c, 0x41},

	{0x120, 0x41},

	{0x124, 0x7F},

	{0x128, 0x0},

	{0x12c, 0x0},

	{0x130, 0x1},

	{0x134, 0x0},

	{0x138, 0x0},

	{0x13C, 0x10},

	{0x140, 0x1},

	{0x144, 0x12},

	{0x148, 0xFE},

	{0x14C, 0x1},

	{0x154, 0x0},

	{0x15C, 0x23},

	{0x160, ULPM_WAKE_UP_TIMER_MODE},

	{0x164, 0x00},

	{0x168, 0xA0},

	{0x16C, 0x25},

	{0x170, 0x41},

	{0x174, 0x41},

	{0x178, 0x3E},

	{0x17C, 0x0},

	{0x180, 0x0},

	{0x184, 0x7F},

	{0x1cc, 0x41},

	{0x81c, 0x2},

	{0x82c, 0xFF},

	{0x830, 0xFF},

	{0x834, 0xFB},

	{0x838, 0xFF},

	{0x83c, 0x7F},

	{0x840, 0xFF},

	{0x844, 0xFF},

	{0x848, 0xEF},

	{0x84c, 0xFF},

	{0x850, 0xFF},

	{0x854, 0xFF},

	{0x28, 0x0},

	{0x800, 0x0},

	{0x4, 0xC},

	{0x8, 0x14},

	{0x8, 0x14},

	{0x10, 0x52},

	{0x14, 0x60},

	{0x14, 0x60},

	{0x1C, 0xa},

	{0x1c, 0xa},

	{0x38, 0x1},

	{0x3C, 0xB8},

	{0x3C, 0xB8},

	{0x14, 0x0},

	{0x14, 0x0},

	{0x700, 0xC0},

	{0x150, 0},

	{0x1dc, 0x51},

	{0x2C, 0x1},

	{0x34, 0xf},

	{0x728, 0x4},

	{0x0, 0x91},

	{0x70C, 0xA5},

	{0x38, 0xFE},

	{0x81c, 0x6},

};



struct csiphy_settings_t csiphy_combo_mode_v5_0_1 = {

	{

		{0x818, 0x1},

		{0x81c, 0x2},

		{0x004, 0x08},

		{0x704, 0x08},

		{0x204, 0x08},

		{0x404, 0x08},

		{0x604, 0x08},

		{0x02c, 0x1},

		{0x22c, 0x1},

		{0x42c, 0x1},

		{0x62c, 0x1},

		{0x72c, 0x1},

		{0x034, 0x0f},

		{0x234, 0x0f},

		{0x434, 0x0f},

		{0x634, 0x0f},

		{0x734, 0x0f},

		{0x01c, 0x0a},

		{0x21c, 0x0a},

		{0x41c, 0x0a},

		{0x61c, 0x0a},

		{0x71c, 0x0a},

		{0x014, 0x60},

		{0x214, 0x60},

		{0x414, 0x60},

		{0x614, 0x60},

		{0x714, 0x60},

		{0x728, 0x4},

		{0x428, 0x0a},

		{0x628, 0x0e},

		{0x03c, 0xb8},

		{0x73c, 0xb8},

		{0x23c, 0xb8},

		{0x43c, 0xb8},

		{0x63c, 0xb8},

		{0x000, 0x91},

		{0x700, 0x80},

		{0x200, 0x91},

		{0x400, 0x91},

		{0x600, 0x80},

		{0x70c, 0xA5},

		{0x60c, 0xA5},

		{0x010, 0x52},

		{0x710, 0x52},

		{0x210, 0x52},

		{0x410, 0x52},

		{0x610, 0x52},

		{0x038, 0xfe},

		{0x738, 0x1f},

		{0x238, 0xfe},

		{0x438, 0xfe},

		{0x638, 0x1f},

	}

};

#endif

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+16 −6
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "include/msm_csiphy_3_4_2_hwreg.h"

#include "include/msm_csiphy_3_5_hwreg.h"

#include "include/msm_csiphy_5_0_hwreg.h"

#include "include/msm_csiphy_5_0_1_hwreg.h"

#include "cam_hw_ops.h"



#define DBG_CSIPHY 0
@@ -40,7 +41,8 @@ 
#define CSIPHY_VERSION_V32                        0x32

#define CSIPHY_VERSION_V342                       0x342

#define CSIPHY_VERSION_V35                        0x35

#define CSIPHY_VERSION_V50                        0x50

#define CSIPHY_VERSION_V50                        0x500

#define CSIPHY_VERSION_V501                       0x501

#define MSM_CSIPHY_DRV_NAME                      "msm_csiphy"

#define CLK_LANE_OFFSET                             1

#define NUM_LANES_OFFSET                            4
@@ -766,7 +768,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, 


	if (csiphy_dev->hw_version >= CSIPHY_VERSION_V30 &&

		csiphy_dev->clk_mux_base != NULL &&

		csiphy_dev->hw_version != CSIPHY_VERSION_V50) {

		csiphy_dev->hw_version < CSIPHY_VERSION_V50) {

		val = msm_camera_io_r(csiphy_dev->clk_mux_base);

		if (csiphy_params->combo_mode &&

			(csiphy_params->lane_mask & 0x18) == 0x18) {
@@ -789,7 +791,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, 
			rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev,

				csiphy_dev->csiphy_3p_clk_info,

				csiphy_dev->csiphy_3p_clk, 2, true);

			if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)

			if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)

				rc = msm_csiphy_3phase_lane_config_v50(

					csiphy_dev, csiphy_params);

			else
@@ -797,7 +799,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, 
					csiphy_params);

			csiphy_dev->num_irq_registers = 20;

		} else {

			if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)

			if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)

				rc = msm_csiphy_2phase_lane_config_v50(

					csiphy_dev, csiphy_params);

			else
@@ -1201,7 +1203,7 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg) 
		msm_camera_io_w(0x0,

			csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_cmn_ctrl6.addr);

		if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)

		if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)

			msm_camera_io_w(0x0,

				csiphy_dev->base +

				csiphy_dev->ctrl_reg->csiphy_3ph_reg.
@@ -1312,7 +1314,7 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg) 
		msm_camera_io_w(0x0,

			csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_cmn_ctrl6.addr);

		if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)

		if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)

			msm_camera_io_w(0x0,

				csiphy_dev->base +

				csiphy_dev->ctrl_reg->csiphy_3ph_reg.
@@ -1694,6 +1696,14 @@ static int csiphy_probe(struct platform_device *pdev) 
		new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;

		new_csiphy_dev->ctrl_reg->csiphy_combo_mode_settings =

			csiphy_combo_mode_v5_0;

	} else if (of_device_is_compatible(new_csiphy_dev->pdev->dev.of_node,

		"qcom,csiphy-v5.01")) {

		new_csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_v5_0_1_3ph;

		new_csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v5_0_1;

		new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V501;

		new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;

		new_csiphy_dev->ctrl_reg->csiphy_combo_mode_settings =

			csiphy_combo_mode_v5_0_1;

	} else {

		pr_err("%s:%d, invalid hw version : 0x%x\n", __func__, __LINE__,

		new_csiphy_dev->hw_dts_version);