Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

This project is archived. Its data is read-only.

Commit 25804d81 authored Sep 21, 2012 by Wei Ni Committed by Stephen Warren Nov 05, 2012

ARM: tegra: set up wlan clocks for tegra dt



Set up the wlan clock tree for Tegra20 and Tegra30.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

parent bb1de887

arch/arm/mach-tegra/board-dt-tegra20.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -102,8 +102,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
		{ "pll_a", "pll_p_out1", 56448000, true },
		{ "pll_a_out0", "pll_a", 11289600, true },
		{ "cdev1", NULL, 0, true },
		{ "blink", "clk_32k", 32768, true },
		{ "i2s1", "pll_a_out0", 11289600, false},
		{ "i2s2", "pll_a_out0", 11289600, false},
		{ "sdmmc1", "pll_p", 48000000, false},
		{ "sdmmc3", "pll_p", 48000000, false},
		{ "sdmmc4", "pll_p", 48000000, false},
		{ NULL, NULL, 0, 0},
		};

arch/arm/mach-tegra/board-dt-tegra30.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -61,11 +61,15 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
		{ "pll_a_out0", "pll_a", 11289600, true },
		{ "extern1", "pll_a_out0", 0, true },
		{ "clk_out_1", "extern1", 0, true },
		{ "blink", "clk_32k", 32768, true },
		{ "i2s0", "pll_a_out0", 11289600, false},
		{ "i2s1", "pll_a_out0", 11289600, false},
		{ "i2s2", "pll_a_out0", 11289600, false},
		{ "i2s3", "pll_a_out0", 11289600, false},
		{ "i2s4", "pll_a_out0", 11289600, false},
		{ "sdmmc1", "pll_p", 48000000, false},
		{ "sdmmc3", "pll_p", 48000000, false},
		{ "sdmmc4", "pll_p", 48000000, false},
		{ NULL, NULL, 0, 0},
		};